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					                 CR Framework Simulink
                        Clocking
                                  WINLAB – Rutgers University
                                      Date : July 26 2010
Authors :
Prasanthi Maddala, prasanthi.m@gmail.com
Khanh Le, kle@winlab.rutgers.edu
CR Framework R3 Architecture
Clocks
n   Ethernet clock
n   DAC IF clock
n   DAC ref clock
n   ADC IF clock                          125 MHz   100 MHz   100 MHz            25 MHz
                                                    CE : 4    CE : 4
n   Pkt. Proc. (2)
n   App (2)
n   Control Plane
Simulink Clocking Options
n   Clock Enables (Default)
                                                                        50 MHz
n   Hybrid DCM – Clock Enable
n   Expose Clock Ports
n   Fake Clock Ports (?)



                                100 MHz
Clock Enables

n   Multiple subsystem generator, with 2 subsystems
n   Can not generate DAC IF and ADC IF clocks.
n   Will more subsystems help - yes, but the generated rtl has to be combined with clk gen. code.
Hybrid DCM - CE

n   Multiple subsystem generator, with 2 subsystems
n   Hybrid DCM – CE generates up to 3 clks. Rest of the clks are clk enabled. 3 highest frequencies are generated
    using DCM.
n   Can not generate same frequency with both DCM and clock enable
     Ex: ADC IF clk = 25 MHz. App Clk = 25 MHz - 100 MHz with clock enable
n   Xilinx core FIFOs have to be imported as black boxes (to be used as Sync FIFOs between App and DAC/ADC
    IFs).
n   Works well if only 3 clocks are required
Expose Clock Ports

n   Need not use Multiple Subsystem generator.
n   Xilinx core FIFOs have to be imported as black boxes (to be used as Sync FIFOs).
n   Generated rtl code has to be combined with a clock generation code to get the bit stream.
n   System clock – 500 MHz (LCM of all the clocks)
n   Easy for Modelsim co-simulation ?

				
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posted:7/24/2013
language:English
pages:5