Analog and digital electronics developments

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					Analog and digital electronics developments
Analog electronics

Saclay-Irfu engineers: Ph. Abbon, E. Delagnes, H. Deschamps, P. Kestener Irfu physicists: J.-M. Le Goff, Ch. Magneville, J. Rich, Ch.Y. Orsay-LAL engineers:Ch. Beigbeder, D. Breton, T. Caceres, D. Charlet, B. Mansoux, C. Pailler, M. Taurigna LAL physicists: R. Ansari, M. Moniez N5055

Outline  Analog electronics  Clock distribution  Digital electronics  Test in Nançay (NRT)

Clock distribution

500MHz ADC board

PCI-express board

Ch. Yèche CEA-Saclay, Irfu/SPP

Fermilab, 21cm BAO Meeting, July 10th 2008

Introduction

Ch Yèche

Analog and digital electronics

July 10, 2008

2

Goals and Strategy
 Develop a multi-channel, full digital system for radio

interferometers in the 500 - 1500 MHz spectral bands
 Covering very large bandwidth ( 250 MHz) at once  Analog amplification / filtering / down conversion sub-system  Clock distribution sub-system  Fast digitization sub-system, with the ability to perform on

the fly frequency component separation (FFT …) reception sub-system

 High capacity optical digital link and PCI-Express data
 PC-cluster based acquisition and data processing system
Ch Yèche Analog and digital electronics July 10, 2008

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The engineering Team
(LAL-Orsay, Irfu-Saclay)
 E. Delagnes, P. Abbon, H. Deschamps (Analog sub-

system, clock distribution ( hardware, firmware & control program))
 D. Breton, C. Beigbeder, T. Caceres, D. Charlet (ADC

board, PCI-Express board, electronics and firmware)
 B. Mansoux, C. Pailler, M. Taurigna

(Software/Acquisition, PCI-Ex. drivers)
 P. Kestener (on the fly FFT on the ADC board)

Ch Yèche

Analog and digital electronics

July 10, 2008

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Electronics chain
…

X4

…

PC
……
Down conversion filtering 2nd

…

128 dipoles

Antenna board 4 dipoles

……

…

X4

Down conversion filtering

……

Antenna board 4 dipoles

X4

ADC (500 MHz) 4 channels

Time FFT FPGA

2nd

Clock distribution

ADC (500MHz) 4 channels

……

X8

Spatial FFT (FPGA)

Time FFT FPGA

PC
Ch Yèche Analog and digital electronics July 10, 2008

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Analog Electronics

Ch Yèche

Analog and digital electronics

July 10, 2008

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Analog Electronics
Goals:
 Filtering and down conversion: Shift from 1.5 GHz signal to a 0-250 MHz window.  2nd stage amplifier up to 650 mV (signal input for ADC) Two boards have been developed  “LO” board: LO clock and splitter  “RF” board: Amplifier + Mixer

LO board

RF board

Ch Yèche

Analog and digital electronics

July 10, 2008

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Analog chain for the RF prototype Board
Gain=20DB

Antenna board
LNA LNA Summer LNA LNA

75 Ω 40m

RF Prototype Board
Pass band Filter Gain=19DB
RF 2 RF RFout LO=1.2GHZ Gain=20DB IF: Intermediate frequency 1 Mixer IF IF Low pass Filter Low-pass Filter

50 Ω 1-2m
ADC
FPGA

Local Oscillator

RF amplifier, mixer

LO Prototype Board
Master Frequency 50MHz PLL LO=1.2GHZ RF Splitter 1/8 1 2 3 4 5 6 7 8

Phase-locked loop

RF board:  75/50 inputs  2 channels per board  Possibility of by-passing mixer to test the under-sampling approach.
Ch Yèche Analog and digital electronics

Front panel plug-in (3U EuroCard)
July 10, 2008

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Tunable pass band filters
 Developments of LC filters with connectors  Very easy to tune the filter width  Should be very convenient for Nançay and Pittsburgh tests

C2

C4

C6

C1

L1 C3

L2 C5

L3 C7

Ch Yèche

Analog and digital electronics

July 10, 2008

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Clock Distribution

Ch Yèche

Analog and digital electronics

July 10, 2008

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Goals:

Clock Distribution

 Synchronization of the interferometer clock  Clock Distribution for ADC boards and for Local Oscillator boards  Clock & commands encoded on optical fiber ( slow-control & configuration capability )  Define Trigger (Sampling start) and Reset for ADC boards  Configuration byte transmitted to ADC with trigger (On/Off..)  Use of external rubidium master clock (specific to Nançay)

Status:

 A prototype (Transmitter  Receiver)  Easy extension to several crates (connection with optical fiber)  Successful tests in labs  The definition of configuration bytes finalized for Nançay  Need to be discussed for Pittsburgh
Ch Yèche Analog and digital electronics July 10, 2008

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Digital Electronics

Ch Yèche

Analog and digital electronics

July 10, 2008

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500MHz ADC board
 First 2 prototype ADC boards have been manufactured and delivered to LAL (end of april)
 Each ADC board has :  4 input channels (digitized at
ADC + Stratix bloc

Input analog channels (4)

ADC + Stratix bloc

500 MHz max)

 Input clock + control

Optical digital

(start/stop…) ports port (for control)

 USB, and VME communications  2 high speed (4.8 Gbit/s)

Control FPGA

outputs (2)

USB port

optical outputs (data links to PCI-express boards)
Ch Yèche Analog and digital electronics July 10, 2008

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500MHz ADC board
 Tests of the ADC by using a fiber between the two FPGA with the two receivers  Successful tests: see below fin= 3MHz Amp= 500mV Fiber: 4Gbit/s

FFT (2048 hits)
250 MHz

Signal
Ch Yèche Analog and digital electronics July 10, 2008

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ADC board: More tests
 Tests for different frequencies

fin= 10MHz Amp= 200mV (-10dBm) Fiber: 5Gbit/s

FFT (2048 hits)
250 MHz

Signal
Ch Yèche Analog and digital electronics July 10, 2008

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ADC board: More tests
 Tests for different frequencies

fin= 180MHz Amp= 200mV (-10dBm) Fiber: 5Gbit/s

FFT (2048 hits)
250 MHz

Signal
Ch Yèche Analog and digital electronics July 10, 2008

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ADC board: Under-sampling
 Tests for different frequencies  Under-sampling up to 750 MHz

fin= 300MHz Amp= 200mV (-10dBm) Fiber: 5Gbit/s

FFT (2048 hits)
250 MHz

Signal
Ch Yèche Analog and digital electronics July 10, 2008

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ADC board: Noise level
 Only 6 ADC counts for signal  Noise floor is 50 dB below !!!

fin= 100MHz Amp= 20mV -30dBm Fiber: 5Gbit/s

FFT

250 MHz

Signal
Ch Yèche Analog and digital electronics July 10, 2008

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ADC board: Noise level
 Less than 1 bit for signal (0.6 ADC count)  Noise floor is still 25 dB below !!!  With averaging we can easily extract signal from the noise below the ADC count

fin= 100MHz Amp= 2mV -50dBm Fiber: 5Gbit/s

FFT

250 MHz

Signal
Ch Yèche Analog and digital electronics July 10, 2008

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PCI-express board
Pattern generator

Fifo 1024
ST ST MM ctrl MM Ms MM ctrl MM S MM S MM S

Ram 15k

FPGA

Successful tests with pattern generator Transfer through DMA works  Connection between ADC optical link and FPGA transceiver is also OK

DMA Controller

MM Ms Rd MM Ms Wr MM S Ctrl

MM Ms Rd MM Ms Wr MM S Ctrl DMA Controller

PCIExpress 4x

MM Ms

MM MS

MM TX

Memory map data bus Memory map ctrl bus Streaming bus
Serdes Serdes Serdes Serdes

Ch Yèche

Analog and digital electronics

July 10, 2008

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PC Acquisition
Carte SLite / PCIe
FIFO 4KB

A D C

OR
pattern

DMA

Chip memory

Decode raw data

DMA
~320MB/s

Read DMA

T1 T2 T3 T4

Raid 0 1TBytes
(8 SATA HD)

Simulated data are successfully recorded on disks and reread from disks

Store Data

600000

DoFFT

500000

Configure Acq

400000

300000

PC Acquisition
Ch Yèche

Multi-Thread Acquisition

200000

Averaged speed on disk ~ 420 MB/s
1 103 205 307 409 511 613 715 817 919 1021 1123 1225 1327 1429 1531 1633 1735 1837 1939

Série1

100000

0

Analog and digital electronics

July 10, 2008

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Test with Nançay Radio Telescope (NRT)

Ch Yèche

Analog and digital electronics

July 10, 2008

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Test with NRT
Strategy
 Equipment of one of the two RT dipoles with our electronic chain directly in the focal carriage  Observation in parallel with the other channel.  Comparison with “standard” RT channel.  Final goal : Write on disk with wide band 250MHz and with an optical link at 4Gb/s

Two tests campaigns:
 Dec. 2007: Tests of the analog electronics and clock distribution system  Summer 2008: Tests of the final ADC boards and PCI-express boards (July 16-17 and July 21)
Ch Yèche Analog and digital electronics July 10, 2008

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North

Focal carriage South Secondary spherical reflector

Nançay Radio Telescope
July 10, 2008

Primary flat reflector
Ch Yèche Analog and digital electronics

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Test of analog electronics (Dec. 2007)
Goals and Strategy:  Test of the electronics chain  Test of the analog part with “home made” 14 bit ADC (LAL and Saclay) (see matacq Doc. at http://matacq.free.fr/)  In parallel with Nancay RT Chain (electronics and acquisition)  Configuration: • Sampling: 500 MHz • Window width: 250 MHz • Local oscillator: 1250 MHz • Number of points per bunch: 2560  5s • Speed read-out 3ms  99.9% of dead time  Observation of a few galaxies in On/Off mode
Ch Yèche Analog and digital electronics July 10, 2008

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Inside the focal carriage
Amplified signal from dipole ~1/10 of the signal Matacq Board

LO Board

RF Board

Nançay electronics crate
Ch Yèche Analog and digital electronics July 10, 2008

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Observed Spectrum at Nançay RT
Results:  2 days of test during maintenance period of NRT  Electronics worked out of the box!!!  Unfortunately, due to the huge dead time we have only 1-2s of integrated observation time  Observation of local HI

Ch Yèche

Analog and digital electronics

July 10, 2008

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Extragalactic HI

NGC6822 Vrad=-58km/s m12=8.96  HI flux = 20 Jy
Ch Yèche

NGC6384 Vrad= 1665 km/s m12=13.14  HI flux = 0.3 Jy
Analog and digital electronics July 10, 2008

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Conclusions

Ch Yèche

Analog and digital electronics

July 10, 2008

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Conclusions
 Successful tests of the analog electronics at NRT  Successful tests of the analog electronics + ADC board in lab  Yesterday, successful tests of the chain ADC board + PCI-express board + DMA + PC in lab Transfer on PC with DMA is OK  Write data on disk at ~300 MByte/s  Almost ready for a new campaign of tests in Nançay (next weeks in July)  Goal: write on disk with a wide band (250 MHz) and a speed around ~1-2 Gbit/s and observation of local HI or/and extra-galactic HI : dead time ~50%
Ch Yèche Analog and digital electronics July 10, 2008

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Future plans
 New campaign in September at NRT Goal: several ADC boards, automatic acquisition system with clock distribution and on fly FFT  First tests (1-2 boards) in Pittsburgh planned in fall/end of 2008  Version 2 of ADC boards and development of PCI-express boards  Plan (and budget) to build 10-16 boards (up to 64 channels) in 2009  Multi-channel (32/64) tests in Pittsburgh in 2009  Equipment of the prototype of NRT Focal Plane Array with our electronics in early 2009  Development of correlator prototype with FPGA architecture
Ch Yèche Analog and digital electronics July 10, 2008

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