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					Design Examples                                                 J. Silva-Martinez




       Wideband Continuous-Time Multi-Bit
               Delta-Sigma ADCs
                          Jose Silva-Martinez

    Thanks to All our Graduate Students that generate these ideas and
       make possible to test the concepts, and report them in the
   ISSCC-2009, and JSSC: June 2010, September 2010 and March 2011.


     Texas A&M University
     Department of Electrical and Computer Engineering
     Analog and Mixed-Signal Center
     March, 2012
                                         1
                              Outline
Design Examples                                          J. Silva-Martinez




            •  Introduction

            •  Design techniques for a 3th order Low-
               Power 10MHz Low-Pass ΣΔ ADC in 65nm
               Technology

            •  Design techniques for a 5th Order 25MHz
               ΣΔ ADC with SNDR>68 dB

            •  Conclusions



                                 2
Design Examples                                                                  J. Silva-Martinez


                  Introduction: Connectivity
                                   WLAN
                                UWB, 802.15.3a

                                                                       WI-FI
                                                                       MAN
                                                                      Wi-Max,
                                                                     802.16a,e




                   GPS




                                                               BLUETOOTH
                                                               PAN, 802.15

                                             Connectivity to
                                             EVERYTHING

      v  Increasing number of wireless standards
      v  Support of multiple-standards on the same chip
      v  Advances in Integrated RF design towards universal devices
      v  Software Radio: easy addition of new standards
                                           3
Design Examples                                                         J. Silva-Martinez


         Introduction: Design considerations

   v    Numerous systems will be included into the next generation receiver.
           - Cell phone standards (GSM, WCDMA, DECT, EDGE etc)
           - Communication network (802.11 a/b/g, bluetooth, WiMax, UWB etc)
           - Satellite services (GPS)

   v    Different technologies are used to achieve the receiver
            - CMOS, BiCMOS, III-IV Compounds (GaAs, InP, etc.)

   v    Strong push to the digital domain
            - Digital circuit: accurate & robust

   v    In a complete System-on-Chip: 90% is digital circuitry
            - only 10% is analog

   v    Variations of receiver architecture are proposed.
            - Direct conversion, software-radio, High-IF receiver
                                            4
Design Examples                                                J. Silva-Martinez


       Motivation
  •  Low power, low cost WLAN ADC for
     ultra-mobiles

  •  Conventional ADC architectures are
     often unsuitable for nanometric
     technologies (feature size <100nm)

  •  New architecture for low power
     ADC compatible with nanometric      Internet surfing on mobile device
     technology is desired
                              20MHz BW, >12bit ADC




                                     5
                                                           5
Design Examples                                                          J. Silva-Martinez

             Existing Solutions for Baseband ADC


  •  ΔΣ architecture is preferred for nanometric digital
     technology
       –  Does not rely on component matching and complex analog
          circuits
       –  Digital decimation filter scales well with technology
  •  1-bit ΔΣ impractical for wideband application
       –  Order of modulator is limited by overloading effects
       –  Large Over Sampling Ratio (OSR) increases power dissipation
  •  Typical Multi-bit ΔΣ architecture gives up “Digital
     friendly” advantages
       –  Front-end filter and feedback DAC linearity are major issues

                                         6
Design Examples                                                                                J. Silva-Martinez


                      State-­‐of-­‐the-­‐art	
  and	
  Target	
  

                                               Sigma-­‐Delta	
  ADC	
  
                                               • 	
  Power	
  efficient	
  and	
  cost	
  effec8ve	
  
                                               • 	
  Inherent	
  “anG-­‐aliasing”	
  filtering	
  
                  Target                       • 	
  Digital	
  post-­‐processing	
  capability	
  

                                                    On-­‐going	
  research	
  
                                               • 14	
  bit,	
  20MHz	
  ADC	
  in	
  90nm	
  
                                               technology	
  with	
  auto-­‐calibra8on	
  
                                               • 	
  Total	
  Power	
  consump8on	
  <	
  50	
  mW	
  
                                               • 	
  Robust	
  performance	
  with	
  on-­‐chip	
  	
  
                                               	
  	
  master	
  clock	
  having	
  5-­‐10	
  psec	
  	
  ji=er	
  
                                               • 	
  Figure	
  of	
  merit	
  in	
  the	
  range	
  of	
  	
  
                                               	
  	
  250	
  fJ/conversion	
  step	
  



                                          7
                                                                                                      7
Design Examples                                                                                          J. Silva-Martinez


                  Direct	
  Conversion	
  MulG-­‐Standard	
  Receiver	
  




       System	
  issues	
  in	
  broadband	
  systems:	
  
       High	
  frequency	
  filtering	
  is	
  especially	
  criGcal	
  in	
  broadband	
  applicaGons	
  
       RejecGon	
  of	
  Blockers:	
  ADC	
  filtering	
  must	
  be	
  complemented	
  by	
  LP	
  filtering	
  
       Neighbor	
  channels	
  are	
  quite	
  relevant	
  even	
  if	
  heavy	
  filtering	
  is	
  used	
  
       	
  
       Trade-­‐offs:	
  
       Light	
  filtering	
  in	
  front	
  demands	
  an	
  ADC	
  with	
  higher	
  SNR	
  and	
  higher	
  SDR	
  
       Higher	
  SNDR-­‐ADC	
  implies	
  more	
  power	
  and	
  more	
  circuit	
  complexity 	
  	
  
                                                           8
             Design issues in Low-pass ΣΔ ADC
Design Examples                                                                           J. Silva-Martinez




                            Vin + Qn                               Dout = STF * Vin + NTF * Qn
Error = Vin − Vout =                        = NTF * (Vin + Qn)
                       1 + Loop _ Gain( s )
                                                                                1
                                 Qn
                                                                 NTF =
                                                                       1 + Loop _ Gain( s )
                                       Quantizer
                                                                              H( s )
                                                                 STF =                      = NTF * H ( s )
       Vin         H(s)                            Dout                1 + Loop _ Gain( s )

                  Loop Filter                              H(s)
                                                                                   Internal issues
                                DAC                         Biq1
  Vin
H(s)
                                      Qn                   NTF

                                           NTF gain increases at high frequency
                                           HF Power at filter input maybe excessive
         Error Signal
                                           Error signal is mainly at high frequency
                                           and the filter must deal with that!
                                                    9
Design Examples                                                                                                 J. Silva-Martinez


              Blocker	
  RejecGon:	
  Feedforward	
  vs.	
  Feedback	
  




  Input	
  signal:	
  Weak	
  in-­‐band	
  component	
  (-­‐43dBFS	
  @12MHz)	
  and	
  a	
  strong	
  out-­‐of-­‐band	
  
  component	
  (-­‐6dBFS	
  @395MHz).	
  Clock	
  frequency	
  =	
  400MHz.	
  	
  
  In-­‐band	
  alias	
  signal	
  at	
  5	
  MHz.	
  
  Feedback	
  architecture	
  clearly	
  has	
  significant	
  advantages:	
  
  • 	
  Excellent	
  Blocker	
  RejecGon	
  :	
  Feedback	
  STF	
  provides	
  Nth	
  order	
  filtering	
  for	
  blockers	
  
  • 	
  Improved	
  Dynamic	
  Range:	
  Be=er	
  filtering	
  of	
  out-­‐of-­‐band	
  channels	
  reduces	
  input	
  power	
  
  in	
  filter	
  stages	
                                      10
Design Examples                                                                                                                J. Silva-Martinez


        Ji=er	
  InsensiGvity	
  of	
  Switched-­‐Capacitor	
  DACs	
  
Non-­‐Return-­‐to-­‐Zero	
  vs.	
  Switched-­‐Capacitor	
  




                              Ji=er	
  error	
  




  • 	
  Clock	
  ji=er	
  causes	
  a	
  variaGon	
  in	
  the	
  width	
  of	
  the	
  feedback	
  pulse	
  resulGng	
  in	
  a	
  random	
  
  variaGon	
  in	
  the	
  amount	
  of	
  charge	
  fed	
  back	
  per	
  clock	
  cycle	
  

  • 	
  Ji=er	
  noise	
  is	
  directly	
  proporGonal	
  to	
  ji=er	
  variance	
  and	
  DAC	
  pulse	
  magnitude	
  	
  

  • 	
  Switched	
  Capacitor	
  (SC)	
  DACs	
  present	
  excellent	
  ji=er	
  performance	
  but	
  demands	
  large	
  
  slew-­‐rate	
  and	
  faster	
  OPAMPs	
  
                                                                       11
Design Examples                                                                              J. Silva-Martinez

       Strategy for nanometric technologies


•  Make use of time domain                Vdd                                 Vdd
   signal representation

•  Small supply voltage limits                                   VQ
   the dynamic range of
                                                   0                                  0             Ts
   analog signals                                                                           TQ


                                   Amplitude




                                                                      Amplitude
•  Fast switching gates
   provide fine time precision,
   which provide alternate
   means for high DR signal
                                                   2Ts         time
                                                         4Ts




                                                                                      2Ts
                                               0                                  0               time




                                                                                            4Ts
   representation

•  Also takes advantage of
   CV2f                           Time domain signal representation

                                               12
Design Examples                                             J. Silva-Martinez




         A 20MHz Signal Bandwidth 68dB Dynamic
         Range Continuous Time ΔΣ ADC Based On
              Multi-bit Time Domain Quantizer and
                         Feedback Element
           V. Dhanasekaran, et.al. ISSCC-2009; JSSC March 2011




                                   13
Design Examples                                                                                                                              J. Silva-Martinez


                          Proposed ADC Architecture
                                                                                                   PWM Generator    CLK
                  Loop Filter   Multi-bit Quantizer                             Loop Filter
                                                                                                                                                          Digital
Vin                                                   Dout   Vin   +                                THA                               Dout   Decimation
                                                                                                                                                          Output
  +
          S                                                               S                                                TDC &
      -                                                                                                                                          Filter
                                                                       -                                                  Digital Logic
                            CLK                                                    CLK                ò

                          Multi-bit
                                                                                                       1-Level
                                                                                                                                          P(t)
                           DAC
                                                                                                        DAC
                                                                                                                   Time Quantized PWM


                Conventional ΔΣ	

                                                     Time domain Quantizer-DAC	



           •     Multi-level quantizer and Digital to Analog Converter (DAC) is replaced
                 by PWM generator and Time to Digtal Converter (TDC)

           •     Width of p(t) is proportional to the amplitude of the signal in a given
                 clock period

           •     Output code (Dout) represents “quantized pulse” edges with a
                 quantization step size = TQ
                                                                                              14
Design Examples                                                                                  J. Silva-Martinez
                                                                  Loop Filter

 Why ΔΣ Noise Shaping
                                                      +                         PWM Gen                      Dout
                                                Vin           Σ
                                                                                                   TDC
                                                          -                               p(t)
                                                                                ∫
                                                                          CLK
                                                                                                     pq(t)



    •  PWM + TDC cannot achieve necessary performance
          –  Timing edges are precise to sub-pS level but resolution is limited
          –  Typical TDC resolution is about 1 inverter delay (~15pS in 65nm
             technology)
          –  Difficult to achieve good linearity of PWM at this speed
    •  Noise shaping is used to overcome limited time resolution of
       TDC
          –  Time quantization results in quasi-white noise that can be shaped
             by the loop filter
          –  Precise timing edges (standard deviation < 800fS), required for the
             feedback path, is achieved by using matched delay elements
    •  Loop filter serves to suppress the quantization noise
       introduced by the TDC and the non-linearity of the PWM
                                          15
Design Examples                                                        J. Silva-Martinez


            Merits of the Proposed Approach

  •  Flash ADC and Multi-level                             Multi-bit   Proposed
     DAC is replaced by PWM
                                           Low OSR
     Generator & TDC
                                            design           J           J 
  •  The TDC is implemented by
     digital circuits, which takes        Small supply
     advantage of technology                voltage          L           K 
     scaling
                                          DAC linearity
  •  Feedback signal is
     inherently linear and is                                L           J 
     ultimately limited by timing
                                          Sensitivity to
     precision
  •  Reduced sensitivity to clock
                                           clock jitter      L           J 
     jitter


                                     16
Design Examples                                            J. Silva-Martinez


        Full System Simulation




        •  System level design and simulation of the proposed
           architecture was performed using SIMULINK
        •  Transistor level simulations were performed using
           TISPICE, SPECTRE and FINESIM simulators
                                  17
Design Examples                                                                       J. Silva-Martinez

                       PWM Generator
                                                              Loop Filter
                                                  +                         PWM Gen                   Dout
                                            Vin           Σ
                                                                                             TDC
                                                      -                               p(t)
                                                                            ∫
                                                                      CLK
                                                                                              pq(t)




     •  PWM signal generated by standard method - comparing signal with
        triangle waveform

     •  Double-sampled or “asymmetric sampled” PWM is used to minimize
        distortion and improve OSR

     •  Performance is relaxed due to noise shaping
                                      18
Design Examples                                                        J. Silva-Martinez

                        TDC Functionality

         0 2 4 6 8 10 12 14
                                                               Drout    (6)
                                               TDC
                                                               Dfout   (11)
                            TQ
                    TCLK                       CLK

  •  TDC
       –  Converts pulse timing information to digital codes (Drout & Dfout)
       –  Drout & Dfout can be used to reconstruct signal in clocked digital
          domain
       –  Also generates a feedback pulse aligned to the timing edges
          represented by the dotted lines


                                        19
Design Examples                                                          J. Silva-Martinez


      TDC & Time quantized feedback pulse
                                               Binary code
•  Digital output code
                                                                  p(t)         D
                                                      2
                                                      6             CK0

    –  CT PWM output p(t) is latched by       TCLK
                                                                  RST
                                                                               D
       delayed versions of the clock                                 CK1

    –  Flipflop outputs provide                           pq(t)                D
                                                          p(t)       CK2
       “thermometer” coded pulse
       width                                         TQ
                                                                     CK3
                                                                               D

                                                           CK0
    –  D input of the flipflops are driven                 CK1    p(t)
       by p(t) to facilitate easy                          CK2
                                                                               D
                                                                    CK4
       generation of f/b pulse                             CK3    RST
                                                           CK4                 D
•  Feedback pulse - pq(t)                                  CK5       CK5
                                                           CK6
                                                                               D
    –  Must match output code                              CK7
                                                                     CK6

    –  Edges of pq(t) are always aligned                   RST                 D
       to the delayed clock edges                          RST       CK7


                                         20
Design Examples                                                           J. Silva-Martinez

              Time quantized pulse generator

                                                          Thermo-to-Bin
                                             p(t)     D

•  Pq(t) can be generated using a OR           CK0
                                             RST
                                                                              DRout

   gates and SR latch                                 D
                                                CK1
•  Pq(t) turns ‘High’ when the earliest of            D
                                                                      +

   CK0-3 goes High after p(t) is High           CK2

•  Pq(t) turns ‘Low’ when the earliest of             D
                                                CK3
   CK4-7 goes High after p(t) is Low                                          S
                                                                                       pq(t)
                                             p(t)                             R
                                                      D
                                               CK4
                                             RST
                                                      D
 •  Wired-NOR/NAND gate can be                  CK5
                                                                      +
    used to ensure uniform delay                      D
                                                CK6

                                                      D                       DFout
                                                CK7
                                                          Thermo-to-Bin

                                       21
Design Examples                                                                                                                              J. Silva-Martinez

                                              Full TDC Schematics
                                                                                             Pq(t)

                                                                                              S      R



                                                              25 Input OR Gate                                          25 Input OR Gate


                      CK3       CK4     CK5       CK6     CK7     CK8       CK9    CK10 CK11 CK12                       CK48    CK49    CK50 CK51 CK52

   P(t)                                                                                                  P(t)



          CK1   CK2       CK3     CK4       CK5         CK6     CK7   CK8    CK9      CK10                      CK46 CK47 CK48 CK49 CK50         CK51 CK52

            D     D         D         D       D           D       D     D         D      D                         D    D      D       D    D     D    D
  CLKIN
            1         2     3           4     5           6       7     8         9     10                        46   47      48      49   50    51 52


   •  50 levels of time steps are used in the proposed design for 20MHz ADC
   •  Clock phases are generated using cascade of delay elements that are
      tuned using a phase detector
                                                                                        22
 Design Examples                                                                            J. Silva-Martinez

                       Active-RC Topology Loop Filter
                              RF


                  Rq


                                   C2
                  C1                                         C3
Vin   R1
             _           R2
                                   _               R3
                                            V_lp             _
            +                                                          Vout
                                   +
                 A1    V_bp                                  +
                                       A2
                                              CB                  A3

                                       CH



                                                                          Noise Transfer Function
             Vout (s) 7.312s 2 + 2.312e17s + 4.223e25
      H(s) =         =                                                    (NTF)
             Vin(s)     s(s 2 + 1.414e7s + 1.279e16)

      •  The gain of the filter in the signal bandwidth (20MHz) serves to
         suppress the quantization noise of the TDC
      •  The filter has a minimum inband gain of 37dB

                                                        23
Design Examples                                                       J. Silva-Martinez



                  Mitigating Excess loop delay
                         FILTER




                                                 T
                                      PWM        D
                                                 C




                                     KFB path


            DAC




        Characterstics            Amplifier 1-2           Amplifier 3
             DC Gain              High (>30dB)        Moderate-low (20dB)
        Gain-Bandwidth     Moderate (150-250MHz)        High (>500MHz)
          Supply Noise            High (>40dB)             Moderate
           Rejection
 KFB provides a ‘fast path’ through INT3 => Make AMP3 a minimum phase structure
                                           24
Design Examples                                                                        J. Silva-Martinez


             Schematic: Amplifier1 / Amplifier2
                          VDD
                                                            Two Stage ‘Typical’ configuration
           Pbias                      Pbias
   M7                       M9                M8


           Vinp                      Vinm
                                                            •  maximizes gain of the initial
                    M1          M2             Voutm
                                                               stages => Better Q control
 Voutm

           Cc Rc                     Rc Cc
                                                            •  Output pole ~ 4*GBW
   M5                                          M6

           cmbias   M3          M4
                                     cmbias                 •  Overall noise limited by input
                                                               devices
                     Rf         Rf


                                                            •  Rf reduces (degenerate) noise
                          VSS                                  due to NMOS current mirrors
    Limitations:
       •  Parasitic poles result in additional loop delay/excess phase in
       the filter (could be > 10 deg at 500MHz)
       • Limits loop stability and affects the overall performance
                                                       25
Design Examples                                                     J. Silva-Martinez



Schematic: Amplifier 3
                    VDD
                                              •  A simple single stage
                                                 pseudo-differential ‘inverter
                                                 based’ amplifier
      Vinp            Vout           Vinm
                                              •  Complementary structure
                                                 with class A-B action

                                              •  CM noise (supply etc) is
                                                 suppressed by biquad gain
                    GND                          of 18dB
         Single Ended Schematic of Amp3

   Limitations:
         • Bias point not accurately controlled + % variation across
         statistical corner & Temp
         • Need for ‘Non-conventional’26common-mode control
Design Examples                                                 J. Silva-Martinez



           Amplifier 3 Common Mode control

                                     Icm

                           CB                C3

                           R3



                   From
                           CH              Amp3
                  Biquad


                           R3                              EA


                                              C3   Cmref
                                CB
                                     Icm




    •  Current sources at virtual ground control amplifier’s common mode

    •  Icm are: small current source, sized to meet transconductance and
    noise specifications               27
Design Examples                          J. Silva-Martinez


                       Chip Micrograph


•  Folded layout to
   minimize delay in
   feedback
•  Digital approach
   minimizes area
   requirement
•  Occupies 0.15mm2




                              28
Design Examples                                                                         J. Silva-Martinez

       Test Setup
            E4432B                               Pattern
                                                Generator
                                                                          16902A / 16950B
                                                16         CLK




                        LC-BPF     SE2DE
                                                     ADC         E5387A




                                                SAW Osc.
   •  LC Bandpass filter used to
      generate a clean input
      (remove noise and
      distortion from source)                    •  16950B LVDS input Logic
                                                    analyzer used to capture
   •  SAW Osc. used to generate
                                                    data @500MHz
      low jitter clock

                                           29              29
Design Examples                                                         J. Silva-Martinez


       Input Conditioning Filter
                                          Rt     L1     C1       C1   L1
  Source Performance                                                              Vo

  •  Noise floor = -125dBm/Hz                                                  Rt
                                                         L2    C2
  •  THD = -45dB

  Required Performance
                                      Discrete LC BPF
  •  Noise < -143dBm/Hz
                                 3rd order Chebyshev BPF centered at 4MHz
  •  THD < -70dB


                                Performance after filtering
                                •  Noise beyond 150KHz offset < -150dBm/Hz

                                •  Distortion < -75dB

                                            30          30
Design Examples                                                            J. Silva-Martinez


Single-ended to Differential Converter

   •  Differential opamp                                            C1

      with CM control
                           R1 = 300Ω                                R3
                                         Vi              R1
   •  Input resistance     Rt' = 60Ω                            _              Vo+
                                                          Vcm
      set to 50Ω           R2 = 360Ω          Rt'
                                                                +
                                                                         AD8138
                                                                               Vo-
                           R3 = 300Ω
      (Rt=Rt’||R1)                                  R2              R4
                           R4 = 300Ω

   •  R1+Rt’ = R2 to       Vcm = 0.45V
                                                                    C2
      eliminate offset

   •  1st order RC pole          •  Noise < -146dBm/Hz
      at ~30MHz
                                 •  THD < -85dB
                                  31                31
Design Examples                                                             J. Silva-Martinez


                   Clock Generation
                                                       Level Converter
•  Agilent clock generator                 CVS575
                                                              4V
   (E88440) RMS jitter = 20pS                                                    DUT
                                                                       Vb

•  Need clock jitter < 3pS-rms

•  CVS575 SAW Osc. provides                            25Ω         50Ω              50Ω
   low jitter (0.2pS-rms)
   LVPECL clock                   2.3 V                  CMOS levels
                                  1.65 V              1.2 V
•  On-PCB BJT diff.pair               LVPECL levels
   converts LVPECL to CMOS                            0V

   levels
                                 Diff pair bias adjusted to
                                 provide peak current swing
                                 of 50mA
                                     32
Design Examples                                         J. Silva-Martinez

       Test Setup Pictures

                                 Signal                Logic
                                 source                Analyzer
                                               PCB




           Power supplies


            Line filters
                                 Pattern Generator & LC-BPF
                            33
Design Examples                      J. Silva-Martinez


       PCB Pictures




        DC Regulators on
        bottomside of the PCB

                                34
Design Examples                             J. Silva-Martinez


           Output Spectrum: -5dB Input
                             •  Output spectrum for
                                -5dB 4MHz Input
                                signal




   •  SNR=62dB
   •  THD=65dB


                        35
Design Examples                     J. Silva-Martinez


         Output Spectrum : -30dB Input

  •  Output spectrum for
     -30dB 4MHz Input
     signal

  •  SNR=38.6dB

  •  THD=50.0dB

  •  Slight increase in
     noise floor due to
     loop delay variation
     with amplitude



                            36
Design Examples                                      J. Silva-Martinez


                     Dynamic Range


 •  DR = 68DB

 •  Peak SNDR=60dB
    @ -5dB input

 •  Peak THD=67dB @
    -6dB input



        Dynamic Range (DR) is defined as the amplitude
        range with SNR>0dB


                               37
Design Examples                                                   J. Silva-Martinez

          Comparison of 20MHz BW ΔΣ ADCs

                            Breems    Straayer * Malla    Proposed
                           ISSCC 07    VLSI 07 ISSCC 08     ADC
              SNDR (dB)      69            55     70        60

             Power (mW)      56            38    27.9      10.5

            Energy/Conv.     595       2058*     270        319
              (fJ/Step)
             Area (mm2)      0.5       0.19      1.0       0.15

             Output Rate     680           950   420        250
              (MSPS)

          * Uses VCO based time domain approach

                                      38
Design Examples                                            J. Silva-Martinez


                        Conclusions


   •  Demonstrated the suitability of time-to-digital converter
      based ADC in silicon
   •  Sub pico second time edge matching is experimentally
      proven
   •  Not just “works around” scaled technology limitations
      but leverages their strength
   •  Proposed a ADC solution for nanometric technologies




                                 39
Design Examples                                      J. Silva-Martinez




       25MHz Bandwidth (BW) Continuous-Time
      (CT) Lowpass (LP) ΣΔ Modulator with Time-
            Domain 3-bit Quantizer and DAC

                  Cho-Ying Lu, et.al., Sept 2010, JSSC




40                                 40
Design Examples                                                                                                                                         J. Silva-Martinez


                                                           System Architecture
                                                                                                             Φ1
                         RF                                                             RC
                                                                                                             Φ2
                          RQ
                                               C                                             C               Φ3                         •  5th-order 3-bit
                          C
                                                                                                                                           feedforward
                   Rin                RF                                      Rg
                         + -                 + -                                         + -
  IN                                                      OUTLP          IN                          OUT     Φ4
                         - +                 - +                                         - +
                   Rin     C
                           RQ
                                      RF
                                     OUTBP
                                               C
                                                                              Rg
                                                                                           C                 Φ5                            architecture
                                                                                                             Φ6
                                                                                         RC
                         RF
                                                                                                             Φ7
                                                                                                                                        •  Local feedback is
                                                                                                                                           to compensate the




                                                                                                                       Ts/7
                                                                                                                      2Ts/7
                                                                                                                      3Ts/7
                                                                                                                      4Ts/7
                                                                                                                      5Ts/7
                                                                                                                      6Ts/7
                                                                                                                  0




                                                                                                                        Ts
Vin +
                          nd                   nd                   st
                         2 -Order             2 -Order              1 -Order
                                                                                        b5                                                 excess loop delay
                                     LP




                                                          LP




      -                    Filter               Filter                    LP
                                                                                                             3-Bit Two-Step
                               BP                   BP                                                         Quantizer
                                                               b4
                                                                                                                              Digital
                                                                                                                              Output
                                                                     b3
                                                                              b2
                                                                                                 Σ                                      •  LC-VCO+CILFD are
                                                                                   b1                 3-Bit NRZ                  4
                                                                                                                                           used to generate
                                                                                                                                           clean reference
                                                                                                        DAC
                                           Complementary Injection-
                                           Locked Frequency Divider
                                                                                                                                           clocks
   1-Bit PWM DAC




                               VCO
                                                    CILFD

                                                         Programmable Delay
                                                                                                     Level-to-PWM
                                               1                                        1
                                                                                                       Converter


                                                                                                           41
 Design Examples                                                                                                                                                 J. Silva-Martinez


                                       Biquadratic section and OPAMP
                                                RF


                       Rq                                                           Quiescent current ~ 1.0 mA
                                                                -1


                           C1
                                                       C2
                                                                                     GBW > 800MHz
       R
                                                                                    First stage Second stage
Vin    1
                 _                     R2
                                                       _
                 +              V_bp
                                                       +
                                                                       V_lp
                                                                                    No extra CMFB                            (current re-use)
                     A1
                                                           A2
                                                                                    needed
      in   gm1                   gm2             out

            RL1            CL1         RL2       CL2


                     gmf                      Two stage amplifier with                                                                                      MP4            MP4
                                                                                                    MP2B                                        MP2B
                                             feedforward compensation 1
                                                                      MP                     MP1                 MP2A                  MP2A                        VCMFB
                                                                                                                         VCMFB
                                                                                                                                              VOUT+ VOUT+
      Large resistors are used                                                 R1       R1               VOUT-
                                                                                                                                                       R2   C2

                                                                              MN1      MN1                             MN2   MN2                                   MN4     MN4

                                                                     VIN+       1st stage         VIN-                  2nd stage                      R2   C2       CMFB        VREF
                                                                                                                                                                      stage
                                                                                                                                                    VOUT-
      Feed-forward stage                                                              IB1
                                                                                                   VIN+
                                                                                                                                 IB2
                                                                                                                                                  VIN-
                                                                                                                                                                           IB4

                                                                                                                 MN3                   MN3
                                                                                                                       feedforward
                                                                                                                           stage

                                                                                             42                               IB3
Design Examples                                                                                                             J. Silva-Martinez


    Very linear OPAMP for >100MHz applications
                  Feed-Forward Path
                                                                              95
                                                Vcmfb                                                                       Convetional
                                                                              90                                            Linearized
                      MF    MF                 -Vout +                        85
      +                                                                       80
                            2IF
      Vin                                     M3     M3                       75




                                                                   IM3 (dB)
       -                                                                                                 17dB improvement
                                                     2I3                      70
                    AV1       AV2                                             65
                                                                              60

      VCM                                                                     55
     R1 R1                                    ML     ML                       50
                                                                              45
                                                        2IL                     -30   -28   -26   -24   -22    -20    -18     -16     -12   -10
                                      Linearity
                                      Compensation                                                  Output Signal (dBV)
            2I1




                                                                                       C.-Y. Lu, “A 6th-order 200MHz IF
                                                                                       Bandpass Sigma-Delta Modulator
                                                                                       With over 68dB SNDR in 10MHz
                                                                                       Bandwidth,” To be published JSSC
                                                              43
Design Examples                                                                                  J. Silva-Martinez


      Wide-band Adder with delay compensation

                                                        The load resistor is split into 2 pieces and
                  RDAC2
  VDAC2-                                                one section replaced by an RC T-network
                   R5
   VLP3-                   CT
                   R4
   VLP2-
                   R3     RB             RC             Rfeedback = Ra||(Rb+Rc) at low frequencies
  VBP2-
                   R2                                   Rfeedback = Ra at low frequencies
   VLP1-                            RA        CL
                   R1
   VBP1-
                                Gm             VOUT
  VBP1+
                                                          θ (ω ) = tan −1 ( ω ) − tan −1 ( ω )
                                                                            ω              ω
                                                                              z                 p
                   R1
   VLP1+                            RA        CL
                   R2
   VBP2+                                                                               (ω z − ω p )(ω 2 − ω zω p )
                   R3     RB             RC               τ delay =   − dθ (ω )
                                                                         dω
                                                                                  =−
   VLP2+                                                                                         2
                                                                                        (ω 2 + ω z )(ω 2 + ω 2 )
                                                                                                             p
                   R4          CT
   VLP3+
                   R5
  VDAC2+
                  RDAC2

                                                   44
Design Examples                                                    J. Silva-Martinez


                  Pulse Amplitude Modulation

                   •  Traditional Multi-level Digital Signal




                                          I               Q inj = (α I )T s
                                        4I/7              where:
                                                                    1 2
                                                          α = [0,    , ,.... 1]
                                         I/7                        7 7
                                                    Ts



        Unit element current mismatch generates DAC
        non-linearity.
                                   45
Design Examples                                          J. Silva-Martinez


            Time-Domain Pulse Width Modulation




                                   I            Qinj = I (α Ts )
                                                where:
                                                          1 2
                                                α = [0,    , ,.... 1 ]
                                                          7 7

                                       2Ts/7
                                        T /7
                                        T
                                       4Tss/7



     Only inherently linear 1-level DAC achieve multi-
     bit feedback
                              46
Design Examples                                              J. Silva-Martinez


                  Systematic (Nonlinearity) errors

                     •  Error Charge from Device Mismatch

   Conventional Multi-Level             1-level PWM DAC
   DAC                                         4Ts/7
        I                                 I
          4I/7

            I/7
                         Ts
                      ΔI                                ΔT
          Qerr = N ⋅ ( ) ITs                Qerr = 2 ⋅ ( ) ITs
                       I                                T
      Current errors                    Timing errors at the
      accumulate                        pulse edges
                                   47
Design Examples                                                             J. Silva-Martinez



                   INL, DNL and Linearity
                  •  Robustness to device mismatch
                     –  only affect the edges of the pulse


                                                                     ΔI
                                                             δ%I =      = 0 .5 %
                                                                      I
                                                                     ΔT
                                                            δ %T =      = 0.16%
                                                                     T

                                                   HD3PWM          ⎛ 2 ⎞⎛ δ %T = 0.16% ⎞
                                                                 ≅ ⎜   ⎟⎜
                                                                   ⎜ 7 ⎟⎜ δ = 0.5% ⎟
                                                                                          ⎟
                                                  HD3conventional ⎝    ⎠⎝ % I          ⎠




                             PWM Linearity could be >10dB better!
                                        48
Design Examples                                                                J. Silva-Martinez


      Time-Domain Pulse Width Modulation
•  Pulse Arrangement                                                       ⎛ Ts2 ⋅ OSR       ⎞
   –  To ease the design of interface circuitry     SJNR peak   = 10 log10 ⎜                 ⎟
                                                                           ⎜ 2 ⋅ σ 2 ⋅ σ 2   ⎟
      between quantizer and level-to-PWM                                   ⎝       y     β   ⎠
      converter
                                                                       +I
                  000                     100
                                     -I
                                                                       +I
                  001                     101
                                     -I
                                                                       +I
                  010                     110
                                    -I
                                                                       +I
                  011                     111
                                    -I               Ts/7
                                                    2Ts/7
                                                    3Ts/7
                                                    4Ts/7
                                                    5Ts/7
                                                    6Ts/7
                             Ts/7
                            2Ts/7




                                                0
                            3Ts/7
                            4Ts/7
                            5Ts/7
                            6Ts/7




                        0


                                                      Ts
                              Ts




                                          49
Design Examples                                                                   J. Silva-Martinez


                                   Jitter Comparison
             •  Sensitivity to Jitter Noise: 400 MHz clock frequency
                –  More transitions in one sampling period
 SNDR (dB)




                                                                                  ⎛ Ts2 ⋅ OSR       ⎞
                                                           SJNR peak   = 10 log10 ⎜                 ⎟
                                                                                  ⎜ 2 ⋅ σ 2 ⋅ σ 2   ⎟
                                                                                  ⎝       y     β   ⎠
                    Conventional 3-bit modulator

                     Proposed 7-phase modulator




                                     Jitter σβ (ps)

    Worst case for the PWM case: Jitter at both edges is
    uncorrelated
                                                      50
  Design Examples                                                                                                                                                                                J. Silva-Martinez


                                                                                                            LC-VCO + CILFD
Vin +              2nd-Order        2nd-Order            1st-Order
                                                                          b5
                            LP




                                               LP

      -              Filter           Filter                    LP
                                                                                           3-Bit Two-Step
                      BP                 BP                                                  Quantizer
                                                    b4
                                                                                                            Digital
                                                           b3
                                                                               Σ
                                                                                                            Output
                                                                                                                            phase order:                        Φ4P                                    Φ4N
                                                                b2

                                                                     b1             3-Bit NRZ                  4
                                                                                                                        Φ1,Φ5,Φ2,Φ6,Φ3,Φ7,Φ4
                                                                                      DAC
                                 Complementary Injection-
                                 Locked Frequency Divider
   1-Bit PWM DAC




                      VCO
                                         CILFD

                                              Programmable Delay
                                                                                                                                          Φ5P                                             Φ5N
                                                                                   Level-to-PWM
                                     1                                    1
                                                                                     Converter




                                                                                                                               Φ1P                                           Φ1N

                                                                                                                                                     7-stage chain                              7-stage chain
                                                                                                                                                          Mpt



                                                                                                                      VCOP                                Mp          VCON
                                                                                                                               VBP                                             VBP
                                                                                                                             (off-chip)                                      (off-chip)

                                                                                                                                                          Mn



                                                                                                                                                          Mnt

                                                                                                                               Vbn                                            Vbn
                                                                                                                             (off-chip)                                  (off-chip)



  •                Phase noise of VCO is -119dBc/Hz @ 1MHz                                                                                                      Jitter between phases
  •                CILFD phase noise is -136dBc/Hz @ 1MHz
                                                                                                                                                51              is highly correlated
           Design Examples                                                                                                                                                                                       J. Silva-Martinez


                                                                       Proposed 3-bit Two-Step Quantizer
Vin +                2nd-Order        2nd-Order            1st-Order
                                                                            b5
                              LP




                                                 LP




      -                Filter           Filter                    LP
                                                                                             3-Bit Two-Step




                                                                                                                        •  The output is composed by 1 MSB +
                        BP                 BP                                                  Quantizer
                                                      b4
                                                                                                              Digital
                                                                                                              Output
                                                             b3
                                                                                 Σ
                                                                  b2




                                                                                                                           3LSB
                                                                       b1             3-Bit NRZ                  4
                                                                                        DAC
                                   Complementary Injection-
                                   Locked Frequency Divider
   1-Bit PWM DAC




                        VCO
                                           CILFD




                                                                                                                        •  The MSB is determined first
                                                Programmable Delay
                                                                                     Level-to-PWM
                                       1                                    1
                                                                                       Converter




                                                                                 Iin                  Vcmp                       MSB
                                                                                                                                       Differential Voltage Range

         Vin                       S/H                      Gm
                                                                                                                                              +200mV
                                                                                                                                       +Vref3 = +150mV
                                                                                                                                                                                       = decision (latching) instant for a bit


                                   CLK
                                                        Iref1                                                  Rcmp         τ1         +Vref2 = +100mV
                                                                                                                                       +Vref1 = +50mV
                                                                                                                                                                             MSB > VrefDC
                                                                                                                                  B2
      Vref1                             Gm                                                                                               VrefMSB = 0V
                   (τ4)                                                                             Iref
                                                                                                                                       -Vref1 = -50mV
                                                        Iref2                                                        CTRL   τ2         -Vref2 = -100mV
                                                                                                                                                                             MSB < VrefDC

                                                                                                                                  B1
    Vref2                              Gm                                        4:1 MUX                                               -Vref3 = -150mV
                                                                                                                                                                        τ1                   τ2       τ3       τ4            sampling
        (τ3)                                                                                                         MSB                       -200mV
                                                                                                                                                             sampling   MSB                  B2       B1       B0
                                                           Iref3                                     IrefDC                 τ3                                                                                                           Time

       Vref3                               Gm                                                                                     B0
                                                                                                                                                         0         Ts/7        2Ts/7      3Ts/7    4Ts/7    5Ts/7    6Ts/7       7Ts/7

             (τ2)                                                                       Gm                                                                                             successive              S/H tracking
                                                                                                                                                                                  comparisons to Vref (Iref) (for next cycle)
                                                                            VrefDC (τ1)                                     τ4
                                                                                                                                          52
                   Design Examples                                                                                                                                             J. Silva-Martinez


                                                                                Proposed Level-to-PWM Converter

                                                                                                                        •  SR latches generate the pulses
Vin +                2nd-Order        2nd-Order            1st-Order
                                                                            b5
                              LP




                                                 LP




      -                Filter           Filter                    LP
                                                                                             3-Bit Two-Step
                        BP                 BP                                                  Quantizer
                                                      b4
                                                                                                              Digital
                                                                                                              Output
                                                             b3
                                                                                 Σ
                                                                  b2

                                                                       b1             3-Bit NRZ




                                                                                                                        •  AND gates + OR gates decide the required pulses
                                                                                                                 4
                                                                                        DAC
                                   Complementary Injection-
                                   Locked Frequency Divider
   1-Bit PWM DAC




                        VCO
                                           CILFD

                                                Programmable Delay




                                                                                                                        •  Programmable Delay is used to minimize excess
                                                                                     Level-to-PWM
                                       1                                    1
                                                                                       Converter




                                                                                                                           loop delay
                                                                                                                          5-Input OR Gate

                                                                                                                                                                  Programmable
                                                                                                                                                                      Delay
                                           Φ1                 S Q                                 Φ6            S Q        Φ4   S Q   Φ3   S Q        Φ5   S Q
                                           Φ3                 R                                   Φ1            R          Φ5   R     Φ4   R          Φ6   R
                                                                                                                                                                             to 1-Bit
                                                                                                                                                                      S Q
                                                                                                                                                                 ΔT
                                     MSB                          D Q                                            D Q       B2   D Q   B1   D Q        B0   D Q
                                                                                                                                                                      R Q   PWM DAC
                                     MSB                          D Q                                            D Q       B2   D Q   B1   D Q        B0   D Q

                                                                   Φ6                                                Φ4          Φ2        Φ1               Φ3




                                                                                                                          5-Input OR Gate
                                                                                                                                                 53
Design Examples                                                           J. Silva-Martinez


             Chip Microphotograph & Clock Jitter

    	
  




                        Loop Filter +
                      Summing Amplifier

             DAC1 &DAC2

                              3-Bit Two-Step
              Level-to-PWM
                                Quantizer
                Converter



             VCO & Complementary
                Injection-Locked   Buffers
               Frequency Divider




                                               	
  




           Core area = 2.6mm2                              RMS jitter= 0.27ps
                                                           => SJNR > 75dB
                                                      54
     Design Examples                                                                                                                         J. Silva-Martinez


                             Measurement Result – SNDR & SFDR

                             •  Output Spectrum of the Modulator
   -2.2dBFS @ 5.08MHz
                    0                                                                                                   DR=69dB
                                                                                          70
                   -20                                                                                SNR
                                                                                          60
                                                                                                      SNDR




                                                           78dB
                   -40
Magnitude (dBFS)




                                                                                          50




                                                                        SNR & SNDR (dB)
                   -60                                                                    40

                                                                                          30                              69
                   -80
                                                                                                                          68
                                                                                          20
                                                                                                                          67
                   -100
                                                                                                                          66
                                                                                          10
                                                                                                                          65
                   -120                                                                                                   64
                                                                                          0                                    -5.5   -5   -4.5   -4    -3.5   -3    -2.5

                   -140                                                                        -70   -60     -50        -40       -30             -20          -10          0
                       104    105      106           107          108                                              Input Signal (dBFS)
                                    Frequency (Hz)


                              Ø  Peak SNR= 68.5dB @25MHz BW
                              Ø  Peak SNDR= 67.7dB @25MHz BW
                              Ø  SFDR=78dB                       55
       55
Design Examples                                                                                      J. Silva-Martinez


                                                 Signal to Distortion Ratio

  •  Two tones with 2MHz apart and -2dBFS overall power

                                                 0
                  -72




                                                                     IM3 = -76.3dB
                            Magnitude (dBFS)


                                                -20
                                                -40
                  -73                           -60
                                                -80
       IM3 (dB)




                                               -100
                  -74
                                               -120
                                                                     107
                  -75                                      Frequency (Hz)


                  -76

                        0                             5         10                        15   20   25
                                                      Two-Tone Average Frequency (MHz)
                                                                                     56
Design Examples                                                            J. Silva-Martinez


                       Overall Performance

                      Technology	
                 Jazz 0.18µm CMOS	
  
                     Power Supply	
                        1.8V	
  
                    Clock Frequency	
                    400MHz	
  
                       Bandwidth	
                       25MHz	
  
             Peak SNR / SNDR* @ 25MHz
                                                     68.5dB / 67.7dB	
  
                      Bandwidth	
  
                         SFDR	
                           78dB	
  
                 IM3 (-5dBFS per tone)	
                 < -72dB	
  
                    Dynamic Range	
                       69dB	
  
                  Power Consumption	
                    48mW	
  
           Area without pads &ESD protection	
           2.6mm2	
  


                                          57
Design Examples                                                                  J. Silva-Martinez


                          Aliasing Test: -10dBFS tone at 390MHz

  •  Two tones with 2MHz apart at 10 MHz offset from Clock
     frequency and -10dBFS overall power

                          -40
                          -50
       Magnitude (dBFS)




                          -60
                          -70
                                      Over 56dB blocker rejection

                          -80
                          -90

                          -100
                          -110

                          -120

                                104         105        106           107   108
                                                    Frequency (Hz)
                                                        58
Design Examples                                                                        J. Silva-Martinez


                  Comparison with Reported Works

   A 25MHz Bandwidth 5th-Order Continuous-Time Lowpass Sigma-Delta Modulator With
   67.7dB SNDR Using Time-Domain Quantization and Feedback, C.Y. Lu, et.al., Sept 2010,
   IEEE J. Solid-State Circuits.


                                                       Filter Peak
   Reference       Technology        Fs        BW                         Power      FoM (fJ/bit)
                                                       Order SNDR
    JSSC 2008     130nm CMOS      950MHz     10MHz        2   72dB        40mW*           500
   ISSCC-2008     180nm CMOS      640MHz     10MHz       5      82dB     100mW†           487
    ISSCC-2009     65nm CMOS      250MHz     20MHz       3      60dB     10.5mW†          319
   ISSCC-2007      90nm CMOS      340MHz     20MHz       4      69dB      56mW#           608
   ISSCC-2008      90nm CMOS      420MHz     20MHz       4      70dB      28mW†           271Δ
    JSSC 2006     130nm CMOS      640MHz     20MHz       3      74dB      20mW†           122
   This work      180nm CMOS 400MHz 25MHz                5     67.7dB     44mW†          444†


  * Includes clock generation circuitry.
  † For modulator circuitry only.
  # Includes digital calibration of RC spread & noise cancellation filter.
  Δ Discrete-time modulator (would require anti-aliasing filter for comparable blocker rejection).
                                                 59
Design Examples                                                      J. Silva-Martinez


                             Conclusions

     •  A 5th-order LP CT ΣΔ modulator with time-domain 3-bit
        quantizer and DAC was designed

     •  The jitter effect and device mismatch issue are analyzed and
        considered in the design
     •  By employing the proposed time-domain PWM digital signal,
        the timing mismatch issue is minimized

     •  Better jitter tolerance if jitter is correlated in all clock phases
     •  Measured 67.7dB peak SNDR @ 25MHz BW and < -72dB
        IM3.

     •  Over 55dB blocker rejection
                                       60

				
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