ESPRIT: A Compact Reluctance Based Interconnect Model Considering Lossy Substrate Eddy Current Rong Jiang Charlie Chung-Ping Chen Electrical and Computer Engineering Graduate Institute of Electronics Engineering College of Engineering & Department of Electrical Engineering University of Wisconsin, Madison, WI 53706 National Taiwan University, Taipei 106, Taiwan Abstract— With the advancement of radio frequency mixed- capture the inductance loss due to the formation of eddy signal ICs, lossy silicon substrate has signiﬁcant impact on the currents in the conductive substrate. Although several works already complicated interconnect modeling issue. To account for have been proposed to resolve this issue by constructing three the substrate loss, the traditional electromagnetic methods are dimensional linear substrate models –, most of these often computationally prohibitive for large scale VLSI geome- approaches employ a numerical ﬁnite difference based method tries. In this paper, we extend the traditional PEEC model to by spatially discretizing a large volume of silicon bulk under consider the substrate eddy current loss based on the complex the conductor system and hence will lead to equivalent circuits image theory and the skin and proximity effects by discretization of conductors. To deal with even larger scale of interconnects, prohibitive in size. we present a reluctance based model, ESPRIT, to enhance the In this paper, we propose an accurate and efﬁcient method extended PEEC model to use reluctance by equipping it with to extend the PEEC model to consider the substrate eddy an advanced windowing algorithm to further reduce the model current loss based on the complex image theory , which size and runtime. Detail comparisons with state-of-the-art tools has been recently used in RFIC regime to accurately capture such as FastHenry and Momentum demonstrate that ESPRIT is line impedances of microstrips   and spiral inductors within 1% accuracy while providing over 100X speedup.  on lossy silicon substrates. The complex image theory generates the complex images of interconnects based on the I. I NTRODUCTION conﬁguration of substrate structure instead of discretizing the Due to the proliferation of mixed analog-digital system and substrate and hence can result in very compact models for radio frequency integrated circuit (RFIC), the development interconnects. of efﬁcient interconnect models for such a system is made To deal with millions of interconnects and their images, we difﬁcult because of the lossy nature of the silicon substrate. enhance the extended PEEC model to use reluctance element In particular, the creation of eddy currents in the conductive with an extended window searching reluctance extraction silicon substrate can lead to signiﬁcant interconnect inductance algorithm. Finally, since this new model, ESPRIT, includes loss. An interconnect system analysis without considering the mutual resistances and reluctances, in order to be applicable lossy substrate effect will result in an over-designed network to general circuit simulators, SPICE compatible models for and waste chip resources. mutual resistance and reluctance are also provided. Detail With the increasing clock frequency and integration density, comparisons with state-of-the-art tools such as FastHenry and intentional and unintentional inductance effects gradually rise. Momentum demonstrate that ESPRIT is within 1% accuracy One major problem of inductance analysis is the unknown while providing over 100X speedup. current return path. Fortunately, the PEEC (Partial Equivalent Element Circuit) method has been widely adopted to deal with this issue . However, since PEEC model assumes current II. C OMPLEX I MAGE T HEORY return paths at inﬁnity, extremely dense partial inductance matrices are usually generated which dramatically increases For frequencies up to a few Giga Hertz, the wavelength of both model size and simulation runtime. the magnetic ﬁelds far exceeds a typical die’s dimension. Thus For this reason, various inductance sparsiﬁcation techniques we can make magneto-quasi-static approximations. have been introduced to alleviate this problem –. In par- Under this assumption, for a z-direction current, only the ticular, the reluctance-based method   has been proposed z-component of the magnetic potential A is nonzero, thus by Hao Ji et al. Since reluctance has higher degree of locality the substrate diffusion equation can be reduced to a two similar to capacitance, only a small number of neighbors need dimensional EM problem: to be considered, and hence reluctance matrix for circuit sim- ulation is very sparse compared to partial inductance matrix. ∂ ▽2 Az (x, y) − µσ Az (x, y) = 0 (1) Moreover, the traditional PEEC approach does not take ∂t the substrate loss effect into consideration and hence cannot By constructing the Green’s function, the solution can be expressed as: Since for every metal layer of the on-chip conductor system, only the ﬁrst term dMi in Eq. 8 is different, a common complex Az (x, y) = G(x, y|x′ , y ′ )Jz (x′ , y ′ )dx′ dy ′ (2) image plane is shared by all metal layers. Based on the method of image, the common complex image plane can be substituted where Jz (x, y) is the current distribution of a line current by image conductors which are at a distance 2hi f below the ef located above the substrate. physical conductors in metal layer i. Without loss of generality, we assume that a unit line current Besides the lossy substrate effect, as the frequency goes is located at (x′ = 0, y ′ ), with the consideration of the ﬁnite high, the current in a physical conductor is no longer evenly thickness of the substrate and the presence of a ground plane, distributed, which leads to signiﬁcant changes in resistance the Green’s function G(x, y|x′ = 0, y ′ ) can be expressed as and inductance values. In order to obtain wide band accuracy, : those effects, namely skin effect and proximity effect, also G(x, y|x′ = 0, y ′ ) = need to be modeled. For capturing both skin and proximity effects, conductors have to be discretized into ﬁlaments so as µ0 ∞ e−k|y−y | ′ ′ p − k kd e−k(y+y +d) to account for the non-uniform distribution of current within − e cos(kx)dk (3) 2π 0 k p+k k conductors . where The extended PEEC model, which is shown in Fig. 1, is obtained by the application of complex image theory and the γ = jωµ0 σsi (4) discretization of both the physical and image conductors into q(k) = k2 + γ 2 (5) ﬁlaments. Physical Conductors p(k) = q(k)coth[q(k)hsi ] (6) . . . . . . . . . . . . µ0 is the permeability of free space, σsi is the bulk conductiv- . . . . ity, hsi is the thickness of the substrate, while coth[x] is the hyperbolic cotangent function. Effective Complex . . . . Distance The kernel of the integral in Eq. 3 has two terms. The ﬁrst . . . . . . . . . . . . term can be attributed to the physical line current located at (x′ = 0, y ′ ), while the second term is due to an image line Image Conductors current located at y = −(y ′ + d). This approximation holds when the coefﬁcient of the second term, p−k ekd , is approxi- p+k Fig. 1. Extended PEEC model mated by constant one. By applying the Taylor expansion of The complex inductance matrix for the conductor system p−k kd with n ﬁlaments is given by: p+k e at k = 0 and neglecting high order terms, we obtain that this requirement can be satisﬁed when L(hef f ) = Lf reespace − Limage (9) (1 + j)hsi d = (1 − j) · δsi · tanh (7) Lf reespace is the inductance matrix without considering the δsi lossy substrate, i.e. in free space. Limage is the mutual √ where δsi = 1/ πf µ0 σsi is the skin depth of the bulk silicon inductance matrix between physical and image ﬁlaments. and tanh[x] is the hyperbolic tangent function. The calculation of Limage depends on the effective complex Thus the eddy current effect in the lossy substrate and distance hef f , thus L(hef f ) will be frequency and process the ground plane can be approximated by an image current parameters dependent. located at the complex distance d below the substrate surface. Since L(hef f ) = L(ω)+R(ω)/jω, the complex inductance Alternatively, an image ground plane can be placed at d/2 matrix can be interpreted as follows: below the surface to represent the currents both in the substrate L(ω) = Real[L(hef f )] (10) and the ground plane. and III. E XTENDED PEEC M ODEL R(ω) = −ωImag[L(hef f )] + RDC (11) For interconnects within metal layer i, which has a distance where L(ω) and R(ω) are the frequency dependent partial dMi above the substrate, according to the complex image inductance and resistance matrix respectively. RDC is a diag- theory, the lossy silicon substrate effect can be approximated onal matrix including DC resistances of the physical ﬁlaments. by placing a complex image plane below metal layer i at an It can be seen that R(ω) contains off diagonal terms which effective complex distance, hi f . If we denote the thickness ef represent mutual resistances. We will address the mutual of oxide and silicon bulk as hox and hsi respectively, by using resistance modeling problem in the following section. Eq. 7, the effective complex distance of metal layer i is given by: IV. SPICE C OMPATIBLE R ELUCTANCE -BASED M ODEL 1−j (1 + j)hsi In the previous section, we present how to obtain par- hi f = dMi + hox + ef · δsi · tanh (8) tial inductance matrix L(ω) and resistance matrix R(ω) by 2 δsi using complex image theory. However, L(ω) and R(ω) are • Effective Search Window (ESW): Extend the physical extremely dense due to the globe effect of partial inductance aggressor along its length by a window extension factor coupling. Therefore, a more practical modeling approach is (WEF) and obtain the effective window width (EWW). necessary to obtain circuit model of manageable size. Then, the ESW is deﬁned by sweeping in the direction perpendicular to the length of the aggressor to inﬁnity A. Physical Meaning of Partial Reluctance with the EWW. Reluctance based methods have been extensively used re- • Conductor Shielding Level (CSL): The CSL of the aggres- cently because reluctance has better locality than inductance. sor is deﬁned as 0, which is the highest level. Conductors The partial reluctance matrix K is deﬁned as the inverse of outside ESW are of CSL ∞, the lowest level. A conductor the partial inductance matrix L. i is directly shielded by conductor j if conductor j can be K = L−1 (12) reached by some points along the length of conductor i within ESW without encountering any other conductors. Since LI = Φ and by applying the Stoke’s theorem: A conductor is of CSL k+1, if the minimum CSL of conductors directly shielding it is k. Φ= Bds = ▽ × Ads = Adl (13) • Conductor Group of CSL k: Conductor group of CSL k contains two parts. The physical part includes the physical the partial inductance matrix for a system including n con- aggressor and its victim conductors of CSL no larger than ductors will be: k. The image part includes images of physical conductors I1 A1 dl1 in the physical part. The union of these two parts gives L11 L12 · · · L21 L22 · · · . = . . . (14) conductor group of CSL k. . . Ln1 Ln2 Lnn In An dln We illustrate our extended window selection algorithm ??? through a small example shown in Figure 2. If the current where Ai is the vector potential in conductor i. Hence the Effective Window Width WEF WEF partial reluctance matrix can be obtained as follows: 1 A dl I K11 K12 · · · 1 1 1 2 3 . . = . K21 K22 · · · . . . (15) Kn1 Kn2 Knn An dln In 4 5 6 7 The globe coupling effect of partial inductance is caused by the artiﬁcial assumption that the current return path is 8 9 at inﬁnite. During partial inductance extraction, we apply a unit current source on the aggressor conductor at inﬁnity and Fig. 2. Extended Window Selection Algorithm force the currents in victim conductors to be zero by applying aggressor is conductor 1, its CSL is 0. Conductor 3 and 4 zero current sources at inﬁnity. Since in this scenario the only are of CSL 1; Conductor 5, 6, 7 and 8 are of CSL 2 while magnetic ﬁeld is generated by the current in the aggressor and conductor 9 is of CSL 3. Conductor 2 is outside the ESW no other magnetic ﬁelds cancel its effect, it can propagate far and hence its CSL is ∞. Conductor group of CSL 1 includes away and give rise to a dense partial inductance matrix. physical conductors 1, 3, 4 and image conductors 1′ , 3′ and However, when calculating the self and mutual reluctances 4′ . for conductor j, we need to set a unit magnetic ﬂux for the Our frequency dependent reluctance-based interconnect j th conductor, and zero ﬂux for all others. In order to satisfy model, ESPRIT, is based on the combination of the extended this conﬁguration, we need to apply an unit vector potential PEEC and the above window selection algorithm. For each on the aggressor and at the same time pose negative vector conductor, we search its conductor group of CSL k and potentials on victims to cancel the magnetic ﬁeld generated by calculate the small L(ω) and R(ω) for this conductor group the aggressor. Therefore, the currents ﬂowing in aggressor and after proper discretization according to conductor skin depth. victims are basically of opposite direction and the magnetic Then the small L(ω) for this conductor group is inverted ﬁeld of the aggressor is mostly cancelled by victim magnetic to obtain the small K(ω) matrix. The ﬁnal circuit model is ﬁelds and cannot propagate faraway. This explains why partial assembled by using those small K(ω) and R(ω) matrices. reluctance has better locality than partial inductance. Since ESPRIT includes mutual resistances and reluctances, in order to avoid signiﬁcant modiﬁcations on general simula- B. Extended Window Selection Algorithm tion tools, we need to consider their SPICE compatible models, In stead of directly calculating partial inductance matrix and which can be obtained from their branch equations respec- inverting it to obtain partial reluctance matrix, most existing tively. The branch equation of self and mutual resistances is reluctance extraction tools are based on window selection given by algorithms, such as . Here we propose an extended window n n selection algorithm to consider both physical conductors and Vi = Rij Ij = Rii Ii + Rij Ij (16) their images. j=1 j=1,j=i where Rii is self resistance and Rij is the mutual resistance The waveforms of the enhanced PEEC at different frequen- between Rii and Rjj . Eq. 16 can be rewritten as cies are shown in Fig. 4.(a). Also the responses in Fig. 4.(b) n demonstrate that ESPRIT has much smaller model size while Rij maintaining less than 3% error compared to the enhanced Vi = Rii Ii + (Rjj Ij ) (17) Rjj PEEC model. j=1,j=i 1.4 1.4 If we view Rii Ii as the voltage drop across the self 1.2 1.2 resistance Rii , Vi is then equal to the sum of the voltage drop 1.0 1.0 on a self resistance Rii and serially connected voltage control Voltage (V) Voltage (V) 0.8 0.8 voltage sources (VCVS). These VCVSs are controlled by 0.6 0.6 voltages on other self resistances which originally have mutual 0.4 Free Space Lossy at 4gHz 0.4 resistances with Rii . Therefore, Eq. 17 can be used to construct 0.2 Lossy at 10gHz Lossy at 20gHz 0.2 Enhanced PEEC ESPRIT SPICE compatible model for mutual resistances, which is 0.0 0.05 0.10 0.15 0.20 0.0 0.05 0.10 0.15 0.20 R n Rij shown in Figure 3.(a), where VV CV S = j=1,j=i Rjj Vjj . Time (ns) (a) Time (ns) (b) ni ni ni ni Fig. 4. The Enhanced PEEC vs. ESPRIT Rii 1 / K ii Rii K ii VI. C ONCLUSION + + R k VVCVS VVCVS A new reluctance-based interconnect model ESPRIT con- | | nj nj nj nj sidering the loss substrate effect is presented in this paper. (a) (b) It’s obtained by combining an enhanced PEEC model with an extended window-based reluctance extraction algorithm. Fig. 3. SPICE Compatible Model for (a) mutual resistance (b) reluctance Extensive simulation results demonstrate that ESPRIT has SPICE compatible model for reluctance can be derived by extremely high accuracy and signiﬁcantly small model size. similar method. It includes a self inductance 1/Kii and serial K n Kij VCVSs VV CV S = − j=1,j=i Kjj Vjj shown in Figure 3.(b). R EFERENCES By applying those equivalent circuit models, ESPRIT can be  A. E. Ruehli, “Inductance calculatioin in a complex integrated circuit fully accepted by general simulators. environment,” IBM Journal of Research and Development, Sep 1972.  B. Krauter and L. T. Pileggi, “Generating sparse partial inductance V. E XPERIMENTAL R ESULTS matrices with guaranteed stability,” ICCAD, Nov 1995.  K. L. Shepard and Z.Tian, “Return-limited inductances: A practical Extensive experimental results are reported to show the ef- approach to on-chip inductance extraction,” Computer Aided Design of ﬁciency and accuracy of our new interconnect model ESPRIT. Integrated Ciurcuits and Systems, Apr 2000.  K. Gala, V. Zolotov, R. Panda, B. Young, J. Wang, and D. Blaauw, To validate the new modeling approaches and to illustrate “On-chip inductance modeling and analysis,” DAC, Jun 2000. the accuracy, we ﬁrst compare the inductance values computed  A. Devgan, H. Ji, and W. Dai, “How to efﬁciently capture on-chip by the enhanced PEEC model with FastHenry  and a more inductance effects:introducing a new circuit element k,” ICCAD, 2000.  H. Ji, A. Devgan, and W. Dai, “Ksim: A stable and efﬁcient rkc simulator rigorous full wave EM analysis tool, HP-Momentum. Under for capturing on-chip inductance effect,” ASPDAC, Jun 2001. TABLE 1  R. Gharpurey and R. G. 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Without considering the inductors on lossy silicon substrate,” Microwave Symposium Digest, substrate, PEEC takes about 25.316s to assemble the model, 2003. while the enhanced PEEC spends about 59.131s to model the  M. Kamon, M. J. Tsuk, and J. K. White, “Fasthenry: A multipole- accelerated 3-d inductance extraction program,” DAC, Jun 1993. lossy substrate effect. However, they both contain 282,125  G. Zhong, C.-K. Koh, V. Balakrishnan, and K. Roy, “An adaptive elements. While applying ESPRIT by searching neighboring window-based susceptance extraction and its efﬁcient implementation,” of shielding level two, it takes only 5.368s to obtain the circuit DAC, Jun 2003. model with 3,632 elements.
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