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					Sequential Logic Implementation

z Sequential Circuits
   yPrimitive sequential elements
   yCombinational logic
z Models for representing sequential circuits
   yFinite-state machines (Moore and Mealy)
   yRepresentation of memory (states)
   yChanges in state (transitions)
z Basic sequential circuits
   yShift registers
   yCounters
z Design procedure
   yState diagrams
   yState transition table
   yNext state functions
                CS 150 - Fall 2000 - Sequential Logic Implementation - 1
Abstraction of State Elements

z Divide circuit into combinational logic and state
z Localize feedback loops and make it easy to break cycles
z Implementation of storage elements leads to various
  forms of sequential logic

 Inputs                                                                        Outputs
                                Combinational
                                   Logic



State Inputs                                                              State Outputs

                Storage Elements


               CS 150 - Fall 2000 - Sequential Logic Implementation - 2
Forms of Sequential Logic

z Asynchronous sequential logic – state changes occur
  whenever state inputs change (elements may be simple
  wires or delay elements)
z Synchronous sequential logic – state changes occur in
  lock step across all storage elements (using a periodic
  waveform - the clock)




                                                                          Clock
               CS 150 - Fall 2000 - Sequential Logic Implementation - 3
Finite State Machine Representations

z States: determined by possible values in sequential
  storage elements
z Transitions: change of state
z Clock: controls when state can change by controlling
  storage elements
                               001                       010                 111
                                               In = 1             In = 0
                                In = 0
                                            100                        110
                                                         In = 1
z Sequential Logic
   ySequences through a series of states
   yBased on sequence of values on input signals
   yClock period defines elements of sequence
                CS 150 - Fall 2000 - Sequential Logic Implementation - 4
Example Finite State Machine Diagram

z Combination lock from first lecture


                                                                                     ERR
                                                                            closed

                               not equal              not equal
                                & new                                 not equal
                                                       & new           & new
                 S1                    S2                     S3                     OPEN
   reset    closed             closed                 closed
                      equal                 equal                  equal    open
           mux=C1             mux=C2                 mux=C3
                      & new                 & new                  & new

           not new             not new                not new




                 CS 150 - Fall 2000 - Sequential Logic Implementation - 5
Can Any Sequential System be
Represented with a State Diagram?

z Shift Register                                                 OUT1             OUT2        OUT3
   yInput value shown
    on transition arcs                IN            D Q                D Q              D Q
   yOutput values shown              CLK
    within state node

                                                1
                      100                                             110
               1               0                                1             1
                                                1

     0   000          1            010                   101             0        111     1

                                                0
               0               0                                1             0
                      001                                             011
                                                0



                   CS 150 - Fall 2000 - Sequential Logic Implementation - 6
Counters are Simple Finite State Machines

z Counters
   yProceed thru well-defined state sequence in response to enable
z Many types of counters: binary, BCD, Gray-code
   y3-bit up-counter: 000, 001, 010, 011, 100, 101, 110, 111, 000, ...
   y3-bit down-counter: 111, 110, 101, 100, 011, 010, 001, 000, 111, ...


                 001                       010                        011



         000                       3-bit up-counter                         100



                 111                       110                        101

                 CS 150 - Fall 2000 - Sequential Logic Implementation - 7
How Do We Turn a State Diagram into Logic?

z Counter
  yThree flip-flops to hold state
  yLogic to compute next state
  yClock signal controls when flip-flop memory can change
     xWait long enough for combinational logic to compute new value
     xDon't wait too long as that is low performance
                                                    OUT1                  OUT2         OUT3

                                          D Q                D Q                 D Q

                           CLK




                                    "1"

               CS 150 - Fall 2000 - Sequential Logic Implementation - 8
FSM Design Procedure

z Start with counters
   ySimple because output is just state
   ySimple because no choice of next state based on input
z State diagram to state transition table
   yTabular form of state diagram
   yLike a truth-table
z State encoding
   yDecide on representation of states
   yFor counters it is simple: just its value
z Implementation
   yFlip-flop for each state bit
   yCombinational logic based on encoding
                 CS 150 - Fall 2000 - Sequential Logic Implementation - 9
FSM Design Procedure: State Diagram
to Encoded State Transition Table

z Tabular form of state diagram
z Like a truth-table (specify output for all input
  combinations)
z Encoding of states: easy for counters – just use value
                                                             current state      next state
      001         010           011                          0    000            001     1
                                                             1    001            010     2
                                                             2    010            011     3
000         3-bit up-counter              100
                                                             3    011            100     4
                                                             4    100            101     5
      111         110           101                          5    101            110     6
                                                             6    110            111     7
                                                             7    111            000     0



                    CS 150 - Fall 2000 - Sequential Logic Implementation - 10
Implementation

z D flip-flop for each state bit
z Combinational logic based on encoding                                                       notation to show
                                                                                              function represent
          C3       C2       C1       N3   N2     N1                                           input to D-FF
          0        0        0        0    0      1
          0        0        1        0    1      0                   N1 := C1'
          0        1        0        0    1      1                   N2 := C1C2' + C1'C2
          0        1        1        1    0      0                      := C1 xor C2
                                                                     N3 := C1C2C3' + C1'C3 + C2'C3
          1        0        0        1    0      1                      := C1C2C3' + (C1' + C2')C3
          1        0        1        1    1      0                      := (C1C2) xor C3
          1        1        0        1    1      1
          1        1        1        0    0      0

N3                          C3                 N2                        C3            N1                       C3
      0        0        1        1                    0     1        1    0                   1    1        1    1

 C1   0        1        0        1             C1     1     0        0    1              C1   0    0        0    0

                   C2                                           C2                                     C2
                                 CS 150 - Fall 2000 - Sequential Logic Implementation - 11
Implementation (cont'd)

z Programmable Logic Building Block for Sequential Logic
   yMacro-cell: FF + logic
      xD-FF
      xTwo-level logic capability like PAL (e.g., 8 product terms)




                                                                            DQ
                                                                             Q




                CS 150 - Fall 2000 - Sequential Logic Implementation - 12
 Another Example

 z Shift Register
      yInput determines next state

In   C1   C2   C3   N1    N2    N3                           100                1              110
0    0    0    0    0     0     0                        1          0                                1
0    0    0    1    0     0     0                                               1          1
0    0    1    0    0     0     1            0     000       1          010          101         0       111    1
0    0    1    1    0     0     1
0    1    0    0    0     1     0                                               0
                                                         0          0                      1         0
0    1    0    1    0     1     0                            001                               011
0    1    1    0    0     1     1                                               0
0    1    1    1    0     1     1
1    0    0    0    1     0     0         N1 := In
1    0    0    1    1     0     0         N2 := C1
1    0    1    0    1     0     1         N3 := C2                       OUT1         OUT2               OUT3
1    0    1    1    1     0     1
1    1    0    0    1     1     0
1    1    0    1    1     1     0                IN          D Q              D Q              D Q
1    1    1    0    1     1     1
1    1    1    1    1     1     1                CLK

                         CS 150 - Fall 2000 - Sequential Logic Implementation - 13
More Complex Counter Example
z Complex Counter
   yRepeats five states in sequence
   yNot a binary number representation
z Step 1: Derive the state transition diagram
   yCount sequence: 000, 010, 011, 101, 110
z Step 2: Derive the state transition table from the
  state transition diagram
                                                                Present State Next State
           000          110                                     C    B    A   C+ B+ A+
                                                                0    0    0   0    1    0
                                                                0    0    1   –    –    –
                                                                0    1    0   0    1    1
                                                                0    1    1   1    0    1
     010                       101                              1    0    0   –    –    –
                                                                1    0    1   1    1    0
                                                                1    1    0   0    0    0
                 011                                            1    1    1   –    –    –
      note the don't care conditions that arise from the unused state codes
                       CS 150 - Fall 2000 - Sequential Logic Implementation - 14
More Complex Counter Example (cont’d)

z Step 3: K-maps for Next State Functions
 C+                   C                 B+                        C              A+                       C
      0   0       0       X                     1     1       0       X                   0   1       0       X

 A    X   1       X       1              A      X     0       X       1               A   X   1       X       0

              B                                           B                                       B



                                               C+ := A

                                               B+ := B' + A'C'

                                               A+ := BC'




                          CS 150 - Fall 2000 - Sequential Logic Implementation - 15
Self-Starting Counters (cont’d)

z Re-deriving state transition table from don't care
  assignment
C+                   C                 B+                        C                   A+                      C
     0   0       0       0                     1     1       0       1                    0     1       0        0

 A   1   1       1       1              A      1     0       0       1               A    0     1       0        0

             B                                           B                                          B


     Present State Next State                                    111                                        001
     C    B    A   C+ B+ A+
     0    0    0   0    1    0
     0    0    1   1    1    0                                                 000            110
     0    1    0   0    1    1                           100
     0    1    1   1    0    1
     1    0    0   0    1    0
     1    0    1   1    1    0
     1    1    0   0    0    0                                           010                        101
     1    1    1   1    0    0
                                                                                      011
                         CS 150 - Fall 2000 - Sequential Logic Implementation - 16
Self-Starting Counters
z Start-up States
      yAt power-up, counter may be in an unused or invalid state
      yDesigner must guarantee it (eventually) enters a valid state
z Self-starting Solution
      yDesign counter so that invalid states eventually transition to
       a valid state
      yMay limit exploitation of don't cares

            111                                                 111          implementation           001
001                                                                         on previous slide

                    000          110                                         000         110
      100                                                100


              010                       101                            010                      101


                           011                                                     011
                     CS 150 - Fall 2000 - Sequential Logic Implementation - 17
State Machine Model

z Values stored in registers represent the state of the
  circuit
z Combinational logic computes:
   yNext state
      xFunction of current state and inputs
   yOutputs
      xFunction of current state and inputs (Mealy machine)
      xFunction of current state only (Moore machine)
                                     output                            Outputs
                                      logic
          Inputs
                                   next state                 Next State
                                     logic


                            Current State
                   CS 150 - Fall 2000 - Sequential Logic Implementation - 18
State Machine Model (cont’d)

                                                                      output               Outputs
                                                                       logic
                                          Inputs
                                                                    next state       Next State
                                                                      logic
z States: S1, S2, ..., Sk
z Inputs: I1, I2, ..., Im         Current State
z Outputs: O1, O2, ..., On
z Transition function: Fs(Si, Ij)
z Output function: Fo(Si) or Fo(Si, Ij)
       Next State

           State
           Clock 0              1            2             3            4        5



                    CS 150 - Fall 2000 - Sequential Logic Implementation - 19
Example: Ant Brain (Ward, MIT)

z Sensors:               L and R antennae, 1 if in touching wall
z Actuators:             F - forward step, TL/TR - turn
                         left/right slightly
z Goal:                  find way out of maze
z Strategy:              keep the wall on the right




               CS 150 - Fall 2000 - Sequential Logic Implementation - 20
Ant Behavior

     A: Following wall, touching                            B: Following wall, not touching
        Go forward, turning                                    Go forward, turning right
        left slightly                                          slightly




                                                                   D: Hit wall again
        C: Break in wall                                              Back to state A
           Go forward, turning
           right slightly

         E: Wall in front                                        F: ...we are here, same as
            Turn left until...                                       state B



                                                                 G: Turn left until...
    LOST: Forward until we
    touch something

                 CS 150 - Fall 2000 - Sequential Logic Implementation - 21
Designing an Ant Brain

z State Diagram

                                        L+R                                   L’ R

       LOST   L+R                E/G                 L               A
        (F)                      (TL)                              (TL, F)


     L’ R’               L’ R’                 R
                                                                          R
                                                         L’ R’

                                B                                    C
                                                                                 R’
                              (TR, F)                              (TR, F)
                                                   R’




              CS 150 - Fall 2000 - Sequential Logic Implementation - 22
Synthesizing the Ant Brain Circuit

z Encode States Using a Set of State Variables
   yArbitrary choice - may affect cost, speed
z Use Transition Truth Table
   yDefine next state function for each state variable
   yDefine output function for each output
z Implement next state and output functions using
  combinational logic
   y2-level logic (ROM/PLA/PAL)
   yMulti-level logic
   yNext state and output functions can be optimized together




                CS 150 - Fall 2000 - Sequential Logic Implementation - 23
Transition Truth Table

z Using symbolic states
  and outputs                                                            L+R                                L’ R
                                    LOST          L+R            E/G                  L             A
                                     (F)                         (TL)                             (TL, F)


                                   L’ R’                    L’ R’              R
                                                                                                       R
                                                                                          L’ R’
 state   L     R     next state     outputs                      B                                  C
 LOST    0     0     LOST           F                          (TR, F)                            (TR, F)      R’
 LOST    –     1     E/G            F                                              R’
 LOST    1     –     E/G            F
 A       0     0     B              TL, F
 A       0     1     A              TL, F
 A       1     –     E/G            TL, F
 B       –     0     C              TR, F
 B       –     1     A              TR, F
 ...     ...   ...   ...            ...
                          CS 150 - Fall 2000 - Sequential Logic Implementation - 24
Synthesis

z 5 states : at least 3 state variables required (X, Y, Z)
   yState assignment (in this case, arbitrarily chosen)                                  LOST   -   000
                                                                                         E/G    -   001
                                                                                         A      -   010
                                                                                         B      -   011
                                                                                         C      -   100
     state   L R       next state        outputs                     it now remains
     X,Y,Z             X', Y', Z'        F TR TL                     to synthesize
     000     0 0       000               1 0 0                       these 6 functions
     000     0 1       001               1 0 0
     ...     ... ...   ...               ...
     010     0 0       011               1 0 1
     010     0 1       010               1 0 1
     010     1 0       001               1 0 1
     010     1 1       001               1 0 1
     011     0 0       100               1 1 0
     011     0 1       010               1 1 0
     ...     ... ...   ...               ...

                       CS 150 - Fall 2000 - Sequential Logic Implementation - 25
Synthesis of Next State and Output
Functions


 state   inputs   next state   outputs
 X,Y,Z   L R      X+,Y+,Z+     F TR TL
 000     0 0      000          1 0 0
 000     - 1      001          1 0 0
 000     1 -      001          1 0 0
 001     0 0      011          0 0 1
 001     - 1      010          0 0 1                    e.g.
 001     1 -      010          0 0 1
                                                               TR = X + Y Z
 010     0 0      011          1 0 1
 010     0 1      010          1 0 1                           X+ = X R’ + Y Z R’ = R’ TR
 010     1 -      001          1 0 1
 011     - 0      100          1 1 0
 011     - 1      010          1 1 0
 100     - 0      100          1 1 0
 100     - 1      010          1 1 0



                        CS 150 - Fall 2000 - Sequential Logic Implementation - 26
Circuit Implementation

z Outputs are a function of the current state only -
  Moore machine

                                    output                                   F
                                                                             TR
                                     logic
                                                                             TL
             L                    next state         Next State
             R                      logic
                                                       X+      Y+     Z+




                           Current State
                                                       X       Y      Z




                 CS 150 - Fall 2000 - Sequential Logic Implementation - 27
Don’t Cares in FSM Synthesis

z What happens to the "unused" states (101, 110, 111)?
z Exploited as don't cares to minimize the logic
    yIf states can't happen, then don't care what the functions do
    yif states do happen, we may be in trouble
                               L’ R’
                                                            L+R                              L’ R
                       000             L+R          001                L            010
                       (F)                          (TL)                           (TL, F)

    101
                                                L’ R’             R
                                                                                        R
                                                                           L’ R’

                                                    011                              100
            110                                   (TR, F)                          (TR, F)      R’
                                                                      R’
                              111
Ant is in deep trouble
if it gets in this state
                           CS 150 - Fall 2000 - Sequential Logic Implementation - 28
State Minimization

z Fewer states may mean fewer state variables
z High-level synthesis may generate many redundant
  states
z Two state are equivalent if they are impossible to
  distinguish from the outputs of the FSM, i. e., for any
  input sequence the outputs are the same

z Two conditions for two states to be equivalent:
   y1) Output must be the same in both states
   y2) Must transition to equivalent states for all input
    combinations


                CS 150 - Fall 2000 - Sequential Logic Implementation - 29
Ant Brain Revisited

z Any equivalent states?

                                           L+R                                  L’ R

        LOST    L+R                 E/G                 L               A
         (F)                        (TL)                              (TL, F)


      L’ R’                 L’ R’                 R
                                                                           R
                                                            L’ R’

                                   B                                    C
                                                                                   R’
                                 (TR, F)                              (TR, F)
                                                      R’




               CS 150 - Fall 2000 - Sequential Logic Implementation - 30
New Improved Brain

z Merge equivalent B and C states
z Behavior is exactly the same as the 5-state brain
z We now need only 2 state variables rather than 3
                                                     L+R                                L’ R

           LOST           L+R                 E/G                L              A
            (F)                               (TL)                            (TL, F)


         L’ R’                        L’ R’                 R
                                                                     L’ R’

                                            B/C
                            R’
                                          (TR, F)



                  CS 150 - Fall 2000 - Sequential Logic Implementation - 31
New Brain Implementation


state   inputs   next state outputs
                                                               X+                          X                   Y+                          X
X,Y     L R      X',Y'    F TR TL
                                                                           0   1       1       1                           0   1       1       1
00      0 0      00       1 0 0
                                                                           0   0       1       1                           1   0       0       0
00      - 1      01       1 0 0                                                                        R                                               R
                                                                           0   0       1       0                           1   0       0       1
00      1 -      01       1 0 0                                L                                               L
                                                                           0   0       1       0                           1   0       1       1
01      0 0      11       0 0 1
                                                                                   Y                                               Y
01      - 1      01       0 0 1
01      1 -      01       0 0 1
10      0 0      11       1 0 1               F                    X                   TR                          X                   TL                          X
10      0 1      10       1 0 1                    1   0       1       1                           0   0       1       0                           0   1       0       1
                                                   1   0       1       1                           0   0       1       0                           0   1       0       1
10      1 -      01       1 0 1                                                R                                               R                                           R
                                                   1   0       1       1                           0   0       1       0                           0   1       0       1
11      - 0      11       1 1 0               L                                        L                                               L
                                                   1   0       1       1                           0   0       1       0                           0   1       0       1
11      - 1      10       1 1 0
                                                           Y                                               Y                                               Y




                        CS 150 - Fall 2000 - Sequential Logic Implementation - 32
Mealy vs. Moore Machines

z Moore: outputs depend on current state only
z Mealy: outputs depend on current state and inputs
z Ant brain is a Moore Machine
   yOutput does not react immediately to input change
z We could have specified a Mealy FSM
   yOutputs have immediate reaction to inputs
   yAs inputs change, so does next state, doesn’t commit until
    clocking event                    L’ R / TL, F
                     L / TL
                                          A

                                                react right away to leaving the wall


                          L’ R’ / TR, F
                CS 150 - Fall 2000 - Sequential Logic Implementation - 33
 Specifying Outputs for a Moore Machine

  z Output is only function of state
        ySpecify in state bubble in state diagram
        yExample: sequence detector for 01 or 10
                                                                              current   next
                                                          reset     input     state     state   output
                   0
                                                          1         –         –         A
                                1                         0         0         A         B       0
                   B/0                      D/1
                                                          0         1         A         C       0
               0                                          0         0         B         B       0
                         0                                0         1         B         D       0
reset
         A/0                              1         0
                                                          0         0         C         E       0
                         1                                0         1         C         C       0
               1                                          0         0         D         E       1
                   C/0                        E/1         0         1         D         C       1
                               0
                                                          0         0         E         B       1
                    1                                     0         1         E         D       1


                         CS 150 - Fall 2000 - Sequential Logic Implementation - 34
Specifying Outputs for a Mealy Machine

z Output is function of state and inputs
   ySpecify output on transition arc between states
   yExample: sequence detector for 01 or 10

                          0/0                                              current   next
                                                        reset     input    state     state   output
                                                        1         –        –         A       0
                            B
                                                        0         0        A         B       0
                0/0
                                                        0         1        A         C       0
  reset/0                                               0         0        B         B       0
            A         0/1       1/1
                                                        0         1        B         C       1
                                                        0         0        C         B       1
                1/0                                     0         1        C         C       0
                            C

                          1/0


                      CS 150 - Fall 2000 - Sequential Logic Implementation - 35
Comparison of Mealy and Moore Machines
 z Mealy Machines tend to have less states
         yDifferent outputs on arcs (n^2) rather than states (n)
 z Moore Machines are safer to use
         yOutputs change at clock edge (always one cycle later)
         yIn Mealy machines, input change can cause output change as
          soon as logic is done – a big problem when two machines are
          interconnected – asynchronous feedback
 z Mealy Machines react faster to inputs
         yReact in same cycle – don't need to wait for clock
         yIn Moore machines, more logic may be necessary to decode
          state into outputs – more gate delays after
                                                                                           logic for
inputs                                                              inputs                                   outputs
            combinational                                                                  outputs
               logic for
              next state                   logic for                               combinational
                                reg                     outputs                       logic for        reg
                                            outputs
                                                                                     next state



              state feedback                                                        state feedback
                               CS 150 - Fall 2000 - Sequential Logic Implementation - 36
Mealy and Moore Examples

z Recognize A,B = 0,1
   yMealy or Moore?


     A
                                       ou t
                              D   Q
     B
                     cl ock
                                  Q




                                                   A
                                                         D    Q           ou t

                                                              Q

                                                   B
                                                         D    Q
                                              cl ock
                                                              Q




              CS 150 - Fall 2000 - Sequential Logic Implementation - 37
Mealy and Moore Examples (cont’d)

z Recognize A,B = 1,0 then 0,1
   yMealy or Moore?                                                               ou t

                                       A
                                                       D    Q

                                                            Q

                                       B
                                                       D    Q

                                                            Q
                                           cl ock



                                                                           ou t

       A
           D   Q               D   Q

               Q                   Q

       B
           D   Q               D   Q

               Q                   Q

  cl ock


                   CS 150 - Fall 2000 - Sequential Logic Implementation - 38
Registered Mealy Machine (Really Moore)

z Synchronous (or registered) Mealy Machine
   yRegistered state AND outputs
   yAvoids ‘glitchy’ outputs
   yEasy to implement in PLDs
z Moore Machine with no output decoding
   yOutputs computed on transition to next state rather than
    after entering
   yView outputs as expanded state vector
                                   output                                  Outputs
                                    logic
           Inputs
                                 next state
                                    logic


                          Current State
               CS 150 - Fall 2000 - Sequential Logic Implementation - 39
Example: Vending Machine

z Release item after 15 cents are deposited
z Single coin slot for dimes, nickels
z No change
                                          Reset



                             N
                                         Vending          Open
               Coin                      Machine                      Release
              Sensor                       FSM                       Mechanism
                             D




                                          Clock



                CS 150 - Fall 2000 - Sequential Logic Implementation - 40
Example: Vending Machine (cont’d)

z Suitable Abstract Representation
                                                                           Reset
   yTabulate typical input sequences:
      x3 nickels
      xnickel, dime                                                       S0
                                                                    N            D
      xdime, nickel
      xtwo dimes
                                                               S1                    S2
   yDraw state diagram:
                                                          N         D            N        D
      xInputs: N, D, reset
      xOutput: open chute                            S3
                                                                  S4             S5         S6
                                                                [open]         [open]     [open]
   yAssumptions:
                                                    N
      xAssume N and D asserted
       for one cycle                                 S7
      xEach state has a self loop                  [open]
       for N = D = 0 (no coin)

              CS 150 - Fall 2000 - Sequential Logic Implementation - 41
Example: Vending Machine (cont’d)

z Minimize number of states - reuse states whenever possible

             Reset                         present         inputs          next    output
                                           state           D    N          state   open
                                             0¢            0    0            0¢    0
                                                           0    1            5¢    0
           0¢                                              1    0          10¢     0
                                                           1    1          –       –
             N                              5¢             0    0            5¢    0
                                                           0    1          10¢     0
           5¢          D                                   1    0          15¢     0
                                                           1    1          –       –
             N                             10¢             0    0          10¢     0
                                                           0    1          15¢     0
     D                                                     1    0          15¢     0
           10¢
                                                           1    1          –       –
                                           15¢             –    –          15¢     1
             N+D
           15¢                                          symbolic state table
          [open]


                   CS 150 - Fall 2000 - Sequential Logic Implementation - 42
Example: Vending Machine (cont’d)

z Uniquely Encode States
             present state      inputs       next   state     output
               Q1 Q0            D    N        D1    D0        open
               0 0              0    0        0     0         0
                                0    1        0     1         0
                                1    0        1     0         0
                                1    1        –     –         –
                0    1          0    0        0     1         0
                                0    1        1     0         0
                                1    0        1     1         0
                                1    1        –     –         –
                1    0          0    0        1     0         0
                                0    1        1     1         0
                                1    0        1     1         0
                                1    1        –     –         –
                1    1          –    –        1     1         1




             CS 150 - Fall 2000 - Sequential Logic Implementation - 43
Example: Vending Machine (cont’d)

z Mapping to Logic         D1           Q1          D0            Q1         Open    Q1
                                0 0 1 1                  0 1 1 0                0 0 1 0
                                0 1 1 1                  1 0 1 1                 0 0 1 0
                                             N                           N                 N
                                X X X X                  X X X X                 X X X X
                          D                         D                        D
                                1 1 1 1                  0 1 1 1                 0 0 1 0

                                   Q0                        Q0                    Q0




                                                         D1 = Q1 + D + Q0 N

                                                         D0 = Q0’ N + Q0 N’ + Q1 N + Q1 D

                                                         OPEN = Q1 Q0




             CS 150 - Fall 2000 - Sequential Logic Implementation - 44
Example: Vending Machine (cont’d)

z One-hot Encoding

 present state   inputs      next state   output
 Q3 Q2 Q1 Q0     D N         D3 D2 D1     D0 open
  0 0 0 1        0 0         0 0 0        1    0                    D0 = Q0 D’ N’
                 0 1         0 0 1        0    0
                 1 0         0 1 0        0    0
                 1 1         - - -        -    -                    D1 = Q0 N + Q1 D’ N’
 0 0   1   0     0 0         0 0 1        0    0
                 0 1         0 1 0        0    0                    D2 = Q0 D + Q1 N + Q2 D’ N’
                 1 0         1 0 0        0    0
                 1 1         - - -        -    -
 0 1   0   0     0 0         0 1 0        0    0                    D3 = Q1 D + Q2 D + Q2 N + Q3
                 0 1         1 0 0        0    0
                 1 0         1 0 0        0    0                    OPEN = Q3
                 1 1         - - -        -    -
 1 0   0   0     - -         1 0 0        0    1




                          CS 150 - Fall 2000 - Sequential Logic Implementation - 45
Equivalent Mealy and Moore State Diagrams
z Moore machine                                    Mealy machine
   youtputs associated with                           outputs associated with
    state                                             transitions
      Reset         N’ D’ + Reset                                   Reset/0             (N’ D’ + Reset)/0


                0¢
                             N’ D’                                                    0¢        N’ D’/0
                [0]
               N                                                                N/0

        D       5¢                                                   D/0
                              N’ D’                                                   5¢         N’ D’/0
                [0]
               N                                                                N/0
                10¢
        D                     N’ D’                                  D/1              10¢        N’ D’/0
                [0]
              N+D                                                          N+D/1
                15¢
                              Reset’                                                  15¢        Reset’/1
                [1]


                    CS 150 - Fall 2000 - Sequential Logic Implementation - 46
Example: Traffic Light Controller

z A busy highway is intersected by a little used farmroad
z Detectors C sense the presence of cars waiting on the farmroad
   y with no car on farmroad, light remain green in highway direction
   y if vehicle on farmroad, highway lights go from Green to Yellow to Red,
     allowing the farmroad lights to become green
   y these stay green only as long as a farmroad car is detected but never
     longer than a set interval
   y when these are met, farm lights transition from Green to Yellow to
     Red, allowing highway to return to green
   y even if farmroad vehicles are waiting, highway gets at least a set
     interval as green
z Assume you have an interval timer that generates:
   y a short time pulse (TS) and
   y a long time pulse (TL),
   y in response to a set (ST) signal.
   y TS is to be used for timing yellow lights and TL for green lights

                  CS 150 - Fall 2000 - Sequential Logic Implementation - 47
Example: Traffic Light Controller (cont’)

z Highway/farm road intersection

                             farm road


                                                   car sensors




                                                                         highway




             CS 150 - Fall 2000 - Sequential Logic Implementation - 48
Example: Traffic Light Controller (cont’)

z Tabulation of Inputs and Outputs

  inputs   description                         outputs    description
  reset    place FSM in initial state          HG, HY, HR assert green/yellow/red highway lights
  C        detect vehicle on the farm road     FG, FY, FR assert green/yellow/red highway lights
  TS       short time interval expired         ST         start timing a short or long interval
  TL       long time interval expired



z Tabulation of unique states – some light configurations
  imply others

  state    description
  S0       highway green (farm road red)
  S1       highway yellow (farm road red)
  S2       farm road green (highway red)
  S3       farm road yellow (highway red)


                        CS 150 - Fall 2000 - Sequential Logic Implementation - 49
Example: Traffic Light Controller (cont’)

z State Diagram                                                              Reset
                                                      (TL•C)'


                                                                S0
                                            TL•C / ST                     TS / ST
     S0: HG
     S1: HY                        TS'           S1                            S3      TS'
     S2: FG
     S3: FY                                      TS / ST                  TL+C' / ST
                                                                S2


                                                            (TL+C')'




              CS 150 - Fall 2000 - Sequential Logic Implementation - 50
 Example: Traffic Light Controller (cont’)
 z Generate state table with symbolic states
                                                                          output encoding – similar problem
 z Consider state assignments                                             to state assignment
                                                                          (Green = 00, Yellow = 01, Red = 10)

Inputs               Present State              Next State                       Outputs
C    TL    TS                                                                    ST H           F
0    –     –                HG                         HG                        0    Green     Red
–    0     –                HG                         HG                        0    Green     Red
1    1     –                HG                         HY                        1    Green     Red
–    –     0                HY                         HY                        0    Yellow    Red
–    –     1                HY                         FG                        1    Yellow    Red
1    0     –                FG                         FG                        0    Red       Green
0    –     –                FG                         FY                        1    Red       Green
–    1     –                FG                         FY                        1    Red       Green
–    –     0                FY                         FY                        0    Red       Yellow
–    –     1                FY                         HG                        1    Red       Yellow

    SA1:        HG = 00           HY = 01             FG = 11             FY = 10
    SA2:        HG = 00           HY = 10             FG = 01             FY = 11
    SA3:        HG = 0001         HY = 0010           FG = 0100           FY = 1000       (one-hot)


                            CS 150 - Fall 2000 - Sequential Logic Implementation - 51
Logic for Different State Assignments

z SA1
        NS1 = C•TL'•PS1•PS0 + TS•PS1'•PS0 + TS•PS1•PS0' + C'•PS1•PS0 + TL•PS1•PS0
        NS0 = C•TL•PS1'•PS0' + C•TL'•PS1•PS0 + PS1'•PS0

        ST = C•TL•PS1'•PS0' + TS•PS1'•PS0 + TS•PS1•PS0' + C'•PS1•PS0 + TL•PS1•PS0
        H1 = PS1                            H0 = PS1'•PS0
        F1 = PS1'                           F0 = PS1•PS0'
z SA2
        NS1 = C•TL•PS1' + TS'•PS1 + C'•PS1'•PS0
        NS0 = TS•PS1•PS0' + PS1'•PS0 + TS'•PS1•PS0

        ST = C•TL•PS1' + C'•PS1'•PS0 + TS•PS1
        H1 = PS0                             H0 = PS1•PS0'
        F1 = PS0'                            F0 = PS1•PS0
z SA3
        NS3 = C'•PS2 + TL•PS2 + TS'•PS3                         NS2 = TS•PS1 + C•TL'•PS2
        NS1 = C•TL•PS0 + TS'•PS1                       NS0 = C'•PS0 + TL'•PS0 + TS•PS3

        ST = C•TL•PS0 + TS•PS1 + C'•PS2 + TL•PS2 + TS•PS3
        H1 = PS3 + PS2                       H0 = PS1
        F1 = PS1 + PS0                       F0 = PS3
                     CS 150 - Fall 2000 - Sequential Logic Implementation - 52
 Vending Machine Example (PLD mapping)
D0     = reset'(Q0'N + Q0N' + Q1N + Q1D)
D1     = reset'(Q1 + D + Q0N)
                                                                                   CLK
OPEN   = Q1Q0

                                                                                                Q0
                                                                                     DQ


                                                                                          Seq
                  N


                                                                                                Q1
                                                                                     DQ


                                                                                          Seq
                  D


                                                                                                Open
                                                                                     DQ


                                                                                          Com
               Reset


                       CS 150 - Fall 2000 - Sequential Logic Implementation - 53
Vending Machine (cont’d)
z OPEN = Q1Q0 creates a combinational delay after Q1 and Q0
  change
z This can be corrected by retiming, i.e., move flip-flops and logic
  through each other to improve delay
z OPEN = reset'(Q1 + D + Q0N)(Q0'N + Q0N' + Q1N + Q1D)
       = reset'(Q1Q0N' + Q1N + Q1D + Q0'ND + Q0N'D)
z Implementation now looks like a synchronous Mealy machine
   yCommon for programmable devices to have FF at end of logic




                 CS 150 - Fall 2000 - Sequential Logic Implementation - 54
Vending Machine (Retimed PLD Mapping)
OPEN   = reset'(Q1Q0N' + Q1N + Q1D + Q0'ND + Q0N'D)
                                                                                   CLK


                                                                                                Q0
                                                                                     DQ


                                                                                          Seq
                   N


                                                                                                Q1
                                                                                     DQ


                                                                                          Seq
                   D


            OPEN                                                                                Open
                                                                                     DQ


                                                                                          Seq
              Reset


                       CS 150 - Fall 2000 - Sequential Logic Implementation - 55
Finite State Machine Optimization

z State Minimization
   yFewer states require fewer state bits
   yFewer bits require fewer logic equations
z Encodings: State, Inputs, Outputs
   yState encoding with fewer bits has fewer equations to implement
      xHowever, each may be more complex
   yState encoding with more bits (e.g., one-hot) has simpler
    equations
      xComplexity directly related to complexity of state diagram
   yInput/output encoding may or may not be under designer control




                CS 150 - Fall 2000 - Sequential Logic Implementation - 56
Algorithmic Approach to State Minimization

z Goal – identify and combine states that have
  equivalent behavior
z Equivalent States:
   ySame output
   yFor all input combinations, states transition to same or
    equivalent states
z Algorithm Sketch
   y1. Place all states in one set
   y2. Initially partition set based on output behavior
   y3. Successively partition resulting subsets based on next
    state transitions
   y4. Repeat (3) until no further partitioning is required
      xstates left in the same set are equivalent
   yPolynomial time procedure
                CS 150 - Fall 2000 - Sequential Logic Implementation - 57
State Minimization Example

z Sequence Detector for 010 or 110
                                 Input                              Next State                   Output
                                 Sequence           Present State X=0     X=1                X=0     X=1

                                 Reset              S0                  S1           S2      0      0
                                 0                  S1                  S3           S4      0      0
                                 1                  S2                  S5           S6      0      0
                                 00                 S3                  S0           S0      0      0
                                 01                 S4                  S0           S0      1      0
                                 10                 S5                  S0           S0      0      0
                                 11                 S6                  S0           S0      1      0

                     S0
          0/0                1/0

         S1                      S2
  0/0          1/0         0/0         1/0

   S3          S4          S5          S6
         1/0         1/0         1/0         1/0
   0/0         0/1         0/0         0/1

                                 CS 150 - Fall 2000 - Sequential Logic Implementation - 58
Method of Successive Partitions

      Input                             Next State                        Output
      Sequence          Present State X=0     X=1                     X=0     X=1

      Reset             S0                 S1            S2           0        0
      0                 S1                 S3            S4           0        0
      1                 S2                 S5            S6           0        0
      00                S3                 S0            S0           0        0
      01                S4                 S0            S0           1        0
      10                S5                 S0            S0           0        0
      11                S6                 S0            S0           1        0


      ( S0 S1 S2 S3 S4 S5 S6 )
                                                               S1 is equivalent to S2
      ( S0 S1 S2 S3 S5 ) ( S4 S6 )
                                                               S3 is equivalent to S5
      ( S0 S3 S5 ) ( S1 S2 ) ( S4 S6 )
                                                               S4 is equivalent to S6
      ( S0 ) ( S3 S5 ) ( S1 S2 ) ( S4 S6 )




                 CS 150 - Fall 2000 - Sequential Logic Implementation - 59
Minimized FSM

z State minimized sequence detector for 010 or 110
                  Input                              Next State                 Output
                  Sequence           Present State X=0      X=1              X=0     X=1

                  Reset              S0                 S1'           S1'    0      0
                  0+1                S1'                S3'           S4'    0      0
                  X0                 S3'                S0            S0     0      0
                  X1                 S4'                S0            S0     1      0


                S0

                  X/0

                S1’
         0/0          1/0

        S3’             S4’
          X/0     0/1         1/0



                 CS 150 - Fall 2000 - Sequential Logic Implementation - 60
More Complex State Minimization

z Multiple input example
                                                         inputs here

                 00                     10
           S0               00    S1
           [1]                    [0]
                      01                                 present                next state   output
          10                          11                  state          00     01 10 11
                      11
                                  00 01                     S0           S0     S1 S2 S3     1
                 00              01                         S1           S0     S3 S1 S4     0
           S2                     S3                        S2           S1     S3 S2 S4     1
           [1]        01          [0]                       S3           S1     S0 S4 S5     0
                            10
     10          11                 11                      S4           S0     S1 S2 S5     1
                       01                                   S5           S1     S4 S0 S5     0
          10                10

    00     S4         11          S5         00
           [1]                    [0]
                                                                      symbolic state
                            01                                        transition table
                                        11




                             CS 150 - Fall 2000 - Sequential Logic Implementation - 61
Minimized FSM

z Implication Chart Method
  yCross out incompatible states based on outputs
  yThen cross out more cells if indexed chart entries are
   already crossed out

 S1                                               present             next state           output
                                                   state          00 01 10 11
                                                     S0'          S0' S1 S2 S3'            1
      S0-S1
      S1-S3                                          S1           S0' S3' S1 S3'           0
 S2
      S2-S2                                          S2           S1 S3' S2 S0'            1
      S3-S4                                          S3'          S1 S0' S0' S3'           0
              S0-S1
 S3           S3-S0
              S1-S4
              S4-S5                                                minimized state table
      S0-S0           S1-S0                                        (S0==S4) (S3==S5)
 S4   S1-S1           S3-S1
      S2-S2           S2-S2
      S3-S5           S4-S5
              S0-S1            S1-S1
 S5           S3-S4            S0-S4
              S1-S0            S4-S0
              S4-S5            S5-S5
       S0       S1      S2       S3        S4
                      CS 150 - Fall 2000 - Sequential Logic Implementation - 62
Minimizing Incompletely Specified FSMs

z Equivalence of states is transitive when machine is fully
  specified
z But its not transitive when don't cares are present
      e.g., state output
             S0         –0           S1 is compatible with both S0 and S2
             S1         1–           but S0 and S2 are incompatible
             S2         –1


z No polynomial time algorithm exists for determining best
  grouping of states into equivalent sets that will yield the
  smallest number of final states


              CS 150 - Fall 2000 - Sequential Logic Implementation - 63
Minimizing States May Not Yield Best Circuit

z Example: edge detector - outputs 1 when last two
  input changes from 0 to 1
                                                       X      Q1     Q0         Q1 +   Q0+
           X’                                          0      0      0          0      0
                                                       0      0      1          0      0
         00         X’                                 0      1      1          0      0
         [0]
                                                       1      0      0          0      1
                         01                            1      0      1          1      1
    X’          X        [1]                           1      1      1          1      1
                                                       –      1      0          0      0
         11         X
         [0]
                                                        Q1+ = X (Q1 xor Q0)
           X
                                                        Q0+ = X Q1’ Q0’




                    CS 150 - Fall 2000 - Sequential Logic Implementation - 64
Another Implementation of Edge Detector

z "Ad hoc" solution - not minimal but cheap and fast
            X’

            00
     X’     [0]              X

             X
   10                            01
   [0]                           [1]
             X’

     X’     11               X
            [0]

             X




                  CS 150 - Fall 2000 - Sequential Logic Implementation - 65
State Assignment

z Choose bit vectors to assign to each “symbolic” state
   yWith n state bits for m states there are 2n! / (2n – m)!
             [log n <= m <= 2n]
   y2n codes possible for 1st state, 2n–1 for 2nd, 2n–2 for 3rd, …
   yHuge number even for small values of n and m
      xIntractable for state machines of any size
      xHeuristics are necessary for practical solutions
   yOptimize some metric for the combinational logic
      xSize (amount of logic and number of FFs)
      xSpeed (depth of logic and fanout)
      xDependencies (decomposition)




                CS 150 - Fall 2000 - Sequential Logic Implementation - 66
State Assignment Strategies

z Possible Strategies
   ySequential – just number states as they appear in the state table
   yRandom – pick random codes
   yOne-hot – use as many state bits as there are states (bit=1 –>
    state)
   yOutput – use outputs to help encode states
   yHeuristic – rules of thumb that seem to work in most cases
z No guarantee of optimality – another intractable problem




                CS 150 - Fall 2000 - Sequential Logic Implementation - 67
One-hot State Assignment

z Simple
   yEasy to encode, debug
z Small Logic Functions
   yEach state function requires only predecessor state bits as input
z Good for Programmable Devices
   yLots of flip-flops readily available
   ySimple functions with small support (signals its dependent upon)
z Impractical for Large Machines
   yToo many states require too many flip-flops
   yDecompose FSMs into smaller pieces that can be one-hot encoded
z Many Slight Variations to One-hot
   yOne-hot + all-0

                CS 150 - Fall 2000 - Sequential Logic Implementation - 68
Heuristics for State Assignment

z Adjacent codes to states that share a common next state
   yGroup 1's in next state map                     a                                           b
          I   Q     Q+     O                                                      i/j           i/k
                                            c=i*a + i*b
          i   a     c      j                                                                c
          i   b     c      k

z Adjacent codes to states that share a common ancestor state
   yGroup 1's in next state map                          a
          I   Q     Q+    O                                                        i/j              k/l
                                            b=i *a
          i   a     b     j                 c=k*a
          k   a     c     l                                                             b           c


z Adjacent codes to states that have a common output behavior
   yGroup 1's in output map
          I   Q   + Q      O
                                            j=i *a+ i *c                      a                 c
          i   a     b      j
                                            b=i*a                                   i/j                   i/j
          i   c     d      j                d=i*c
                                                                                    b                   d
                  CS 150 - Fall 2000 - Sequential Logic Implementation - 69
General Approach to Heuristic State
Assignment

z All current methods are variants of this
   y1) Determine which states “attract” each other (weighted pairs)
   y2) Generate constraints on codes (which should be in same cube)
   y3) Place codes on Boolean cube so as to maximize constraints
    satisfied (weighted sum)
z Different weights make sense depending on whether we
  are optimizing for two-level or multi-level forms
z Can't consider all possible embeddings of state clusters
  in Boolean cube
   yHeuristics for ordering embedding
   yTo prune search for best embedding
   yExpand cube (more state bits) to satisfy more constraints

               CS 150 - Fall 2000 - Sequential Logic Implementation - 70
 Output-Based Encoding
  z Reuse outputs as state bits - use outputs to help
    distinguish states
       yWhy create new functions for state bits when output can
        serve as well
       yFits in nicely with synchronous Mealy implementations
  Inputs                Present State             Next State                       Outputs
  C    TL    TS                                                                    ST H          F
  0    –     –                HG                        HG                         0    00       10
  –    0     –                HG                        HG                         0    00       10
  1    1     –                HG                        HY                         1    00       10
  –    –     0                HY                        HY                         0    01       10
  –    –     1                HY                        FG                         1    01       10
  1    0     –                FG                        FG                         0    10       00
  0    –     –                FG                        FY                         1    10       00
  –    1     –                FG                        FY                         1    10       00
  –    –     0                FY                        FY                         0    10       01
  –    –     1                FY                        HG                         1    10       01

HG = ST’ H1’ H0’ F1 F0’ + ST H1 H0’ F1’ F0              Output patterns are unique to states, we do not
HY = ST H1’ H0’ F1 F0’ + ST’ H1’ H0 F1 F0’              need ANY state bits – implement 5 functions
FG = ST H1’ H0 F1 F0’ + ST’ H1 H0’ F1’ F0’              (one for each output) instead of 7 (outputs plus
HY = ST H1 H0’ F1’ F0’ + ST’ H1 H0’ F1’ F0              2 state bits)
                           CS 150 - Fall 2000 - Sequential Logic Implementation - 71
Current State Assignment Approaches

z For tight encodings using close to the minimum number
  of state bits
   yBest of 10 random seems to be adequate (averages as well as
    heuristics)
   yHeuristic approaches are not even close to optimality
   yUsed in custom chip design
z One-hot encoding
   yEasy for small state machines
   yGenerates small equations with easy to estimate complexity
   yCommon in FPGAs and other programmable logic
z Output-based encoding
   yAd hoc - no tools
   yMost common approach taken by human designers
   yYields very small circuits for most FSMs
               CS 150 - Fall 2000 - Sequential Logic Implementation - 72
Sequential Logic Implementation Summary

z Models for representing sequential circuits
   yAbstraction of sequential elements
   yFinite state machines and their state diagrams
   yInputs/outputs
   yMealy, Moore, and synchronous Mealy machines
z Finite state machine design procedure
   yDeriving state diagram
   yDeriving state transition table
   yDetermining next state and output functions
   yImplementing combinational logic
z Implementation of sequential logic
   yState minimization
   yState assignment
   ySupport in programmable logic devices
               CS 150 - Fall 2000 - Sequential Logic Implementation - 73
enting sequential circuits
   Abstraction of sequential elements
   Finite state machines and their state diagrams
   Inputs/outputs
   Mealy, Moore, and synchronous Mealy machines
 Finite state machine design procedure
   Deriving state diagram
   Deriving state transition table
   Determining next state and output functions
   Implementing combinational logic
 Implementation of sequential logic
   State minimization
   State assignment
   Support in programmable logic devices
               CS 150 - Fall 2000 - Sequential Logic Implementation - 73

				
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