Docstoc

無投影片標題

Document Sample
無投影片標題 Powered By Docstoc
					            MSI
Layout Training – Guideline 篇

        Date : 10/03/2002

       Prepared by Jerry Tsai
                                1
                                    1
               Layout Training – Guideline 篇
                             Layout 術語說明
     Trace (Etch) : 分佈在PCB上之走線
     Routing : 佈線 ( 拉線 )
     Placement : 擺放零件至適當位置
     Pin : 零件接腳
     Via : 引導走線於層與層之間的貫穿孔
     Pad : 零件焊點
     Thermal relief (Pad) : 與 Power / GND layer相接之導通點
     Anti-pad:與 Power / GND Layer相隔之隔離點
     Moat : 不同信號的 Power& GND plane 之間的分隔線
     Grid : 佈線時的走線格點
     .DRC : Design RuIe Check
      trace width               pad to pad space
      via size                  pad to trace space
      routing grid               pad to via space
      via to trace space          pad to outline space
      via to via space       . trace to trace space
      via to outline space       trace to outline space
     Test Point : ATE測試點供工廠ICT測試治具使用.
      TP size                                             2
      TP to TP space                                          2
2
                  Layout Training – Guideline 篇

                        The name of gerber file

    • Top Layer : trace and component attached side.(Component side)
    • Bottom Layer : trace and component attached sjde.(Solder side)
    • Power Layer : power signal plane.(電源層)
    • GND Layer:ground signal plane.(接地層)
    • Silk Screen : part ref/part outline/pin number/Model name/ other text.(文字面)
    • Solder Mask : pad soldering avoided. (防焊面)
    • Solder Paste : pad soldering paste.(錫膏面)
    • Drill Map : drill symbol & drill hole size.(孔徑符號與尺寸樑示)
    • NC-Drill : drill tape data for NC punch of PCB factory.(鑽孔座樑程式)




                                                                                3
                                                                                    3
3
                    Layout Training – Guideline 篇

                      4-Layer PCB Stack-up
    Layer 1       Component Side = 0.5 oz Cu
                  Prepreg = 4.5 mils (1 sheet 2116 Prepreg)
    Layer 2       Power Plane = Layer 0 =0.5oz Cu
                 Top Component 1.0 oz Cu (1.4mils +- 0.2mils)
                                                                      62 mi
                  CORE = 47 mils
    Layer 3       Ground Plane = 1.0 oz Cu (1.4mils +- 0.2mils)

                  Prepreg = 4.5 mil (1 sheet 2116 Prepreg)
    Layer 4       Solder Side = 0.5 oz Cu

              • Material is Fiberglass made of FR4

                                                                  4
                                                                        4
4
            Layout Training – Guideline 篇

                     PCB Layer排列方式



    Layer     Definition   Layer     Definition
      1        Signal        1        Signal
      2        VCC           2        GND
      3        GND           3        VCC
      4        Signal        4        Signal




                                                  5
                                                      5
5
                 Layout Training – Guideline 篇

                   Transmission Line ( 傳輸線 )
    • 傳輸線分2種 : Microstrip及Stripline

    • Microstrip :
      一般走在外層的Trace屬於
      Microstrip,例如Component
      size及solder size的Trace


    • Stripline :
      一般走在內層的Trace屬於
      Stripline.


    • Microstrip及Stripline特性阻
      抗不一樣,須避免不同型態的傳
      輸線存在同一條信號上.                                6
                                                     6
6
                   Layout Training – Guideline 篇

                       General Guidelines – 跨Plane
    • 高頻信號走線須注意跨不同Power plane問題,否則因Return Path不好,
      造成信號不好
    • 如下圖:第2層有兩個不同Plane AGND及DGND,圖(二)Clcok trace同時跨
      在AGND及DGND,此信號一定不好

       Another            Clock trace                          Clock
       ground                              Another             trace
       plane                               ground
                                           plane


                                Relative                      Relative
                                ground                        ground
           AGND
                                plane                         plane
                   DGND                       AGND    DGND


           圖(一)                               圖(二)
         RECOMMENDED                        NOT RECOMMENDED
                                                                         7
                                                                             7
7
               Layout Training – Guideline 篇

                  General Guidelines – 繞線
    • Serpentine trace (蛇行線) : 一般在Bus或clock應用上,常為了要求
      等長,必須將較短的Trace要求繞線增加長度,方能達到所要求的長度.
    • 繞線須注意那些事項 : 首先要注意繞線本身的間距S,S間距越小,
      couple效應越明顯,信號越差,所以S越大越好,但因空間有限,依3-W原
      則,S必須為2倍線寬為佳.




                                               8
                                                   8
8
                         Layout Training – Guideline 篇

                             General Guidelines – 3W
    • 何謂3-W法則:
    • 例如當信號Trace寬度為6 mils(W),則Trace兩旁space需為12 mils(2W)
      此3-W法則可涵蓋70%的通量邊界(Flux boundary),可降低兩條線之間的
      crosstalk效應,一般針對高頻信號(例如clock)而言,經常運用3-W法則
      來減少crosstalk.


        Adjacent trace
                                                        12 mils ( 2W )

        Clock trace                                     6 mils ( 1W )

                                                        12 mils ( 2W )
         Adjacent trace

                          Note : 兩條Trace之間不能有VIA(貫穿孔)



                                                                         9
                                                                             9
9
                   Layout Training – Guideline 篇

               General Guidelines – Damping Resistor

     • Damping 電阻: 一般高頻信號在source端會加一顆串接電阻作阻抗匹配
       即稱為Damping電阻,最常見應用就是clock signals,而Damping
       resistor擺的位置必須靠近source端(越近越好),如下圖所示


                    越短越好



                                              Chips
       Clock       Damping
       Generator   Resistor




                                                      10
                                                           10
10
                          Layout Training – Guideline 篇

                    General Guidelines – Bypass Capacitor
     • Power : 一般IC都需要有Power才能正常工作,Power通常是接到IC的VCC
       及Gnd pin.
                             +                               VCC
                                      電源                                 IC
                             _
                                                             GND

     • Bypass電容 : 一般為了讓IC能得到較穩定電源,通常會在VCC pin加
       bypass電容濾雜訊.Bypass電容位置越靠近IC越好,太遠則沒有效果

       Trace width : least 10 mils.        As short as possible
                                                                                           Via to VCC plane

       Via to VCC plane                    VCC      IC                                     VCC


             Via to GND plane                                     Via to GND plane
                                           GND                                             GND

                                           Good                                      Bad          11
                                                                                                        11
11
              Layout Training – Guideline 篇

              General Guidelines – Power Trace
     • Power Trace : Trace寬度依流過電流大小來決定,電流越大線寬越粗,
       一般小電流線寬為10 mils,大電流理想線寬每1安培40 mils.
     • Power Trace太細則易造成Power不好及Drop電壓太大




                                                 12
                                                      12
12
                     Layout Training – Guideline 篇
                                 Springdale chips 範例解說

                                   P4 CPU
                                          Host Bus
                                          400/533/667 MHz                         DDR
AGP                   2.1 GB/s     Springdale           Channel A                 DDR
8x/4x                                                      2.1 ~ 2.7 GB/s
                                   GMCH
Lan                   266 MB/s                             Channel B              DDR
10/100 or Gigabit                  ( 北橋 )                  2.1 ~ 2.7 GB/s         DDR
                                            Hub Link
                                            266 MB/S
USB 2.0 (8 port)                   Intel                               AC97 C\odec
480 Mb/s

2 Serial ATA Ports                 ICH5                                PCI Bus
150MB/s                                                                Support 6 masters
                                   ( 南橋 )              LPC interface
ATA 100                                                                Super IO
IDE1 & IDE 2
                                                                       BIOS
                                                                                           13
                                                                                                13
                    Layout Training – Guideline 篇

                            Clock Routing Guideline

                             Host bus clocks (I)
                Clock Gen




     • Host Clocks 有3對differential clocks : CPUCLK&CPUCLK#,
       MCHCLK/MCHCLK#, ITP_CLK/ITP_CLK#.
     • Differential Clocks should be routed on same layer.如須換Layer則via hole
       盡量靠近RS ( Damping Resistor )
     • Keep more than 28 mils spacing for CLOCK to other traces.



                                                                  14
                                                                       14
14
                            Layout Training – Guideline 篇

                Clock Gen
                                  Host bus clocks (II)
                    CLK
                             L1   RS     L2                   L4
                                                                        CPU
                    CLK#
                             L1’ RS      L2’                  L4’         Or
                                              L3         L3
                                                   R R                  MCH
                   Lclk = L1+L2+L4                 T T
                   Lclk# = L1’+L2’+L4’
            Signal Name     L1,L1' Length L2,L2' Length L3,L3' Length L4,L4' Length
         CPU Routing Length    0 ~ 0.5"      0 ~ 0.2"      0 ~ 0.2"      2 ~ 12"
         MCH Routing Length 0 ~ 0.5"         0 ~ 0.2"      0 ~ 0.2"      2 ~ 12"
     •    RS ( Damping Resistor ) : Closed to Clock generator within 0.5 inch.
     •    RT ( Pull-down terminator resistor ) : Closed to RS.
     •    Traces width = 5 mils, Differential spacing = 11 mils, other spacing = 25mils.
     •    Differential clock ( CLK & CLK# )必須從頭到尾平行走並保持相同間距11 mils.
     •    Lclk# = Lclk + 10 mils. All Host Clocks must be Ground Reference.
     •    Zd = 100 ohm+/-15%, Zs = 50 ohm + 15%.

                                                                                      15
                                                                                           15
15
                         Layout Training – Guideline 篇
                          66 and 33 MHz Clocks
     • All Clocks must be Ground Reference.
     • 66MHz/33MHz Clock Relationships
        Signal Name        Trace width   CKG to RS   RS to Target          Spacing     Matching
        CLK_66 to MCH      5 mils        0 ~ 0.5"    X (4" ~ 8.5" )        20 mils     +/- 100 mils
        CLK_66 to ICH      5 mils        0 ~ 0.5"    X +/- 100 mils        20 mils     +/- 100 mils
        PCI33 to Slot      5 mils        0 ~ 0.5"    X-2.5"                15 mils     +/- 500 mils
        CLK_33 to ICH      5 mils        0 ~ 0.5"    X +/- 100 mils        15 mils     +/- 100 mils
        CLK_33 to FWH      5 mils        0 ~ 0.5"    X +/- 100 mils        15 mils     +/- 100 mils
        CLK_33 to SIO      5 mils        0 ~ 0.5"    X +/- 100 mils        15 mils     +/- 100 mils


      Note1 : Must be matched to +/-100 mils of CLK66 total length.
     • CLK14 Clock group
         Name       Trace Width    Spacing    Spacing to Others       CKGto R    R to Trace-B   Matching
     CLK14 to ICH5     5 mils      10 mils         10 mils             0~0.5"       0~12"       +/-0.5"
      CLK14 to SIO     5 mils      10 mils         10 mils             0~0.5"       0~12"       +/-0.5"
     CLK14 to Audio    5 mils      10 mils         10 mils             0~0.5"       0~12"       +/-0.5"




                                                                                                       16
                                                                                                            16
16
                   Layout Training – Guideline 篇
                            48 MHz Clocks
     • All Clocks must be Ground Reference.
     • 66MHz/33MHz Clock Relationships
     Signal Name   Trace width   CKG to R   R to Target   Spacing   Matching
     USB_48        5 mils        0 ~ 0.5"   3"~12"        20 mils   N/A
     DOT_48        5 mils        0 ~ 0.5"   2"~9"         20 mils   N/A




                                                                               17
                                                                                    17
17
                          Layout Training – Guideline 篇
                     Serial ATA 100 MHz Clocks
                            L1    RS    L2                   L4
                 CKG        L1’ RS      L2’                  L4’
                                                                          ICH5
                                             L3         L3
                   LT = L1+L2+L4                  R R
                                                  T T

            Signal Name      L1,L1' Length L2,L2' Length L3,L3' Length L4,L4' Length
         SATA Routing Length    0 ~ 0.5"      0 ~ 0.2"      0 ~ 0.2"      2 ~ 12"


     •   Traces width = 5 mils, Diff: spacing = 11 mils, other spacing = 25mils.
     •   Zd = 100 ohm+/-15%, Zs = 50 ohm + 15%.
     •   LT’ = LT + 10 mils.0
     •   RS = 33 ohm + 1%, RT = 49.9 ohm + 1%.
     •   All Host Clocks must be Ground Reference.


                                                                                   18
                                                                                        18
18
                               Layout Training – Guideline 篇

                                  Host Bus – AGTL+ Signal
         Signal Type        Signal Name           Trace width   Spacing         Signal length    Length mismatch
         Data               HD0 ~ HD63            5 mils        13mils          2.5" ~ 6"        +/- 10 mils
         Data Strobe        HDSTBP#[3:0]          5 mils        17 mils         2.5" ~ 6"        +/- 5 mils
         ( Differential )   HDSTBN#[3:0]
         Address        HA#3 ~ HA#31        5 mils              13 mils         3" ~ 10"         +/- 50 mils
         Address Strobe HADSTB[1:0]#        5 mils              17 mils         3" ~ 10"         +/- 5 mils
         Another        CPU Another Signals 5 mils              13 mils         3" ~ 8"          +/- 100 mils

         Group   Signals                 相對應的 Strobe            •   DSTBP[3:0]# and DSTBN[3:0]# 是4對differential
           1     HREQ#[4:0], HA[#16:3]   HADSTB#0                   strobe signal, differential 信號 spacing = 17 mils,
           2     HA#[31:17]              HADSTB#1                   與其他線的spacing = 20 mils
           3     HD#[15:0], HDBI#0       HDSTBP#0, HDSTBN#0                                Other trace
           4     HD#[31:16],HDBI#1       HDSTBP#1, HDSTBN#1                     20 mils
           5     HD#[47:32], HDBI#2      HDSTBP#2, HDSTBN#2                                 HDSTBP#0
           6     HD#[63:48], HDBI#3      HDSTBP#3, HDSTBN#3                     17 mils
                                                                                            HDSTBN#0

     •   同一 Group 信號必須佈線在同一Layer並作等長處理, 例如 HA#[31:17]及HADSTB#1
         必須在同一層.
     •   Trace length = GMCH’s package length + CPU’s package length + M/B trace length 19
                                                                                                                   19
19
                    Layout Training – Guideline 篇
                                  Host Bus -
     Asynchronous GTL+ and other signals (I)
       • Trace width = 5 mils, Impedance = 60 ohm.
     Signal Name   Topologies   L1 length   L2 length   Spacing   Rpu close to
     FERR#         1            1" ~ 12"    3" max      7 mils    ICH5
     PROCHOT#      1            1" ~ 17"    3" max      7 mils    ICH5
     THERMTRIP#    1            1" ~ 12"    3" max      7 mils    ICH5
     A20M#         2            12" max     N/A         5 mils    ICH5
     IGNNE#        2            12" max     N/A         5 mils    ICH5
     LINT [1:0]    2            12" max     N/A         5 mils    ICH5
     SLP#          2            12" max     N/A         5 mils    ICH5
     SMI#          2            12" max     N/A         5 mils    ICH5
     STPCLK#       2            12" max     N/A         5 mils    ICH5
     INIT#         3            17" max     N/A         5 mils    CPU
     PWRGOOD       3            1" ~ 12"    3" max      13 mils   CPU
     RESET#        3            N/A         N/A         13 mils   CPU
     BR0#          4            N/A         N/A         13 mils   CPU
     COMP[1:0]     4            1.5" max    N/A         13 mils   CPU
     TESTHI        4            1" max      N/A         7 mils    CPU




                                                                                 20
                                                                                      20
20
                            Layout Training – Guideline 篇

                               Host Bus - VREF
     • AGTL+ GTLREF1 :
        – Trace width is 12 mils, Spacing is 15 mils far away another signals.
        – 220pF (C2) cap trace length within 1.5 inches of CPU pin.
        – 0.1uF (C1) cap trace length within 3inch of divided resistors.
                                       VTT           VCCP



                                R626                        R1
                              200RST                        200RST
             GTLREF
             0.63*VCC_AVG
                                             C2     C1      R2
                               C312                 0.1u    169RST
                               220p          220p



                  PLACE CLOSE TO GMCH        PLACE CLOSE TO CPU

     • Vref是很重要信號, 也是很sensitive,其電流很小亦受干擾,所以線
       寬要粗及線距要大,佈線需小心處理.
                                                                                 21
                                                                                      21
21
                             Layout Training – Guideline 篇
                                      Host Bus -
                         Asynchronous GTL+ and other signals (II)
     •       Topologies 1 : FERR, THERMTRI#.              •    Topologies 3 : RESET#, BR0#

                                                              VCC_P
                                            VCC_P
                                                                   Rpu                     ICH5/
                                                                                           GMCH
                               ICH5/             Rpu
                CPU           ICH5
                               GMCH                                300 Ohm
                                                                             CPU           GMCH
                                                 62 Ohm
                                                                   +/-5%
                                                 +/-5%
                        L1             L2                                             L1
                                                                      L2



         •    Topologies 2 : A20M#, IGNNE#,               •    Topologies 4 : IERR#
              SMI#, SLP#, STPCLK#,LINT[1:0]
                                                                                   VCC_P
                                                                               Rtt
                                      ICH2
                                       ICH5
                  CPU                IO driven
                                     f rom CPU                    Chipset
                                                                                             CPU
                                                                    or
                                                                  Logic IC
                         L1=12"max


                                                                                              22
                                                                                                   22
22
                          Layout Training – Guideline 篇

                             GMCH Vref Rules
     • Reference voltage layout guideline:
         – HSWING and relative component (R42, R45) place < 3” of GMCH with W=12,
           S=12mil . Place C10 close to GMCH as possible.
         – For GTLREF, route with W=12, S=12mil . Place C6 close to GMCH as possible.
         – HL_SWING & HL_VREF route < 4” with W=12, S=10mil. Place C25, C26 close
           to as possible.
         – Place R41, R62, R66, R63 close to GMCH < 0.5” & W=10, S=7 mil.
                                           VCCP




                                C7            R42
                                X_0.01u       301RST
                                1/4*Vccp
             {5} HSWING
                                C10           R45
                                0.01u         100RST



     •   HL_SWING/ HL_VREF/ GTLREF 都是屬於Vref信號,都很重要信號, 也是很
         sensitive,其電流很小亦受干擾,所以線寬要粗及線距要大,佈線需小心處理.
                                                                                  23
                                                                                        23
23
                          Layout Training – Guideline 篇

                      GMCH Analog Filter Rule
     • Analog Filter layout guideline:
         – 一般chips PLL power都會一組L /C Filter,以確保power是 乾淨不被干擾,所以
           其佈線是很重要, 除了L/C filter需靠近chips端,及線寬/線距的規範,還須注意是
           否有跨不同 power plane的問題.
         – For VCCA_DPLL, place C9, CT12, L4, R44 close to GMCH pin B3, route W=25,
           S=10 mils.
         – For VCCA_FSB, place C8, CT1, L3, R43 close to GMCH pin A31, route W=25,
           S=10 mils.
         – For VCCA_DDR, place C20, C21, L5 close to GMCH , route W=50, S=15mil.
         – For VCCA_DAC, place CB26, C27, CT27, L6, R503 close to GMCH, route the
           ground pin for C1 and C2 need to connect to ground and be routed next to
           VCC_DAC (pin C2) back to the GMCH to the VSS_DAC pin (pin D3), route
           W=18, S=10mil.
                                     ESR is 0.1mohm to GMCH
                   I=35mA
                 VCCA _DPLL                    L4    100nH- 300mA   DPLL   R44   1RST
                                                                                        VCC_AGP
                                         +




                              C9             CT2
                              0.1u           100u_6.3V
             W=25,S=10 mils                    ALU
                                                         CLOSE TO PINB3                           24
                                                                                                       24
24
                      Layout Training – Guideline 篇

                          DDR Routing guide
     • DDR Channel Stack-up :
                      M/B Layer              Description
                       Layer 1              Signal / Power
                       Layer 2              GND Cutouts
                       Layer 3                  GND
                       Layer 4              Signal / Power




        1. All DDR signal’s must reference to the GND Cutouts (Layer2 ) and
             GND plane (Layer 3).
        2. The CPU and DDR GND flood on layer 2 must be connect together.
        3. The GND plane reach before the last termination resistors.
        4. Layer 1 and 4 will put power floor and must first put it.
        5. Layer 1 rout the all Channel A signals.
        6. Layer 4 rout the all Channel B signals.


                                                                              25
                                                                                   25
25
                     Layout Training – Guideline 篇

            DDR Signal Group of Each Channel
     •   1. CPC Address (SMA_A[5:1])
     •   2. Control (SCS[1:0]#, SCKE[1:0])
     •   3. CLOCK (SCK[2:0], SCK[2:0]#)
     •   4. Address/Command (SMAA[12:6,0],SBA[1:0],SRAS#,SCAS#,SWE#)
     •   5. Data Group (SDQ[63:0], SDQS[7:0], SDM[7:0])


     • All total trace length which are measured form GMCH die to
       DIMM connector = package length of GMCH+ M/B trace
       length of DIMM.



                                                                26
                                                                       26
26
                                     Layout Training – Guideline 篇

                                            DDR Routing guide
     • Data Group Routing Guidelines – SDQ[63:0], SDQS[7:0], SDM[7:0]
       MCH pkg
                                DIMM1       DIMM2                          DIMM3       DIMM4
                                                                                                         Figure 2
                   Pkg length
     GMCH
      Pad                                                                                           Rt       Vtt
                                                         Rt       Vtt E
                            A           B           C         D                    F           G         H
      Signal pin
                                                                                                                        Layer 2
                                                                                                                        Layer 3


                                                                                                         Figure 3
          5mils                             7mils                  7mils
                            12mils                      15mils                20mils
           SDM                              SDQ                    SDQS                   Non-DDR
                                                  VSS(Layer 2)
                                                                                          Prepreg


                                                                                                                   27
                                                                                                                          27
27
                              Layout Training – Guideline 篇

                                   DDR Routing guide
     • Data Group Routing Guidelines
              Reference Plane                               Ground reference                       2
           Trace Impedance (Zo)                              60 Ohm 15+/-%
               Trace Width                          5 mils(SDM),7 mils(SDQ/SDQS)                   3
                                      * GMCH to 1'st DIMM =10/15mils for Data/Strobe               3
                                      * Within DIMM pin field =7 mils minimum                      3
                 Spacing
                                      * From DIMM to DIMM = 12 mils                                3
                                      * 2'nd DIMM to Rt = 5 mils for CHANNEL A 5:10 for B          3
              Group Spacing                          20 mils from non-DDR signals                  3
              Trace length-A                                   MAX=5.8"                            2
              Trace length-B               Max=500 mils, Resistor place < 500 mil to DIMM1         2
              Trace length-C                               400 mils ~ 600 mils                     2
              Trace length-D                                 MAX= 800 mils                         2
            Via count per signal             0 ( Data/Strobe/Mask must route on Layer 1)           2
          MCH breakout guidelines          5 mil width with 7 mil spacing for a max of 350 mils
                                      * SDQ[63:0], SCB[7:0] to SDQS[8:0]                          5,6
       Length matching requirements
                                      * SDQS[8:0] to SCK/SCK#[5:0]                                5,6




                                                                                                        28
                                                                                                             28
28
                          Layout Training – Guideline 篇

                               DDR Routing guide
                                          DIMM1   DIMM2
                    Figure 5


                                   DQ
     GMCH package
                                   DQ
                                                          DIMM1 DQ/DM length
                                   DQ
                                                          =(X1+/-25 mils)
                                   DQ

                    MCH            DQS                    DIMM1 DQS length=X1
                    DIE            DM                     DIMM2 DQS length=X2
                                   DQ
                                                          DIMM2 DQ/DM length
                                   DQ
                                                          =(X2+/-25 mils)
                                   DQ




                                                                  29
                                                                         29
29
                         Layout Training – Guideline 篇

                          DDR Routing guide
                                           DIMM1   DIMM2
               Figure 6


                                                           A-4.4”<=DQS=X1
                               SDQS[8:0]
     MCH package

                               SCK[2:0]                    SCK/SCK#[2:0]
                               SCK#[2:0]
                                                           length=A

                   MCH
                   DIE         SDQS[8:0]                   (A+0.5”)-4.4”<=DQS=X2

                               SCK[5:3]
                                                           SCK/SCK#[5:3]
                               SCK#[5:3]
                                                           length=A+0.5”




                                                                   30
                                                                            30
30
                                       Layout Training – Guideline 篇

                                        DDR Routing guide
     • Control Signal Routing Guidelines – SCKE[3:0], SCS#[3:0]
       MCH pkg
                                            DIMM1       DIMM2
                                                                                    Figure 7
             Pkg length
      MCH
       Pad              Signal pin
                                                                    Rt
             A                          C                       D         Vtt
                                                                                 Layer 2
                                                                                 Layer 3
                              B

       MCH pkg                                                                      Figure 8
                                            DIMM1       DIMM2

                 Pkg length
      MCH
       Pad                Signal pin
                                                                     Rt
             A                                      C           D          Vtt
                                                                                  Layer 2
                                                                                  Layer 3
                              B                                                                31
                                                                                                    31
31
                              Layout Training – Guideline 篇

                                  DDR Routing guide
     • Control Signal Routing Guidelines
                  Parameter                                Routing Guideline                        Figure
                 Signal Group                      Control - SCKE[3:0], SCS#[3:0]                             Table 2
                   Topology                                   Point to point                          7,8
                Reference Plane                            Ground reference                           7,8
             Trace Impedance (Zo)                          60 Ohm 15+/-%
                 Trace Width                                     5 mils                                9
                                       * MCH to 1'st DIMM =12 mils                                     9
                                       * Within DIMM pin field =7 mils minimum                         9
                    Spacing
                                       * From DIMM to DIMM = 12 mils                                   9
                                       * 2'nd DIMM to Rt = 5 mils CHANNEL A, 7mils for B               9
                 Group Spacing                       20 mils from non-DDR signals                      9
                 Trace length-A                            Less then 50 mils                          7,8
              Trace length B+C/C'          MAX= 3.5"/If have 2nd via need less then 500 mils/1.0"     7,8
               Trace length-D/D'                              MAX=1.4" / 0.8"                         7,8
              Via count per signal                  4(Without additional trace segments)              7,8
           MCH breakout guidelines           5 mil width with 6 mil spacing for a max of 350 mils
          Signal transition Via distance 500 mils mas from the pin on the 1'st DIMM con.
          Length matching requirements SCS#/SCKE[3:0] to SCK/SCK#[5:0]                              Noted 2
                                                                                                               32
          2.5V Copper Flood spacing Isolatio spacing from the 2.5V copper on layer4 = 7 mils(min)                       32
32
                          Layout Training – Guideline 篇

                           DDR Routing guide
     • Control Signal Routing Guidelines
                                                                             Figure 9
                            5mils                5mils
                 20mils               Table2               7mils
      Non-DDR             SCS#/SCKE            SCS#/SCKE            2.5V
                                      GND
                                                                   Prepreg




       Note2 : SCS#/SCKE[1:0] <= SCK/SCK#[2:0]- 3.4”. MAX length to DIM1 <=3.5”.
               SCS#/SCKE[2:3] <= SCK/SCK#[5:3]- 3.4”. MAX length to DIMM2 <=4”




                                                                                        33
                                                                                             33
33
                                   Layout Training – Guideline 篇

                                    DDR Routing guide
     • Command Signal – SMA[12:6,0],SBS[1:0],SRAS#,SCAS#.SWE#
      MCH pkg
                                     DIMM1       DIMM2
                                                                                          Figure 13
             Pkg length
      MCH
       Pad            Signal pin
                                                                 Rt
             A                               C           D
                                                                                        Layer 2
                                                                                        Layer 3
                 B

                                    5mils                5mils                            Figure 14

                                   Command Table3 Command                      2.5V
      Non-DDR 20mils                                                  7mils
                                    Signal         Signal                     Copper

                                             GND
                                                                              Prepreg


                                                                                                      34
                                                                                                           34
34
                              Layout Training – Guideline 篇

                                  DDR Routing guide
     • Command Signal Routing Guidelines
               Parameter                                     Routing Guideline                    Figure   Table 3
              Signal Group          Command - SMA[12:6,3,0], SBS[1:0], SEAS#, SCAS#, SWE#
                Topology                                        Daisy Chain                        13
             Reference Plane                                 Ground reference                      13
          Trace Impedance (Zo)                               60 Ohm 15+/-%
              Trace Width                                          5 mils                          14
                                    * MCH to 1'st DIMM =12 mils                                    14
                                    * Within DIMM pin field =6 mils minimum                        14
                 Spacing
                                    * From DIMM to DIMM = 12 mils                                  14
                                    * 2'nd DIMM to Rt = 5 mils for CHANNEL A, 7mils for B          14
              Group Spacing                           20 mils from non-DDR signals                 14
              Trace length-A                                 Less then 50 mils                     13
              Trace length-B                                    MAX=4.0"                           13
              Trace length-C                                    0.4" ~ 0.6"                        13
              Trace length-D                                    MAX=0.8"
           Via count per signal                   4(Without additional trace segments)             13
        MCH breakout guidelines            5 mil width with 6 mil spacing for a max of 350 mils
       Length matching requirements Command to SCK/SCK[5:0]                                       Note 3
       2.5V Copper Flood spacing Isolatio spacing from the 2.5V copper on layer4 = 7 mils(min)



                                                                                                             35
                                                                                                                     35
35
                          Layout Training – Guideline 篇

                             DDR Routing guide
     • Command Signal Routing Guidelines

     Note3 :
       Command trace length <= SCK/SCK#[2:0] - 1.9” for DIMM1.
       Command trace length <= SCK/SCK#[5:3] - 1.9” for DIMM2




                                                                 36
                                                                      36
36
                                   Layout Training – Guideline 篇

                                    DDR Routing guide
     • CPC Address Signal – SMA[5:1], SMB[5:1]
      MCH pkg
                                     DIMM1    DIMM2
                                                                               Figure 15
             Pkg length
      MCH
       Pad            Signal pin
                                                              Rt
             A                                        D
                                                                             Layer 2
                                                                             Layer 3
                 B

                                    7mils             7mils                    Figure 16
                 C

                     CPC Address Table4 CPC Address 7mils           2.5V
      Non-DDR 20mils
                       Signal             Signal                   Copper

                                             GND
                                                                   Prepreg


                                                                                           37
                                                                                                37
37
                               Layout Training – Guideline 篇

                                   DDR Routing guide
     CPC Address Signal Routing Guidelines
                Parameter                                     Routing Guideline                    Figure   Table 4
               Signal Group                   CPC Address - SMA[5,4,2,1], SMB[5,4,2,1]
                 Topology                                         Daisy Chain                       15
              Reference Plane                                 Ground reference                      15
           Trace Impedance (Zo)                                60 Ohm 15+/-%
               Trace Width                                           7 mils                         16
                                     * MCH to 1'st DIMM =12 mils                                    16
                                     * Within DIMM pin field =5:5 mils minimum                      16
                  Spacing
                                     * 2'nd DIMM to Rt = 5 mils for CHANNEL A, 7 mils for B         16
                                     * 4'th DIMM to Rt= 5 on 5 mils                                 16
               Group Spacing                           20 mils from non-DDR signals                 16
                                      max 1 address/command can route next to CPC address signal    16
          Trace length-A Breakout              width 5 mil space 6 mil < 200 mils from ball.        15
                                             width 5 mil space 8 mil for addition 550 mils after    15
                                                          the first 200mil from ball.               15
         Trace length-B to DIMM1                                  MAX=2.5"                          15
         Trace length-C to DIMM2                                  MAX=3.0"                          15
             Trace length-D/D'               MAX=1.4" for DIMM1/MAX=0.8" for DIMM2
            Via count per signal                   4(Without additional trace segments)             15
         MCH breakout guidelines            5 mil width with 6 mil spacing for a max of 350 mils
        Length matching requirements Command to SCK/SCK[5:0]                                       Note 4
        2.5V Copper Flood spacing Isolatio spacing from the 2.5V copper on layer4 = 7 mils(min)
                                                                                                              38
                                                                                                                      38
38
                           Layout Training – Guideline 篇

                              DDR Routing guide
     • CPC Address Signal Routing Guidelines

     Note4 :
       CPC Address trace length <= SCK/SCK#[2:0] – 4.4” for DIMM1.
       CPC Address trace length <= SCK/SCK#[5:3] - 4.4” for DIMM2




                                                                     39
                                                                          39
39
                               Layout Training – Guideline 篇

                                   DDR Routing guide
     • Clock Signals – SCK[5:0], SCK#[5:0]
                   Parameter                                  Routing Guideline                   Figure
                  Signal Group                           Clock - SCK/SCK#[5:0]
                   Topology                                     Ponit to Point                    18,19
                Reference Plane                               Ground reference                    18,19
            Trace Impedance (Zo)                            Differential 60 Ohm
                  Trace Width           5mils (Ball) /8 mils (Before DIMM) /6mils (After DIMM)    20,21
           Differential Trace Spacing                               5 mils                        20,21
                 Group Spacing                20 mils from other signal/15 mil to 2.5v Flood      20,21
                 Trace length-A                                 Max 50 mils                       18,19
               Trace length-B/B'                         MAX=7.4" /MAX=7.9"                       18,19
          Maximum via count pre signal                                  1                         18,19
          GMCH breakout guidelines         5 mil width with 5 mil spacing for a max of 450 mils
                                      SCK[0:2]#=SCK[0:2}+/-5mils
         Length matching requirements
                                      SCK[5:3]#=/SCK[5:3]+/-5mils
         Clock relation DIMM1&2       SCK[5:3]/SCK[5:3}#=SCK[0:2]/SCK[2:0]#+0.5"
         Clock space for serpentines                 20 mils for itself during serpentines




                                                                                                           40
                                                                                                                40
40
                                       Layout Training – Guideline 篇

                                           DDR Routing guide
     • Clock Signals – SCK[5:0], SCK#[5:0]
      GMCH pkg
                                           DIMM1           DIMM2
                                                                   • A+B+C<7inchs                Figure 18
            Pkg length
     GMCH                                                          • D<950mils
      Pad             Signal pin


            A      B               C               D
                                                                   • SCK[0:2] <500mils
                                                                                       Layer 2
                                                                                       Layer 3

      GMCH pkg
                                           DIMM1           DIMM2   DIMM3       DIMM4
                                                                                                 Figure 19
            Pkg length
     GMCH
      Pad             Signal pin


            A
                                                                                       Layer 2
                                                                                       Layer 3

                  B                    C               D                   E
                                                                                                 41
                                                                                                      41
41
                     Layout Training – Guideline 篇
                         DDR Routing guide
     • Clock Signals – SCK[5:0], SCK#[5:0]
                           8mils            8mils

                          SCK#              SCK                2.5V
        Non-DDR 20mils             5 mils            15mils
                          Signal            Signal            Copper   Figure 20
                                   GND                                 Prepreg

                           6mils            6mils

                          SCK#              SCK                2.5V
        Non-DDR 20mils             5 mils            15mils
                          Signal            Signal            Copper   Figure 21
                                   GND                                 Prepreg


     • SCK#[2:0]=SCK[2:0] +/- 5 mils
     • SCK#[5:3]=SCK[5:3] +/- 5 mils
     • SCK#[5:3]/SCK[5:3]=SCK#[2:0]/SCK[2:0]+0.5”
                                                                        42
                                                                                 42
42
                       Layout Training – Guideline 篇
                      AGP Routing Guidelines
                           Misc. Signals Guidelines
      VREF Routing
         Divider parts (R754, R272) placed close to GMCH keep separated to other signal
          > 25 mils with width=12 mils.
         One 0.1uf (C117) cap placed within 150 mils of the GMCH.
      GMCH AGP_RCOMP Routing
         Place R66 close to GMCH < 0.5” with trace width = 5 mils




                                                                                  43
                                                                                       43
43
                        Layout Training – Guideline 篇

                         Hub Interface Signals
     Signal Name        Trace Length   Trace Spacing   Spacing to other   Max Length   Matching
     HL_STRB,HL_STRB#   5 mils         15 mils         20 mils            8"           +/- 10 mils of Strobe
     HL[7:0]            5 mils         15 mils         N/A                8"           +/- 50 mils of HL_STRB
     HL[8]=REQM         5 mils         15 mils         N/A                8"           +/- 50 mils of HL_STRB
     HL[9]=REQI         5 mils         15 mils         N/A                8"           +/- 50 mils of HL_STRB
     HL[10]=PSTOP       5 mils         15 mils         N/A                8"           +/- 50 mils of HL_STRB
     HL_RCOMP (R81)     10 mils        7 mils          7 mils             0.5"


                  Hub Interface signals must reference to Ground
     • Reference & Swing voltage
          – HL_VREF & HL_SWING divider (R67, R69, R71, C30, C31)
            should be placed < 4” of GMCH with width 12mils, space=10 mils.
          – Decoupling caps ( C25, C26) place within 250mils of GMCH.
          – H_VREF & H_SWING divider (R68, R70, C80, C82) should be
            placed < 4” of ICH4 with width 12mils, space=10 mils.
          – Decoupling caps ( C32, C33) place within 250mils of ICH4.
                                                                                                     44
                                                                                                           44
44
                   Layout Training – Guideline 篇
                         ICH5 Signals(1)
     • IDE1 Routing
        – All IDE trace width = 5 mils, Spacing = 10 mils.
        – All IDE signals max. trace length must less the 8”(From ICH5 to IDE
          connector).
        – If PD_IOW#=PD_IOR#=X”+/-0.05”, PDD[0--15]=X”+/- 0.25”,




     • PCI Signals
        – Routing requirement width=5 mils , space= 7 mils.
        – ICH4 to 1st PCI slot = 4”~ 10”. 1st PCI slot to 2nd PCI slot <
          1”, 2nd PCI slot to 3rd PCI slot < 1”.


                                                                                45
                                                                                     45
45
               Layout Training – Guideline 篇

                    ICH5 Signals(2)
     • USB 2.0 interface(I)
        – Routing : 7.5 mils wide, 7.5 mils spacing between Differential pairs.
          Differential pair to differential pair space= 20 mils.
        – To other signals spacing=20 mils , spacing=50 mils to clock signal or
          high speed periodic signal.
        – Each P+/P- differential pair must be routed together, parallel to each
          other on the same layer. The P+/P- traces length mismatch < +/- 150
          mil.
        – Maximum length for Back panel USB signal < 17”.
        – Don’t route over plane splits or under clock generator and crystal.
                clock signal

                 Space = 50 mils
                  USB P+
                 Space = 7.5 mils           Differential pair
                  USB P-
                 Space = 20 mils
                 Other signals                                          46
                                                                             46
46
                Layout Training – Guideline 篇

                   ICH5 Signals(2)
     • USB 2.0 interface(2)

        –   USB signal must > 90mils to PCB edge.
        –   USB signal stub length must < 200 mil.
        –   USB signal must > 25mils to plane splits.
        –   USB2.0 signal must be Ground reference.




                                                        47
                                                             47
47
                               Layout Training – Guideline 篇

                                              ICH5 Signals(5)
     • LAN & Giga bit PCI LAN controller Signals
     Name of LAN Signals   Trace Length   Trace Spacing   Spacing to other sigs    M/B Length   Matching
     ELAN_RXD[2:0]         5 mils         15 mils         15 mils                 4"~12"        +/- 0.5" of ELAN_CLK
     ELAN_TXD[2:0]         5 mils         15 mils         15 mils                 4"~12"        +/- 0.5" of CLK
     ELAN_SYNC             5 mils         15 mils         15 mils                 4"~12"        N/A
     ELAN_CLK              5 mils         15 mils         15 mils                 4"~12"        N/A
     MD1_[3:0]X            7 mils         7 mils          >50 mils for group      within 4"     +/- 50 mil for +/-


          – MD1_[3:0]+/- routing width=7 mils, space=7 mils for
            differential pair. Spacing =50 mils for differential pair
            to differential pair. To other signal > 100 mils ( 300
            mils recommend).
          – Don’t route differential trace and vias under crystals or
            oscillators or clock generator.
          – Avoid routing LAN signal near other high-frequency
            signals.
                                                                                                                  48
                                                                                                                       48
48
                   Layout Training – Guideline 篇

                      ICH5 & LAN Signals(5)
     • LAN & Giga bit PCI LAN controller Signals
      – Avoid routing LAN signal near other high-frequency
        signals.
      – Place the Lan chips more than 1.5” away from any
        board edge and differential signal trace > 50 mil to
        plane split.
      – The differential pair signal of LAN should be Ground
        referenced.




                                                               49
                                                                    49
49
                     Layout Training – Guideline 篇

                      ICH5 Decoupling
     • Caps should placed as close to the ICH4 within 100mils
         – Referenced to PAGE 8 for decoupling cap location.


     • RTC Recommendation
         – Keep the RTC lead lengths ( RTCX1, RTCX2) as short as possible;
           should be < 0.25”.
         – Place Y1, C38, C41, R105, as close to ICH5 as possible.
         – Put GND plane underneath Crystal components.
         – Don’t rout switching signals under the external components.
     • AC ’97 recommendation
         – 5 mils width, 5 mils spacing between traces except AC_BCLK.
         – Routing AC_BCLK with 5 mils width, space=15 mils.
         – Max. trace length between ICH5 to Code = 14”



                                                                             50
                                                                                  50
50
            Layout Training – Guideline 篇

       • Power trace width requirement
     • VCC5_SB net must at least 80mil.
     • VCC3_SB should at least 80mil and should add copper wit
     PCI slot.
     •VCCP for ICH net must be at least 60 mils
     •VTT_DDR Plane for DDR terminator resistor must has cur
     plane at least 100mil.
     •VBAT has current path at least 30mil.
     •USB_STR Power for USB & KB/MS should has current at
     least 150 mils. 60 mils for each USB2.0 (two port).
     •VCC_VID should at least 25 mils with space 10mils.
                                                      51
                                                           51
51
                           Layout Training – Guideline 篇

              • Serial ATA Routing Guide
                              5mils          5mils

                  20mils    SATA_TX# 7 mils SATA_TX 50mils     CLOCK
         SIGNAL                                              HIGHSPEED
                              Signal          Signal

                                      GND



     •    SATA_TX#[1:0]=SATA_TX[1:0]=X
     •    SATA_RX#[1:0]=SATA_RX[1:0]=Y
     •    X=Y ≦ +/-100 mils
     •    The maximum number of via for the trace is 2
     •    The trace length should be < 5”.
     • Serial ATA signal must be Ground reference.

                                                                         52
                                                                              52
52

				
DOCUMENT INFO
Shared By:
Categories:
Tags:
Stats:
views:14
posted:5/21/2013
language:Unknown
pages:52