Docstoc

Silicon based Millimeter Wave Transceiver Circuits for GBPS

Document Sample
Silicon based Millimeter Wave Transceiver Circuits for GBPS Powered By Docstoc
					Silicon-based Millimeter Wave Transceiver Circuits for 60 GHz GBPS Wireless Communications
Rahul Kodkani, & Prof. L. E. Larson
Department of Electrical and Computer Engineering; Jacobs School of Engineering, University of California San Diego, CA 92093

Motivation
Frequency Quadrupler Power Amplifier

60 GHz LNA in IBM 8HP BiCMOS Process
• Two Stage Differential Cascode LNA • Microtstrip lines with M1 ground plane used for matching • Small valued ( ~ 15 fF) fringe capacitors to resonate bondwire inductance • Microstrip line based inductors (slab inductors) used to tune out bond-pad capacitance

30 GHz Two Stage Ring Oscillator
0 180 90 270

Two Stage Ring Oscillator

Low Noise Amplifier

Mixer

Transceiver Building Blocks in PHEMT process* Power Amplifier

Quadrature Generation for Subharmonic Mixers
RC polyphase filters
• amplitude and phase inaccuracies • sensitive to parasitics

• GBPS wireless data rates are achievable in the 59 – 64 GHz Frequency Band • Existing Solutions use expensive hybrid GaAs technology • Can we build these in Silicon? • Can we move from expensive technologies to low cost silicon similar to what cellular phones witnessed?
Low Noise Amplifier

Layout of the 60 GHz LNA

90 degree hybrids
• take up lot of area at 30 GHz

Ring oscillator
• can provide accurate multiple phases

* Source: K. Fujii, M. Adamski, P. Bianco, D. Gunyan, J. Hall, R. Kishimura, C. Lesko, M. Schefer, S. Hessel, H. Morkner, A. Niedzwiecki, “ A 60 GHz MMIC chipset for 1-Gbit/s wireless links”, IEEE MTT-S Digest, pp. 1725-1728, 2002.

Project Goals
Subharmonic Mixer

Simulation Results: Low Noise Amplifier
NF vs. Frequency
S21 v/s Frequency
20 18

VCC

13 12.5 12 11.5

OUTP

INP

INN

OUTN

LPF
IF Amp

I_Out To demodulator

Technology

BPF

LNA

BPF

LPF

Q_Out

To demodulator

S21 (dB)

NF (dB)

ft (GHz) 300400 341 156 156

f max (GHz) 600 238 350 275

Breakdown voltage (V) Low (4-5) Low- Medium Medium Medium

InP HEMT
sin 30 GHz Ring Oscillator PLL cos

InP HBT
5 GHz

Typical simplified Superheterodyne Receiver
From modulator
PA DR

GaAs pHEMT GaAs HBT

Min. Noise Figure (dB) 0.5 @ 20 GHz 3.3 @ 18 GHz 1.5 @ 60 GHz 1.6 @ 18 GHz

16 14 12 10 8 6 4 2 0 55G 56G 57G 58G 59G 60G 61G 62G 63G 64G 65G Frequency (GHz)

11 10.5 10 9.5 9 8.5 8 55G 56G 57G 58G 59G 60G 61G 62G 63G 64G 65G Frequency (Hz)

From V/I Converter

Delay Cell schematic

Layout of the Ring Oscillator

Supply Voltage (V) Phase Noise @ 1 MHz offset (dBc/Hz) Tuning Range (GHz) Current Consumption (per stage in mA) Figure of Merit Chip Area (sq. mm.)

3.3 -83 27-36 18 152 1.3 x 1.3
FOM  PhaseNoise(dBc)  10 log(( f offset f osc ) 2 Pdissm W )

From modulator
sin cos

CMOS (90 nm) SiGe HBT (0.12 um)

170 208

150 250

Very Low Very Low 1.7

0.25 @ 5 GHz 1.33 @ 20 GHz

S21(dB) S11(dB) S22(dB) Noise Figure (dB) Current Consumption (mA) Supply Voltage (V) Chip Area (sq. mm.)

17.5 -13 -6 8.8 20 3 1.2 x 1.2

Comparison of various technologies available
PLL
30 GHz

• Gain is > 16 dB • Noise Figure of 8.8 dB

Typical simplified Homodyne Transmitter

• Design and implementation of integrated low-cost SiGe MMWIC transceiver building blocks for Gbit/s wireless data rates

Performance Summary (post layout simulations)

Performance Summary (post layout simulations)

Performance Summary

60 GHz Low Noise Amplifier
V CC
Transmission Line Inductor
Chip Boundary

60 GHz Subharmonic Mixer
Cfringe
Bondpad Bondwire

Summary and Future Work
Summary • 16 dB S21, 8.8 dB NF, 60 GHz LNA designed and is back from fabrication • 30 GHz Two Stage Ring Oscillator with 83 dBc/Hz phase noise @ 1 MHz offset has been taped out for fabrication Future Work • Integrated Downconverter with Ring Oscillator • Integrated Receiver to receive GBPS data • Power Amplifier with Power Combiner

VCC
Input Matching Network

VCC
Output Matching Network

RFOUT+ VB RFIN+

RFOUTVB RFINRFIN+
Bondwire Bondpad

VB
Cfringe

VB

RF + OUT

Resonance

Input Matching Network

Need For Subharmonic Mixers • Can avoid DC offsets due to LO Self Mixing in Direct Conversion Receivers • LO generation is easier since it is a subharmonic fraction of the RF frequency
IFIF+

Simulation Results (schematic) •Conversion Gain: 13 dB •Noise Figure (SSB): 10.5 dB •Supply Voltage: 3.3V •DC Current Consumption: 7 mA

Differential Cascode LNA

Simplified schematic of the LNA (half)

• Two stages to give enough gain • First stage optimized for noise • Second stage optimized for gain

• Differential Topology for easing grounding requirements •Bondwire inductance resonated out with fringe capacitors • Bondpad capacitance resonated out with line inductors

LO+

Frequency Doubler 2LO+

LOLO90+

Frequency Doubler 2LO-

LO90-

Frequency Doubler 2LOLO90+

LO- Frequency LO+
Doubler 2LO+

RF+

RF-

Schematic of the Subharmonic Mixer


				
DOCUMENT INFO