APLLICTAIONS OF IMPROVED GILBERT MULTIPLIER-2

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					   International Journal of Electronics and Communication Engineering & Technology (IJECET), ISSN
   INTERNATIONAL JOURNAL OF ELECTRONICS AND
   0976 – 6464(Print), ISSN 0976 – 6472(Online) Volume 4, Issue 2, March – April (2013), © IAEME
COMMUNICATION ENGINEERING & TECHNOLOGY (IJECET)
ISSN 0976 – 6464(Print)
ISSN 0976 – 6472(Online)
Volume 4, Issue 2, March – April, 2013, pp. 462-468
                                                                            IJECET
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           APPLICATIONS OF IMPROVED GILBERT MULTIPLIER

                               Komal Mehna and Prof. B. P. Singh
                  FET, Mody Institute of Technology & Science Lakshmangarh,
                                    Sikar (Rajsathan), India



   ABSTRACT

           With the advancement in the field of electronics at an incredible pace, the power
   efficient and high-speed VLSI designs are gaining more popularity and are highly in demand.
   The decrease in battery weight, size and increase in the lifetime are the key factors for
   portable equipments. Most of the reported multipliers have very poor performance and/or
   become non-functional in case of low-voltage, low-power environment. This paper describes
   various applications of analog multiplier such as frequency doubler, modulator, demodulator
   etc. All the simulation work has been done on Tanner EDA tool at 45nm technology.

   Keywords : VLSI, Analog Multiplier, Gilbert Cell, CMOS Technology.

   1.     INTRODUCTION

            The growing demand of data transfer via the wireless communication systems results
   in the fast development of various portable products [1]. The analog multipliers are basic
   building blocks, used in many applications like mixers and modulators in communication
   systems, continuous time signal processing, automatic variable gain amplifiers, adaptive
   filters, and neural networks [2]. The multiplier performs a linear product of continuous
   signals x and y yielding an output z=kxy, where k is a constant of suitable dimension [3]. The
   Gilbert Cell Mixer is very useful building blocks in transceiver design [4]. Gilbert-cell mixers
   are among the popular classes of mixers which are used extensively in wireless transceivers.
   Among the important features of Gilbert-cell mixers are their large bandwidth and high
   conversion gain (CG) [5].




                                                 462
International Journal of Electronics and Communication Engineering & Technology (IJECET), ISSN
0976 – 6464(Print), ISSN 0976 – 6472(Online) Volume 4, Issue 2, March – April (2013), © IAEME

2.      DESCRIPTION OF THE PROPOSED CIRCUIT

        Gilbert cell has two important properties. The first property is that the small-signal
gain of the circuit is a function of its tail current. The second property tells that the two
transistors in a differential pair provide a simple means of streeing the tail current to one of
the two destinations [6], [7]. Existing 12T Gilbert cell multiplier [8] has been modified by
grounding the body terminal of all the nMOS transistors and connecting the body terminal of
transistor MP4 to V DD [9]. The positive and negative terminals of the output voltage ( VOUT ) are
indicating Outp and Outn respectively in the proposed multiplier circuit of Fig. 1. Here VC is
the control voltage.

For the conditions

V DS ≥ V GS − V tn and V GS ≥ V tn

Equation of the drain current in the saturation region for the nMOS is given by

                   kn
            ID =      (VGS − Vtn )2
                    2

All the transistors in Fig. 1 operate in the saturation region. Input signals are applied in the
complementary form i.e.

        V1 = −V2 & VC1 = −VC 2


The input signal being varied and 4 V12 is taken to approximately zero. So the output current
[9]

                         2 2 R DV1VC k n
               I OUT =
                             ROUT
               I OUT ∝ V1VC                                  (1)

               2 2RD kn
Where   k1 =
                 R OUT


Equation (1) indicates that the output current ( IOUT ) is proportional to the product of input
voltages which is the property of the voltage multiplier so it is a voltage multiplier.




                                               463
International Journal of Electronics and Communication Engineering & Technology (IJECET), ISSN
0976 – 6464(Print), ISSN 0976 – 6472(Online) Volume 4, Issue 2, March – April (2013), © IAEME




                                    Fig. 1 Proposed multiplier

3. SIMULATION RESULTS

        In order to verify the circuit operation and characteristics, several experimental
simulations have been carried out at the 45nm technology using Tanner EDA tool. The
transient response of the proposed multiplier is shown in Fig. 2. Here input signals are
sinusoidal with 10mv peak amplitude, frequency of V1 and VC are 500kHZ and 0.1GHZ
respectively and the supply voltage is ± 0.8v. The aspect ratio of all transistors is taken 1. The
proposed multiplier had power consumption and power-delay product less than the existing
12T Gilbert cell based multiplier almost 2 times and 4 times respectively [9].




                       Fig. 2 Transient response of proposed multiplier



                                               464
International Journal of Electronics and Communication Engineering & Technology (IJECET), ISSN
0976 – 6464(Print), ISSN 0976 – 6472(Online) Volume 4, Issue 2, March – April (2013), © IAEME

4.   APPLICATIONS OF PROPOSED MULTIPLIER

4.1 Frequency Doubler
       When a sinusoidal voltage ( A sin ωt ) is applied to the both inputs of the proposed
multiplier, output produced is double frequency of the input signal.

                                       Vo = A 2 sin 2 ωt
                                                A2
                                         Vo =      (1 − cos 2ωt )
                                                2

       Thus the output signal contains the DC component and cosine component of
frequency 2ω , which twice of the input frequency.
For example if the sinusoidal voltage of 50mv amplitude and frequency of 500kHz is given to
the inputs then the output voltage is proportional to ,as shown in Fig. 3. Thus proposed
multiplier can operate as frequency doubler.




                     Fig. 3 Frequency doubler using proposed multiplier

4.2 Modulator
        The growing demand of data transfer via the wireless communication systems results
in the fast development of various portable products [10]. The purpose of a communication
system is to deliver a message signal from an information source in recognizable form to a
user destination, with the source and the user being physically separated from each other [11].
Modulation is the systematic alteration of one waveform, called the carrier, according to the
characteristics of another waveform, the modulating signal or message [12]. A circuit, stage
or piece of hardware that modulates is called a modulator.
    When two sinusoidal voltages of different frequencies (500 kHz and 0.1GHz) are applied
to the inputs of proposed multiplier presented in Fig. 1, the output results in a modulated sine
wave as shown in Fig. 4 (a).



                                              465
International Journal of Electronics and Communication Engineering & Technology (IJECET), ISSN
0976 – 6464(Print), ISSN 0976 – 6472(Online) Volume 4, Issue 2, March – April (2013), © IAEME

    Fig. 4 (b) represents the triangular modulation of sine wave when one input is a sinusoidal
voltage and the other is a triangular voltage of lower frequency, the output is triangular
modulation of sinusoidal voltage. Thus the proposed multiplier circuit can also behave as
modulator.




                Fig. 4(a) Output waveform of modulator for sinusoidal input




                Fig. 4(b) Output waveform of modulator for triangular input

4.3 Demodulator
        To reconstruct the transmitted signal, modulated signal must pass through a reversal
process known as demodulation. A circuit, stage or piece of hardware that demodulates is
called a demodulator. Proposed multiplier presented in Fig.1 can also act as demodulator
after connecting capacitors at the output shown in Fig. 5.


                                             466
International Journal of Electronics and Communication Engineering & Technology (IJECET), ISSN
0976 – 6464(Print), ISSN 0976 – 6472(Online) Volume 4, Issue 2, March – April (2013), © IAEME




                       Fig. 5 Demodulator using proposed multiplier

        Transient response of the proposed multiplier as demodulator is shown in Fig. 6. In
this circuit two capacitor c1 and c2, each of 0.1pf, have been used. Here input signals are
sinusoidal with 50mv peak amplitude, frequency of V1 and VC are 500kHZ and 0.1GHZ
respectively and the supply voltage is ± 0.8v. Where V1 = −V2 & VC1 = −VC 2 .




                          Fig. 6 Output waveform of demodulator


5. CONCLUSION

       Applications of the proposed multiplier have been simulated at the 45nm technology
using Tanner EDA tool. Simulation results demonstrate that the proposed multiplier can act
as frequency doublers when both inputs have the same frequency. It can also be used as
modulator when one input has a higher frequency than other and demodulator.


                                             467
International Journal of Electronics and Communication Engineering & Technology (IJECET), ISSN
0976 – 6464(Print), ISSN 0976 – 6472(Online) Volume 4, Issue 2, March – April (2013), © IAEME

REFERENCES

[1]    Yu-Hsin Chang, Chia-Yang Huang, and Yen-Chung Chiang, “A 24GHz Down-
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[2]    Jacek Jasielski, Stanislaw Kuta, Witold Machowski and Wojciech Kolodziejski, “Four-
       Quadrant CMOS Transconductance Multiplier Operating at Low Voltage and High-
       Speed,” MIXDES 2010, 17th International Conference Mixed Design of Integrated
       Circuits and Systems, June 24-26, 2010, Wroclaw, Poland.
[3]    Om Prakash Kumar, J Michel Suman, and Mrs Flavia Princess “A Novel Four
       Quadrant CMOS Analog Multiplier,” International Conference on Devices, Circuits and
       Systems (ICDCS), pp. 149 – 152, March 15-16, 2012 .
[4]      Ms. Ujwala A. Belorkar, Dr. S.A. Ladhake, Member, and Dr. Sujata N. Kale, “2.45
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[5]      Hooman Rashtian, Amir Hossein Masnadi Shirazi, and Shahriar Mirabbasi
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       Systems (MWSCAS) , pp. 61 – 64, Aug. 5-8, 2012
[6]    B. Gilbert, "A precision four-quadrant multiplier with sub-nanosecond response," IEEE
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[7]    Behzad Razavi, Design of Analog CMOS Integrated Circuits (1st ed. Tata McGraw-
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[8]    Chander Shekhar, “Low Voltage Low Power Gilbert Cell Based Multiplier,”
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[9]    Komal Mehna and B. P. Singh ,“Low Voltage Low Power High Speed Analog
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[10]   Yu-Hsin Chang, Chia-Yang Huang, and Yen-Chung Chiang, “A 24GHz Down-
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       Microwave Integrated Circuits Conference, Oct. 29-30, 2012, pp. 285 – 288.
[11]   Sanjay Sharma, “Communication Systems (analog and digital),” S. K. Kataria & sons,
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[12]   A. Bruce Carlson “Communication Systems- An Introduction to signal and noise in
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[13]   Mohit Kumar, “CMOS Current Multipliers in 0.5µm and 0.35µm Technology”,
       International journal of Electronics and Communication Engineering & Technology
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[14]   Rajinder Tiwari and R K Singh, “An Optimized High Speed Dual Mode CMOS
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       ISSN Print : 0976-6545, ISSN Online: 0976-6553.




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