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CSCE 612 VLSI System Design

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					             CSCE 212
             Chapter 5
The Processor: Datapath and Control




        Instructor: Jason D. Bakos
                              Goal
• Design a CPU that implements the following instructions:
   – lw, sw
   – add, sub, and, or, slt
   – beq, j




                                                       CSCE 212 2
Datapath




           CSCE 212 3
Instruction Fetch Datapaths




                              CSCE 212 4
Register File and ALU




                        CSCE 212 5
BEQ Datapath




               CSCE 212 6
Load, Store, and R-type Datapath




                                   CSCE 212 7
Combined Datapaths




                     CSCE 212 8
                                 ALU Control
• ALU performs function based on 4-bit ALU_operation input
• Add a lookup table that instructs ALU to perform:
     – add (for LW, SW), or
     – subtract (for BEQ), or
     – perform operation as dictated by R-type function code

                                                                              ALU control
Instruction opcode   ALUOp   Instruction   Funct field   Desired ALU action     input
       LW             00                                         add             0010
       SW             00                                         add             0010
       BEQ            01                                      subtract           0110
      R-type          10        add         100000               add             0010
      R-type          10        sub         100010             subract           0110
      R-type          10        and         100100               and             0000
      R-type          10         or         100101               or              0001
      R-type          10         slt        101010         set on less than      0111




                                                                                   CSCE 212 9
MIPS Datapath




                CSCE 212 10
MIPS Datapath with Control




                             CSCE 212 11
MIPS Datapath with Jump




                          CSCE 212 12
                          Single-Cycle
• This is a single-cycle implementation
• Each instruction is executed within one clock cycle
   – Must be set for worst-case delay (LW)


                                        Functional units used
           Instruction   Instruction   Register         Memory   Register
              class         fetch       read      ALU   access    write
             R-type          X            X       X                 X
               LW            X            X       X        X        X
               SW            X            X       X        X
              BEQ            X            X       X
                J            X




                                                                            CSCE 212 13
                Multicycle Implementation
• Break instruction execution into a sequence of steps
   – Adjust cycle time to be long enough to perform one basic operation
       • fetch, register read, ALU, memory access, register write
   – Must add registers to carry computed values from one cycle to next
   – Still can perform independent operations in parallel, i.e.:
       • fetch instruction and compute next PC address
       • read registers and compute branch address
   – Allows us to re-use ALU




                                                                    CSCE 212 14
Multicycle MIPS Implementation




                                 CSCE 212 15
                     Multicycle Control
• Instruction fetch
   – Information available: PC
   – Performed for all instructions
   – RTL:
       • IR <= Memory[PC];
       • PC <= PC + 4;


• Instruction decode and register fetch
   – Information available: PC, instruction
   – Performed for all instructions
   – RTL:
       • A <= Reg[IR[25:21]];
       • B <= Reg[IR[20:16]];
       • ALUOut <= PC + (sign-extend(IR[15:0]) << 2);




                                                        CSCE 212 16
                     Multicycle Control
• Execution, memory address computation, or branch
  completion
   – Information available: PC, instruction, (rs), (rt), (ALUOut)

   – Memory reference:
       • ALUOut <= A + sign-extend(IR[15:0]);


   – Arithmetic-logical instruction (R-type):
       • ALUOut <= A op B;


   – Branch:
       • if (A == B) PC <= ALUOut;


   – Jump:
       • PC <= {PC[31:28], IR[25:0], “00”};



                                                              CSCE 212 17
                     Multicycle Control
• Memory access or R-type completion step
   – Information available: PC, instruction, (rs), (rt), (ALUOut)

   – Load:
       • MDR <= Memory[ALUOut];


   – Store:
       • Memory[ALUOut] <= B;


   – Arithmetic-logical instruction (R-type):
       • Reg[IR[15:11]] <= ALUOut;




                                                              CSCE 212 18
                     Multicycle Control
• Memory read completion step
   – Information available: PC, instruction, (rs), (rt), (ALUOut),
     (MDR)

   – Load:
       • Reg[IR[20:16]] <= MDR;




                                                              CSCE 212 19
Multicycle Control




                     CSCE 212 20
          Adding Datapaths and Control
• How to add these instructions:

   – addi rt, rs, imm

   – bgtz rs, target

   – bgtzal rs, target




                                         CSCE 212 21
                Exceptions and Interrupts
• Events other than branches or jumps that change the
  normal flow of instruction execution
   – Examples:
      •   I/O device request (external, interrupt)
      •   System call (internal, exception)
      •   Arithmetic overflow (internal, exception)
      •   Invalid instruction (internal, exception)
      •   Hardware malfunction (internal or external, exception or interrupt)




                                                                                CSCE 212 22
                 Interrupts and Exceptions

• What to do?
   – Execute code in response
     to event (handler)
       • Save PC (EPC reg,)
       • Record cause (Cause reg.)
       • Set new PC (4)
   – Return from handler
       • Restore PC
       • Enable e/i (shift Status reg.)


• Determining type of
  exception
   – Use vectored exceptions
       • Infer type from address
   – Use polled exceptions
       • Use Cause register
       • This is what MIPS does




                                             CSCE 212 23
             Example Implementation
• Example:
  – Use polled approach
  – All exceptions and interrupts jump to single handler at address
    8000 0180
  – The cause is recorded in the cause register
  – The address of affected instruction is stored in EPC




                                                           CSCE 212 24
Example Implementation




                         CSCE 212 25
Example Implementation




                         CSCE 212 26

				
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