Optics and the CMOS Interconnection Problem A Systems and by yurtgc548

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									Wiring Layer Assignments with
   Consistent Stage Delays

       Andrew B. Kahng (UCLA)
  Dirk Stroobandt (Ghent University)

      Supported by Cadence Design Systems, Inc. and

       the MARCO Gigascale Silicon Research Center




  April 9, 2000            SLIP 2000                  --1--
                        Outline


•   Introduction: wiring layer assignment
•   Problem and models
•   Optimization objective function
•   Our layer assignment method
•   Discussion and results
•   Conclusion




        April 9, 2000      SLIP 2000    --2--
                        Introduction


• DSM design routing tools have to account for
   –   delay constraints
   –   yield
   –   power
   –   …
• Conventional technique:
   – router assigns wires to layers
   – wire sizing, repeater insertion/sizing applied
• More interesting approach:
   – wire sizing etc. used by router to assign wires


        April 9, 2000        SLIP 2000          --3--
   Our Layer Assignment Concept

• Search for optimal layer for a wire with
   – optimal wire size, number and size of repeaters for
     each wire
   – meeting consistent stage delay constraints
   – taking total repeater area constraint into account
   – accounting for impact of vias
• A priori estimation techniques make it useful
  for application both before / after placement
• Potential applications
   – improving CAD layout tools
   – studying effects of technological parameters
   – optimizing fabrication process


       April 9, 2000       SLIP 2000          --4--
               Problem and Models

       Find the optimal assignment of wires to
       wiring layers subject to delay constraints
         and total repeater area constraints


• Optimization objective: # of layers needed
• Degrees of freedom (for each wire)
   –   choice of layer parameters
   –   wire width
   –   number of repeaters
   –   size of the repeaters



        April 9, 2000       SLIP 2000     --5--
 Layer Assignment Assumptions

– layer pairs form tiers (H and V)            V
                                              H}
                                                 tier
– tiers grouped in tier types
                                              H}
                                              V
                                                 tier
  (equal parameters)
– (even) number of layers/type to be determined
– wires are routed on 1 tier
– inputs to the method:
   • number of tier types and their layer parameters
   • order (bottom-to-top) user-defined
– output:
   • optimal number of layers / tier type
   • layer to which wires are assigned

     April 9, 2000         SLIP 2000         --6--
           Delay Constraint Model

• Sakurai’s [IEEE TED, 1993] delay equation
  – depends on wire length/width through wire R, C
• Delay can be reduced by
  – increasing wire width (for fixed length and layer)
     • consider uniform wire sizing (no tapering)
     • continuous wire sizing (no discrete set of widths)
  – optimal gate sizing
  – repeater insertion and sizing
     • repeaters at equal distances
     • number of repeaters even
• Trade-off between delay and area
       April 9, 2000        SLIP 2000          --7--
                  Via Impact Model

• Sai-Halasz [1995]: every layer blocks 15%
• Newer models:                          V
                                                       H   } tier
  Chong [1999], Chen [1999]                            V
                                                       H   } tier
   – terminal vias and turn vias
   – each wire uses 2 via stacks
   – number of terminal vias defined by layer
     assignment model
• Via impact factor
                   N v Av                     N v Av
  Chong:       f             Chen:     f 
                     A                          A
       April 9, 2000        SLIP 2000         --8--
          Wire Length Distribution

• All wires classified according to their length
• Wire length distribution needed
  – measuring distances between placed gates
  – applying a priori wirelength estimation




       April 9, 2000   SLIP 2000     --9--
   Cost Function = Number of Layers

• Non-integer by considering area needed/tier
          Nt                Nt
                                   Ai
  C   Li  
         i 1                      A
                      A = available area/layer
                            i 1
• Area parts: wiring area + area “lost” to vias
                                                   Tier type i
 Aw,i   l (k )(W (k )  Si )                                    l(2)
        kIi                                       Wire 2                 W(2)
                                                   Wire 1
          Li
                                                                          Si
                             N v (k ) Av ,i (k )   Wire 0
 Avia,i   A      
          j 1     k J j               A

          April 9, 2000                     SLIP 2000            --10--
               Cost Function (cont.)
                        W

    Tier type 2
                                    Wmin

    Tier type 1

    Tier type 0



• Via area assumptions
  – square area with side = minimal wire width/layer
  – line of vias for wider wires
  – via sizes scale with minimal wire widths for
    lower layers

        April 9, 2000   SLIP 2000          --11--
              Cost Function (cont.)

• Number of vias
  – each repeater adds 2 vias on layer of tier below
  – each repeater adds 1 via on layer of own tier
  – no repeaters: as if 1 repeater

                                           Gate
                                           Repeater
                                           Wire on type 2
                                           Tier type 1
                                           Tier type 2




       April 9, 2000    SLIP 2000       --12--
  Via Impact Limits Number of Layers

• Via impact factor must be < 1
• For maximum number of layers (e.g., 10)
                                  Lw,i
                       fi  1 
                                  Lm ax
  – 8 layers for wires: f<0.2
  – number of wires < 300,000
    (250nm, 10M trans., logic area 54mm2, 4mm wire
    pitch on tier, all wires minimum width, no
    repeaters)

       April 9, 2000               SLIP 2000   --13--
                  Layer Assignment method

  • 2 phases: optimize, then round to integers
  • Phase 1: Calculate minimal Calculate cost DC for
                                  delay Tmin.                 moving wire to other tier
                                                              while optimizing W, Nr.
                    N
  Ttarget=Tmin.                   Tmin<Ttarget?
                                                                   Sort costs in
                                         Y                       increasing order.
                              Calculate minimal                 Repeat for all wires.
                             repeater area Amin.
                                                                                        N Solution
                                                                     DCmin < 0?
  Alimit=Amin           N                                                                  found!
                                  Amin<Alimit?
Solution found!                                                            Y
                                         Y                       Move K wires with
                            Create initial solution               smallest DC<0.
                              on “fattest” tier.                     Repeat.

                  April 9, 2000                   SLIP 2000               --14--
                        A Typical Example

                                                  Tier type 2
                                                  Tier type 1
                                                  Tier type 0

                      Delay (ps)                                       Wire width (mm)




Number of repeaters            0   20   2          4      0     2      4




                                            Wirelength (mm)

              April 9, 2000                 SLIP 2000               --15--
                    Target Delay Influence

                                       Tier type 2
                                       Tier type 1
                                       Tier type 0



Delay (ps)                     Wire width (mm)




             Wirelength (mm)                     Wirelength (mm)



               April 9, 2000    SLIP 2000              --16--
         Uniform Versus Non-uniform Stacks
Tier 2
Tier 1
Tier 0
                                 Number of layers per tier type
    10                                                                              10
     9                                                                              9
                  8.0251
     8                                                                              8
                                                7.1053
     7                                                                     6.3134   7
     6                                                                              6
     5                       Total                                                  5
     4                                                                              4
     3                                                                              3
     2                                                                              2
     1                                                                              1
     0                                                                              0

 • Uniform still 3 numbers: via impact = Li fi
             April 9, 2000                 SLIP 2000              --17--
         Optimal Layer Stack Monotonic?
Tier 2
Tier 1
Tier 0
                             Number of layers per tier type
    20                                                                            20
    18                     19.3665                                                18
    16                                                                            16
    14                                                                            14
    12                                                                            12
    10                                                                            10
     8                                                 7.1285            7.0002   8
     6
               5.4426                                                             6
     4                                                                            4
     2                                                                            2
     0                                                                            0

 • Results depend on delay constraint
           April 9, 2000               SLIP 2000                --18--
                         Conclusions
•   Layer assignment is becoming more critical
•   Our proposal: use stage delay constraints
•   Current work: 2-D length-delay distribution
•   Wire/repeater sizing + via impact + area limit
•   Via impact severely limits number of wires
•   Interesting conclusions:
    – maximum wire width on tier type not dependent on delay
      constraint
    – monotonic non-uniform layer stack (fat-wires-on-top)
      better than uniform
    – non-monotonic worse for tight delay constraints but
      “non-fat” tier on top can be beneficial
• Useful to search for optimal layer stack parameters
• Find threshold values to ensure optimality of layer
  stack and make layer assignment more “trivial”


         April 9, 2000        SLIP 2000          --19--

								
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