Future Challenge in Microelectronic Packaging

Packaging Research Thrusts @ INTEL ATD PR Site Visit st April 21st, 2004 Ravi Mahajan, Johanna Swan Assembly Technology Development Technology Manufacturing Group Chandler, Arizona 1 Agenda Research at INTEL Research for Performance Power Delivery Strategies Cooling Strategies I/O & Signaling Die-Package & On-Package Interconnect Research for Density Die Stacking Package Stacking Package Footprint Summary Note : Research concepts discussed today are under evaluation and will not all necessarily make it to product implementation 2 Research @ INTEL Influence through participation Mentor, Manage, Generate IP Select Develop Integrate Discovery Science Universities National Labs NSF DOE Long range research Universities MARCO Universities SRC Intel funded Directed Research Internal R&D Path-finding Models, Advanced Prototypes Development Product Product Implementation Implementation 3-8 yrs out Breakthrough 8-15 yrs out science for next 40 years Product Implementation 3-5 yrs out 1 • Our strategy : Influence & leverage research to meet future challenges 3 Power Delivery Strategies 4 Performance Performance Power Delivery Second Droop Second Droop Voltage Response to a Current Step Voltage Response to a Current Step (Droop = L di/dt) (Droop = L di/dt) Third Droop Third Droop First Droop First Droop 1st droop challenge: • Cut inductance to pkg caps - determines 1st droop magnitude 3st droop challenge: • Faster VR response time - determines 3rd droop magnitude - minimizes bulk decoupling required - can create thermal side-effect • Increase on-pkg capacitance - to meet board decoupling time constant under increasing load • Cut VR/board/skt/pkg resistance - manage IR loss with higher current 5 Package Capacitor Technology 2-Terminal Capacitors Reducing 1st droop Impact Future Technology Interdigitated Capacitors Array Capacitors Current Technology Thin Film Capacitors Different capacitor technologies under investigation to increase on package capacitance & reduce inductance 6 Reducing capacitor inductance Power Delivery Technology LGAs to reduce path resistance Reducing 3rd droop Impact PGA Die µPGA Future Technology Concepts Current Technology Voltage Regulation closer to the die 7 Reducing Path Resistance High Performance Capacitors integrated closer to the die Cooling Strategies 8 Performance Performance Thermals 250 0.8 0.8 0.7 0.7 0.6 0.6 0.5 0.5 0.4 0.4 0.3 0.3 0.2 0.2 0.1 0.1 1 1 4 4 77 Cooling Capability [W] 200 150 STIM 100 PTIM Bare die 50 S17 S17 S9 S9 10 10 13 13 16 16 19 19 0 2000 2002 2004 2008 2012 00 S1 S1 Die-Pkg Interface Challenge: • Increase heat spreading - Smooth hot spots so commodity system solutions are viable System Integration Challenge: • Low resistance interfaces - Die substrate metallization (Si) - Low bulk resistance materials 9 Thermal Interface Material (TIM) Improved Thermal Interface Materials Improved Thermal Interface Materials (TIMs) (TIMs) Spreader On-Die Temperature Distribution w/ Polymer TIM Significant TIM engineering to enhance heat ducting to spreader On-Die Temperature Distribution w/ Solder TIM On-Die Power Distribution Intel® Pentium® 4 Processor 10 Improved Heat Spreading Improved Heat Spreading Silicon Temperature Package Temperature Ambient Temperature Packaging smoothes out Hot Spots Temperature Gradient Example : Intel® Itanium® Processor Example : Intel® Pentium® 4 Processor Integrated heat pipe Integrated Heat Spreader 11 Fluid Based Cooling Fluid Based Cooling Concept Single phase or 2-phase fluid based cooling w/ flow thru on-die (or package) micro-channels Micro-Fluidics under investigation @ a number of leading schools as the next generation cooling technology We have active collaborations to coresearch this technology Research also being supported at STRL THERMOFLUIDIC/ELECTRICAL I/O MODULE Photonic I/O Photonic I/O Electrical Electrical Connections Connections RF Integrated MEMS Integrated MEMS Sensing Sensing Fluidic I/O Fluidic I/O Mixed Signal Chip Fluidic Fluidic Cooling Cooling 12 Solid State Refrigeration Solid State Refrigeration Concept TEC refrigerators integrated on die/package for spot cooling Micro coolers monolithically grown or bonded on Si Tremendous recent breakthroughs in solid state refrigeration We are actively engaged w/ leading universities to investigate applicability to semi-conductor cooling 13 I/O & Signaling 14 Signaling Research Bandwidth (MB/sec), Core Freq (MHz) Pentium® II Processor Pentium® III Processor Pentium® 4 Processor 64bit DDR333 128bit DDR400 80286 Pentium® Processor 80386 8088 80486 100000 10000 1000 100 10 I/F, DRAM BW RDRAM BW Core Freq differential, point-to-point, advanced signaling, advanced package 8bit DRAM 16bit DRAM 1 1980 1985 32bit DRAM 1990 32bit DRAM 64bit DRAM EDO 64bit SDRAM PC66/100 64bit SDRAM100/133 1995 2000 2005 2010 We are engaged with some of the best schools in the area of EM and I/O performance simulations We have developed some significant measurement capability to validate our models 15 Die-Package and On-Package Interconnect 16 Performance Performance Flipchip Interconnect Die Substrate Challenge: • Reduce stress transmitted to die to enable lower-k ILD - Bump/solder structure, matching substrate CTE Fab + Assembly tradeoffs - Avoid transferring problem to BGA balls Assembly + Board tradeoffs 17 Compliant Interconnects (CI) die solder Compliant interconnect structure substrate Coiled CI Straight CI Shunted CI Coiled CI spring on a polymer dome CI Spring Polymer Dome CI Spring Polymer Dome Compliant Interconnects is a potential future technology to increase interconnect density and reduce package induced stresses on the die 18 On-Package Interconnects 250 200 Bump Pitch um 150 100 Package Traces 50 180 nm 0 130nm 90nm On-going focus to improve die-package and package interconnect feature sizes to enable Moore’s law scaling 19 Agenda Performance Density (performance/mm3) Die Stacking (Z) Package Stacking ( X/Y) Package Footprint (X/Y) 20 100% 80% 60% 40% 20% 0% Die Stacking Package Budget Density Density % Total Thickness (1.4mm Max) Die Budget 1 2 3 4 5 6 7 8 9 Number of Stacked Die More performance /mm^3 More performance /mm^3 Die, package interactions dictate collaboration 21 Die Stacking Z Challenge: Reduce die thickness Density Density Thinning reduces Z but introduces assembly challenges: wire bonding on cantilevered die/ shorts UltraThin (2 mils) Thin (4.5 mils) Standard Thinning (7 mils) Full Thickness (29 mils) 22 Die Stacking Z Challenge: Eliminate spacers Density Density Spacers utilized for wb between same size die Eliminated with through silicon via interconnect Die 2 Top Gap DA Spacer DA thickness Spacer thickness DA thickness Die- Die Gap Bottom Gap DA Nominal Loop Height Die 1 DA Through Silicon Via STRL Program Fab B/E coupled with assy. 23 Die Stacking Z Challenge: Eliminate spacer Density Density Flip chip on bottom die and then wirebond Flip chip die on flex substrates Die are thin enough that they will float and mis-align during reflow which leads to alternative chip attach investigations Flex Substrate 24 Die Stacking Z Challenge: Thin substrates Density Density Flex substrates offer a z height advantage over standard BT. 3 Mil Die on BT Substrate 1mm 3 Mil Die on Flex Sub .8mm SPACER In addition, flex substrates enable package to package stacking in development today. 25 XY Challenge: Package Stacking Density Density Number of Intra-connects within the MCP Package stacking enables smaller xy footprint with the multiple substrate layers available for routing. SP-CSP- Research Surface Layer FSCSP BGA to cu interconnect Single sided bus to top Four sided bus to top 26 Package Stacking XY Challenge: Number of balls and pitch on the package Density Density .5 mm pitch 14x14 mm +50 um SM Reg .4 mm Pitch 12x12mm + 20 um SM Reg Normal develop process requires a keep out of 2 x the solder mask registration for areas around the metal pads. Laser defining of soldermask allows for reduced keep out areas around the metal pads. Pad diameter plus 20um is possible 27 Summary Comprehensive strategy in place to influence and leverage external research to solve major issues in packaging technology Facilitate technology transfer and use research results for packaging development Our technologists complement university and consortia researchers in technology transfer As a result INTEL is well positioned to address the many challenges to packaging technology 28 Back-up 29 Power delivery Research We are actively engaged in university research to improve voltage regulation e.g. improving dynamic compensation Vin VR power stage Regular VR Controller Conventional VR CU P V t age ol M t or oni Vin B - di r ect i onal i A l l ar y uxi C onver t er D ic ynam C r ol l er ont H gh speed dynam c cur r ent com i i pensat or 30 A Holistic “Systems” View Silicon Packages Heat Sinks Architectural improvements in Silicon design Enhance Heat Spreading (Package) Increase Power handling (Heatsinks) Expand System Thermal Envelopes Systems Facilities 31 Improved Heatsinking Improved Heatsinking Temp – Package Temp – Silicon Case (Tc) (Tj) Temp – Ambient (Ta) Temperature Gradient Heatsink Duct out heat Heat sink Strategy : Increase cooling capability – Material, geometry optimization – Focus on cost effective manufacturing 32 Improved Heat-sinking Improved Heat-sinking Extruded Technologies Heatsink Roadmap Heat Sink Thermal Performance Technology Evolution - Desktop and ServersSpiral Fan-sink Fansinks nce,, ma nce r rfforma ive e r o tit ive gh p e mpe tit led Hiigh p o mpe H t c o s enab led Cos t c giies enab Cos lo g e h n o lo c teSkive no tech Crimped Fin ‘01 ‘98 ‘00 ’02 and beyond ‘96 TIME 33 Enabling Holistic System Enabling Holistic System Thermal Designs Thermal Designs Focus Area 3 : Improve Fans & Heat Exchangers Focus Area 1 : Improve TIMs & Attach Methods Air Inlet Ambient Air Exhaust Heat Pipe TIM Focus Area 2 : Improve Heat-pipe performance 34 Spatial Resolution: Leading the Industry in OptoMechanics contour. Contour interval (nm): Displacement Measurement Resolution: Smallest in-plane displacement per fringe Smallest distance between two separate points can be resolved by an imaging system. Spatial resolution (µm) Customized SRC Funding (INTEL) 5µm Moiré Interferometry Customized SRC Funding (INTEL) 417nm Moiré Interferometry 3µm Microscopic Moiré Interferometry (MMI) 1.5µm Enhanced MMI 0.5µm Nano-scale Moiré Interferometry 208nm Microscopic Moiré Interferometry (MMI) 35nm Enhanced MMI 5nm Nano-scale Moiré Interferometry Highly successful partnership with universities has led to a 2 generation improvement in Moiré tools These tools are used routinely in our process & design development 35 FEA Model Validation with High Resolution Moiré Interferometry FEA Model Moiré Image Die : Low Strain Package Substrate Die-Attach Layer : High Strain High Resolution Moiré + Finite Element Analysis (FEA) used for DieAttach Material Selection in organic packages 36 New TIM Tester State of the art tester developed entirely in house High level of TIM interface control Higher power capability for improved resolution (0.01ºC/W) Heating block Load Alignment Mechanism Rmat Thot int − Tcold int = ′′ qave q”ave Sample Cooling block Thotint Tcoldint 0.5” dia. copper rods 37