HIGH PERFORMANCE DOMINO FULL ADDER DESIGN UNDER DIFFERENT BODY BIASED TECHNOLOGY by iaemedu

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									  International Journal of Advanced Research in OF ADVANCED (IJARET), ISSN 0976 –
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             ENGINEERING AND TECHNOLOGY (IJARET)
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Volume 4, Issue 2 March – April 2013, pp. 125-133
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            HIGH PERFORMANCE DOMINO FULLADDER DESIGN UNDER
                    DIFFERENT BODY BIASED TECHNOLOGY


                 Saradindu Panda1, Supriyo Srimani2, Prof. Bansibadan Maji3,
                            Prof. Asish Kumar Mukhopadhyay4
      1,2
          Dept. of Electronics and Communication Engineering, Narula Institute of Technology,
                                            Kolkata, India
      3
        Professor & Head, Dept. of Electronics and Communication Engineering, NIT, Durgapur,
                                                 India
                     4
                       Director, BITM, Santiniketan, Birbhum, West Bengal, India.




  ABSTRACT

          With the advancement in semiconductor technology, chip densities are increasing, so
  the power consumption in VLSI circuits has become a major problem of consideration. More
  power consumption reduces the battery life of the devices and increases packaging cost. In
  modern digital VLSI circuits Dynamic domino logic circuits are widely used. Static CMOS
  logic circuits are very low speed circuit. Dynamic CMOS circuits, featuring a high speed
  operation are used in high performance VLSI designs. In this work, domino Full Adder is
  designed with various body biasing circuit. The proposed design is tested in 150nm and
  45nm. Moreover Noise, Power and Delay have been compared also.

  Keywords: Conventional body bias, CMOS, Domino logic, Dynamic power.

 I.         INTRODUCTION

          A CMOS circuit can have two kinds of Power consumption- dynamic or static.
  Dynamic power dissipation takes place due to switching activities and charging and
  discharging of load capacitances. Static power consumption is another type of power
  dissipation in CMOS circuits [1]. The power consumed in high performance Microprocessor
  has increased to levels that impose a fundamental limitation to increasing performance and

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functionality [3]. Domino logic circuit techniques are extensively applied in high
performance microprocessors due to the superior speed and area characteristics of compared
to static CMOS circuits [4]. Domino logic circuits, however, are highly sensitive to noise as
compared to static gates. Now a day’s enhancing the circuit speed without considering the
power is not acceptable in circuit design. So it has become necessity of the VLSI circuits to
reduce the dynamic as well as the static power consumption. Leakage currents with sub-
threshold source-to-drain leakage, reverse bias junction band-to-band tunneling, gate oxide
tunneling, and other current drawn continuously from the power supply cause static power
dissipation. Dynamic switching power is quadratically reduced by lowering the supply
voltage. Reduction of supply voltage after a certain limit affects the performance of the
circuit, to maintain circuit performance of the circuit it is necessary to decrease the threshold
voltage as well, but it leads to leakage power dissipation.
         At reduced threshold voltage, however sub threshold leakage current increase
exponentially. So, lowering leakage currents are, therefore, highly desirable. Domino logic
circuit techniques compared to static CMOS circuits are extensively applied in high
performance microprocessors due to the speed and area characteristics of domino CMOS
circuits. It has become a major challenge to design error free operation of domino logic
circuits as on-chip noise becomes more with technology scaling and increasing operating
frequencies.
      A portable system must be designed for low power consumption. Supply voltage
scaling is an effective way to reduce power consumption. However, threshold voltage cannot
be scaled down with the same rate. So, sub threshold operation is a better option for low
power applications. The sub threshold logic operates with the power supply Vdd less than the
threshold voltage Vth of the transistor.
       In this paper domino FULL ADDER with different substrate biasing techniques are
designed and their performances are compared. Power consumption, delay, noise are used as
parameters in sub threshold region. The designs are tested and compared at 150 nm and 45
nm technologies to prove the technology independence of the proposed design.

A. Full Adder

A and B are the adder inputs, Ci is the carry input, S is the sum output, and Co is the carry
output. The Boolean expressions for S and Co are given by the following equations:

       s = A ⊕ B ⊕ Ci = ABCi + ABCi + ABCi + ABCi                  C 0 = AB + BC i + AC i

Some logic manipulations can help to reduce the transistor count. The following is an
example of such a reorganized equation set:

                C 0 = AB + BC i + AC i              S = ABCi + C 0 ( A + B + C i )

Fig:1 shows the circuit diagram of a CMOS Full Adder Circuit and Fig: 2 show the output
wave form of the Full Adder Circuit:
:


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       Fig. 1 Circuit diagram of a Full Adder Circuit        Fig. 2 Output wave form of a Full Adder
                                                            Circuit

 II.          CIRCUIT TECHNIQUES

          Dynamic domino logic circuits are widely used in modern VLSI circuits. These
   dynamic circuits are often favored in high performance designs because of the speed
   advantage offered over static CMOS logic. The main drawbacks of dynamic logic are a lack
   of design automation, increased power Consumption. As supply voltage is reduced, delay
   increases, unless threshold voltage VT is also decreased. The voltage difference between the
   source and the substrate VBS also affects the width of the depletion layer and due to changes in
   the charge in depletion layer voltage across the oxide also get changed. Therefore the
   expression for the threshold voltage is given by:
                                                         2ε s qN a (2φ F + VSB )
                                    VT = VFB + 2φ F +
                                                                 COX

           The threshold difference due to an applied source-substrate voltage can therefore be
   expressed by:
                                                  (
                                     ∆VT = γ (2φ F + VSB ) − 2φ F        )
          Where, γ is the body effect parameter given by

                          2ε s qN a
                    γ =
                           C OX

III.          STANDARD DOMINO NAND GATE

          A standard domino NAND gate is as shown in Figure 3. A standard Domino NAND
   gate consists of one p-type transistor and an n-type dynamic logic block. During pre-charge
   phase the output node of the dynamic CMOS stage is pre-charged to high logic level. During
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  evaluation phase, the output node of the dynamic CMOS stage is either discharged to a low
  level or it remains high, means that, the output node may be selectively discharged through
  the n-type logic block depending upon whether there is a path exist to the GND or not. It
  depends upon the inputs of the NMOS logic block. If a path to ground is not formed during
  the evaluation phase, means there is no conducting path exist to the ground, we get the high
  logic level at the output. If inputs to the n-type logic blocks are such that it makes a
  conducting path to the ground, output will be low.




                            Fig. 3 Circuit Diagram of a Domino NAND gate.


IV.      PROPOSED BODY BIASED FULL ADDER

         In order to enhance the performance of the circuit, various body biasing techniques
  are used.
  The substrate of the MOS transistors is connected in six different ways. Six body biasing
  schemes for the evaluation networks are shown in figure 4.
      1. The substrate of NMOS is connected to clock and the substrate of PMOS is connected
         to supply voltage VDD (SB1).
      2. The substrate of NMOS and PMOS is connected to clock (SB2).
      3. The substrate of NMOS is connected to supply voltage VDD and the substrate of
         PMOS is connected to Ground (SB3).
      4. The substrate of NMOS is connected to supply voltage VDD and the substrate of
         PMOS is connected to clock (SB4).
      5. The substrate of NMOS and PMOS both connected to supply voltage VDD (SB5).
      6. The substrate of NMOS is connected to its source terminal and the substrate of PMOS
         is connected to clock (SB6).



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6480(Print), ISSN 0976 – 6499(Online) Volume 4, Issue 2, March – April (2013), © IAEME




a.                                                  b.




c.                                            d.




e.                                             f.

                        Fig. 4 (a)SB1, (b)SB2, (c)SB3, (d)SB4, (e)SB5, (f)SB6.

       For 45nm: NMOS: W=0.135u L=0.045u AS=AD0.030375p PS=PD=0.72u
                 PMOS: W=0.27u L=0.045u AS=AD=0.06075p PS=PD=0.99u
       For 150nm: NMOS: W=.45u L=.15u AS=AD=.3375p PS=PD=2.4u
                  PMOS: W=.9u L=.15u AS=AD=.675p PS=PD=3.3u
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V.       SIMULATION RESULT

       The designs are simulated using 150nm and 45nm technology. The supply voltage in
 150 nm is 0.4 V and 0.2 V for 45 nm are used. Power consumption, delay, Noise is measured.




     Fig. 5 Output wave form of a Full Adder     Fig. 6 Output wave form of a Full Adder in
            Circuit 150nm technology                     Circuit in 45nm technology




       Fig. 7 Power Consumption at different          Fig. 8 Power Consumption at different
           bias in 150nm technology                           bias in 45nm technology




      Fig. 9 Delay at different bias in 150nm         Fig. 10 Delay at different bias in 45nm
                    technology                                     technology

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    Fig. 11 Output Noise at different bias in         Fig. 12 Output Noise at different bias in
             150nm technology                                    45nm technology

Table 1: Comparison of Noise, Power and Delay of Full Adder Circuits under Different Bias
                           and Different Scaling Technology

                     Bias        I         II         III     IV       V        VI
                      Noise
                                330       340         370     300     350      350
                      (µV)
                      Power
             150nm




                                7.2       6.1         3.1     7.1     3.52     0.44
                      (nW)
                      Delay
                                12.3      2.3         5.8     12       6.8     8.77
                      (pSec)
                      Noise
                                2.49     2.47         2.52   2.46      2.5     2.5
                      (µV)
                      Power
             90nm




                               0.936     1.31         1.81   1.71     1.75     0.25
                      (pW)
                      Delay
                                1.26     1.29         2.4      1       2.3     7.2
                      (pSec)

SB6 biasing, in which the substrate of NMOS is connected to its source terminal and the
substrate of PMOS is connected to clock condition, shows minimum power consumption,
delay. At supply voltage of 0.2V, SB6 biasing condition again shows minimum value of
power consumption. Similar results are obtained in 150 nm technology at supply voltage of
0.4V confirming that the SB6 biasing is the best biasing for domino Full Adder design. The
power consumption by the gate is least at various supply voltages, when the SB6 biasing is
used. The SB2 biased gate shows sudden decrease in delay at supply voltage. The noise is
almost similar in all cases in 45nm as well as 150nm technology. In case of 150 nm
technology the operating frequency is 1GHz but for 45nm technology the operating
frequency is 1000MHz. Higher frequency cannot be used in 45nm technology, because due to
small length collision increase between the carriers so the noise increases. The power
consumption among t various biasing by the gate SB6 biasing is less than the other biasing
schemes.
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   International Journal of Advanced Research in Engineering and Technology (IJARET), ISSN 0976 –
   6480(Print), ISSN 0976 – 6499(Online) Volume 4, Issue 2, March – April (2013), © IAEME

VI.       CONCLUSION

           Domino logic circuit techniques compared to static CMOS circuits are extensively
   applied in high performance microprocessors due to the speed and area characteristics of
   domino CMOS circuits. Comparison of body bias methods using delay, power and noise
   indicates ultra-low voltage domino circuits to be realized. Minimum energy in the sub
   threshold region then depends not only on supply voltage but also on the substrate bias
   voltage.
           Simulation analysis reveals that the Full Adder design using SB6 biasing scheme is an
   energy efficient design.

VII.      ACKNOWLEDGEMENTS

         The authors would like to thank Prof. (Dr.) M.R.Kanjilal and Faculty Members,
   Department of Electronics and Communication Engineering, Narula Institute of Technology,
   WBUT, for many insightful discussions.

   REFERENCES

   Journal Papers

   [1]    Pushpa Raikwal V. Neema, and S. Katiyal, “LOW POWER WITH IMPROVED
   NOISE MARGIN FOR DOMINO CMOS NAND GATE”, Proceedings of the International
   Journal Of Computational Engineering Research / ISSN: 2250–3005.
   [2]    H. Mangalam and K. Gunavathi, “Domino Logic Circuit with Reduced Leakage and
   Improved Noise Margin”,International Journal of Applied Engineering Research ISSN 0973-
   4562 Volume 2, Number 4 (2007), pp. 585–593.
   [3]    Aswathy G Nair and Gopakumar M G, “CS-CMOS: A Low-Noise Logic Family for
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   &Technology (IJECET), Volume 4, Issue 2, 2013, pp. 180 - 190, ISSN Print: 0976- 6464,
   ISSN Online: 0976 –6472.
   [4]    P.Sreenivasulu, Krishnna veni, Dr. K.Srinivasa Rao and Dr.A.VinayaBabu. “Low
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   Proceedings Papers

   [5]    A. Alvandpour, P. Larsson-Edefors, and C. Svensson, “A Leakage Tolerant Multi-
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   [6]    V. Kursun and E. G. Friedman, “Low Swing Dual Threshold Voltage Domino Logic”,
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BIOGRAPHY

Saradindu Panda,             He received M.Tech from Jadavpur University in 2007 in VLSI
Design and Microelectronics Technology. He is pursuing his PhD at NIT, Durgapur, West
Bengal, India. Presently, he is involved in design and management of low-power and high
speed integrated circuits with Solid State Devices in Nano Regime. He is now faculty in ECE
Department at Narula Instutute of Technology, Kolkata, India. He has more than 15
publications in different International and National Journals and Conference Proceedings.

Supriyo Srimani,         He is pursuing B.Tech in ECE, Narula Instutute of Technology,
Kolkata, India. His research interest in the area of VLSI Low Power Design, Image
Processing, Signal Processing.

Prof. (Dr.) Bansibadan Maji, He is now a senior Professor of ECE Department in
NIT, Durgapur, West Bengal, India. He is now Head of The Department of ECE at NIT. His
main research area on Microwave, Antenna, VLSI Design and Low power Device and
Circuits. He has more than 56 publications in different International and National Journals
and Conference Proceedings.

Prof. (Dr.) A. K. Mukhopadhyay, He received M.Tech from IIT, Kharagpur,
and Ph.D(Engg) from Jadavpur University, India. Currently, he is the Director of BITM,
Santiniketan, Birbhum, West Bengal, India. He was the Principal of BCET, Durgapur.
Previously he served as the Dean (Academic) and Head of Department of ECE, Dr. B. C. Roy
Engineering College, Durgapur. He also worked at Narula Institute of Technology, Kolkata,
College of Engineering & Management, Kolaghat, NERIST, Itanagar and IIT, Kharagpur.
His current area of research includes Wireless and Mobile Networks and Overlay-based
heterogeneous networks. He has 48 publications mostly in international journal and
conference proceedings. He is a Life Fellow of the Institution of Engineers (I), Member,
IEEE, Member, IEEE ComSoc, Global Member, ISOC; Sr. Life Member, CSI; Life Member,
ISTE, IETE, SSI etc.




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