ROD_VMEADD_02jul10.xlsx

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					                                                     ROD VME Mapping gen
                                                          Version 1.0
                                                         04 June 2010

 VMEADD      31 30 29 28 27 26 25 24 23 22 21   20 19 18 17 16 15 14 13 12 11 10 9          8   7    6   5   4   3   2   1   0


LOCAL/BUSY           GEOGRAPH. ADD                                                 0    0   0   0   INTERNAL ADDRESS              00 ->7F
   BOOT              GEOGRAPH. ADD                                                 0    0   0   1   INTERNAL ADDRESS              80 -> FF
    TTC              GEOGRAPH. ADD                                                 0    0   1   0   INTERNAL ADDRESS             100 ->17F
    IRQ              GEOGRAPH. ADD                                                 0    0   1   1   INTERNAL ADDRESS             180 ->1FF
    PU1              GEOGRAPH. ADD                                                 0    1   0   0                                200 ->27F
    PU2              GEOGRAPH. ADD                                                 0    1   0   1                                280 ->2FF
                                                                                                    INTERNAL ADDRESS
    PU3              GEOGRAPH. ADD                                                 0    1   1   0                                300 ->37F
    PU4              GEOGRAPH. ADD                                                 0    1   1   1                                380 ->3FF
    OC1              GEOGRAPH. ADD                                                 1    0   0   0                                400 ->47F
    OC2              GEOGRAPH. ADD                                                 1    0   0   1                                480 ->4FF
                                                                                                    INTERNAL ADDRESS
    OC3              GEOGRAPH. ADD                                                 1    0   1   0                                500 ->57F
    OC4              GEOGRAPH. ADD                                                 1    0   1   1                                580 ->5FF
  STAG1              GEOGRAPH. ADD                                                 1    1   0   0                                600 ->67F
  STAG2              GEOGRAPH. ADD                                                 1    1   0   1                                680 ->6FF
                                                                                                    INTERNAL ADDRESS
  STAG3              GEOGRAPH. ADD                                                 1    1   1   0                                700 ->77F
  STAG4              GEOGRAPH. ADD                                                 1    1   1   1                                780 ->7FF

 VMEADD      31 30 29 28 27 26 25 24 23 22 21   20 19 18 17 16 15 14 13 12 11 10 9          8   7    6   5   4   3   2   1   0




                                            968800e7-d4b0-4528-ad9c-e7edf480c276.xlsx
                                                                      ROD VME Mapping registers
                                                                             Version 1.1
                                                                            05 July 2010




      A        B               E          G                           H                   I                                       J                           K        L   M         N
1                                                   ROD REGISTERS
2            GEOGRAPHICAL ADDRESS A(31:24) ) + AREA ADDRESS ( 4 bits A(10:7) ) + INTERNAL ADDRESS( 5 bits A(6:2) )
3         INTERNAL BIN      VME Hex      R/W    FUNCTION                                BITS                                VMEDATA                               init value

4            A(6:2)          A(23:0)
5
6                             LOCAL Register (A10:7) = 0000
 7           00000             0         R/W    base address register                    31:0
 8           00001             4          W     reset general                                                            sent to all chips
 9           00010             8          R     status                                    9     data_bus externe au chip vme
10                                                                                        8     quick answer
11                                                                                        4     busy vme bloque busy initialisation
12                                                                                       3:0    pu-ready
13           00011             C          R     board identificator                      7:0    switch hard on board
14           00100             10        R/W    force busy/Jtag                           0     1 busy forced to 1 ( default during initialisation)
15                                                                                        1     1 data bus extern chip VME( vmeconfig)
16                                                                                        2     1 quick answer 2clock( vmeconfig)
17                                                                                        3     1 quick answer 4clock( vmeconfig)
18                                                                                        4     0= Jtag by connector 1 Jtag by Vme
19
20           00101             14        R/W    mask pu OC boot                          3:0    1=mask pu not present for boot bit3 = pu4
21                                                                                       7:4    1=mask OC not present for boot bit3 = pu4
22           00110             18        R/W    Jtag                                      0     TDI
23                                                                                        1     TMS
24                                        W                                               2     TRSTn
25                                        R                                               2     TDO
26
27           01111             3C               version
28
29
30                           BUSY Registers    (A10:7) = 0000
31           10001             44         W     reset and control                                                                                                          0    pu1_busy1
32                                                                                         8    write duration busy to fifo                                      1xx       4    pu1_busy2
33                                                                                        4     reset timing                                                      1x       5    pu2_busy2
34                                                                                         3    reset interval wr fifo counter                                     8       6    pu3_busy2
35                                                                                         1    reset busy duration                                                2
36                                                                                         0    reset fifo                                                         1
37           10010             48         R     status                                    25    busy_active (idem..)                                         2xxxxxx
38                                                                                        24    busy_pu (idem …)                                             1xxxxxx
39                                                                                      23:16   mask busy( idem..)                                           FFxxxx
40                                                                                      14:13   fifo            FF 4xxx        EF 2xxx
41                                                                                         9    enable busy(idem ..)                                             2xx
42                                                                                         8    busy out                                                         1xx
43                                                                                       7:0    busy in                                                          FF
44           10011             4C        R/W    miscellaneous                           23:16   mask busy                                                     FFxxxx       16   pu1_busy1
45                                                                                         9    enable busy                                                      2xx       18   pu3_busy1
46                                                                                         1      1 mode normal                                                        0   19   pu4_busy1
47                                                                                         1      0 mode manual (read fifo by VME authorized)                              20   pu1_busy2
48                                                                                         0     busy source: 1 = PU, 0 = VME                                          0   21   pu2_busy2
49           10100             50        R/W    interval wr fifo                         31:0   write to fifo each (div_clock * value)                                 1   22   pu3_busy2
50           10110             58        R/W    div clock                                7:0    busy count each (100 nS + 25nS*( n -1))                                1
51           11000             60         R     read fifo                               19:18   full fifo 8xxxx / empty fifo4xxxx before reading fifo
52                                                                                      17:16   full fifo 2xxxx/ empty fifo1xxxx after reading fifo
53                                                                                       15:0
54           10111             5C         R     read duration busy                       15:0
55           11010             68         W     send busy                                15:8   send busy                                                      FFxx
56
57
58                        4 PUs Broadcast Access    (A10:7) = 0001
59                             80                                                               base address for accessing all 4 Pus in broadcast.
                                                                                                 For details of addresses check document
60                                                                                              https://edms.cern.ch/document/598713/3.1
61
62                          BOOT PU Registers (A10:7) = 0001
63        00000 =>11011     00 => 6C            boot PU                                         Maybe doesn't exist anymore

64        11100=>11111      70 => FC            boot OC                                         Maybe doesn't exist anymore
65
66                            TTC Registers (A10:7) = 0010
67           00000            100         R     dummy
68           00001            104        R/W    ctrl                                      8     ev_cnt_res_cnt_reset
69                                                                                       7:5    pulses bit 7=TTC_reset, bit 6=clear status ,bit 5=flush
70                                                                                        4     L1A mode double pulse
71                                                                                        3     clk-sel 00 local, 1= ttcrx                                             1
72                                                                                       2:0    bit 0= VME mode, bit 1=local mode, bit 2=TTC mode                      4
73           00010            108         W     BCID register                            11:0
74           00011            10C         W     EVID register                            31:0
75           00100            110         W     ttype register                           7:0
76           00101            114         R     Status register                         25:24   25 TTCclock present 24 TTRX working
77                                              DL_ERR                                  23:16   non double L1A count in double_l1a mode
78                                              DB_ERR                                   15:8   bouble error strobe count
79                                              SIN_ERR                                  7:0    single error strobe count
80
81
82                            IRQ Registers (A10:7) = 00011
83           00001            184         W     reset                                    14:0reset pending and request IRQ by VME
84           00010            188         R     status1                                  14:0state of input IRQ (cf list) before mask                     FEXX XXXX
85                                                                                      23:17state of REAL output IRQ after enable                          FE XXXX
86           00011            18C         R     status2                                  14:0state of interrupt request not sent                          FEXX XXXX
87                                                                                      28:17state of interrupt request to be sent                          FE XXXX
88           00100            190        R/W    mask/enable                               15 irq selector: 0= irq from vme 1= irq from board                FE XXXX
89                                                                                       14:0mask irqinput                                                     3FFF
90           00101            194        R/W    mapping 1 ouput IRQ                      7:1 1 output IRQ
91                                                                                       10:81 output coded
92                                                                                           102=IRQ1,204=IRQ2, 308=IRQ3, 410=IRQ4
93                                                                                           520=IRQ5, 640=IRQ6
94            00110           198         W     send interrupt by vme                   14:0 simul les IRQ vers la sortie
95            10000           1C0               INPUT IRQ STATUS ID                     7:0 pu1_irq1(0) defaut 1                                                            0   pu1_irq1
96            10004           1C4                                                            pu1_irq2(1) defaut 2                                                           1   pu1_irq2
97            10010           1C8                                                            pu2_irq1(2) defaut 3                                                           2   pu2_irq1
98            10011          1CC                                                             pu2_irq2(3) defaut 4                                                           3   pu2_irq2
99            10100           1D0                                                            pu3_irq1(4) defaut 5                                                           4   pu3_irq1
100           10101           1D4                                                            pu3_irq2(5) defaut 6                                                           5   pu3_irq2
101           10110           1D8                                                            pu4_irq1(6) defaut 7                                                           6   pu4_irq1
102           10111          1DC                                                             pu4_irq2(7) defaut 8                                                           7   pu4_irq2
103           11000           1E0                                                            oc1_irq(8) defaut 9                                                            8   oc1_irq
104           11001           1E4                                                            oc2_irq (9) defaut 10 A                                                        9   oc2_irq
105           11010           1E8                                                            oc3_irq (10) defaut 11 B                                                      10   oc3_irq
106           11011          1EC                                                             oc4_irq(11) defaut 12 C                                                       11   oc4_irq
107           11100           1F0                                                            irq_temp(12) defaut 13 D                                                      12   temp_irq
108       INTERNAL BIN      VME Hex      R/W    FUNCTION                                BITS                                                                      init value




                                                           968800e7-d4b0-4528-ad9c-e7edf480c276.xlsx
                                                                       ROD VME Mapping registers
                                                                              Version 1.1
                                                                             05 July 2010




      A        B                E             G                        H                     I                                    J                            K          L   M        N
109       INTERNAL BIN       VME Hex        R/W   FUNCTION                               BITS                                                                       init value
110          11101             1F4                                                                 irq_busy_direct ON(13) defaut 14 E                                         13 busy_on_irq
111                                                                                                irq_busy_direct Off(13) defaut 14 E                                        14 busy_off_irq
112
113
114                             PU1-4 (A10:7) = 0100 ->0111
115                    PU1 Base Address 200 Offset DSP1 +0, DSP2 +40
116                    PU2 Base Address 280 Offset DSP1 +0, DSP2 +40
117                    PU3 Base Address 300 Offset DSP1 +0, DSP2 +40
118                    PU4 Base Address 380 Offset DSP1 +0, DSP2 +40
119                             +0      R/W       Test register
120                             +4      R/W       control 1 register
121                             +8      R/W       HPI register
122                             +C      R         Status 1 register
123                            +10      W         Broadcast HPI register (both DSP)
124                            +14      W         serial data to McBSP2
125                            +18      R         Serial data from McBSP2
126                            +1C      W         InFPGA1 configuration register (16 LSB)
127                            +20      W         InFPGA1 programmation register (8 MSB)
128                            +24      R         InFPGA1 status register
129                            +28      W         Broadcast InFPGA programmation register (both InFPGA)
130                            +2C      R         OutFPGA version register
131                            +30      R/W       DSP1 running counter (x200 default value ie 12800 ns- 40 MHz clk)
132                            +34      R/W       HPI timeout length (12LSB) default value x280 ie 16us
133
134
135            OUTPUT CONTROLER Registers (A10:7) = 1000 -> 1011
136                        OC1 Base Address 400
137                        OC2 Base Address 480
138                        OC3 Base Address 500
139                        OC4 Base Address 580
140          00000             +00          R/W   dummy register                            31:0
141          00001             +04           W    reset
142          00010             +08           R    status                                   26  end Of event flag 1= eOe not found
143                                                                                        25  link_fail
144                                                                                        24  memory complete
145                                                                                        23  memory empty
146                                                                                        22  data available 1= memory can be read, generate IRQ
147                                                                                       21:0 memory size, write pointer address
148          00100             +10          R/W   config                                   28  xfer all 1= all data transfered
149                                                                                        27  enable test link 1= link in test mode
150                                                                                      26: 24data taking mode, enable spy, enable Slink
151                                                                                            1x0 = data to Sdram, 0x0= data storage stopped in Sdram
152                                                                                            111 = next event to Slink and Sdram
153                                                                                            011= enable Vme event read from Sdram
154                                                                                      21:20 in_out_n, staging mode
155                                                                                            11= fifo2 to previous OC, 01= fifo2 to next OC
156                                                                                      17:16 mask fifo2, mask fifo1
157                                                                                       13:0 bank max 1, bank max 0 , row max ( 11:0) only for Sdram
158                                                                                            when reached the OC stops at the end of event
159          00110             +18          R     Sdram register                               read the Sdram
160          11111             +7C          W     version
161
162
163                      STAGING Registers (A10:7) = 1100 -> 1111
164                            Staging1 Base Address 600
165                            Staging2 Base Address 680
166                            Staging3 Base Address 700
167                            Staging4 Base Address 780
168         led_high                                                                               sans feb alumée/ avec feb ( 1 ou 2) count
169          led_low                                                                               sans feb emit / avec feb ( 1 ou 2) count
170           00000            +00          R/W   dummy 32 bits register
171           00001            +04           W    commande                                 22      reset memoire reset auto glink 1 et 2                      4xxxxx
172                                                                                        21      reset memoire link locked 1 et 2                           2xxxxx
173                                                                                        20      reset mem error glink feb ( error or link not ready)       1xxxxx
174                                                                                        19      rst mem fifo input                                          8xxxx
175                                                                                        18      rst min _max temp                                           4xxxx
176                                                                                      17:16     rst count_feb2, feb1 error                                  3xxxx
177                                                                                       5:4      lock_link 2,1                                                 3X
178                                                                                       3:2      reset link2s, link1s                                           C
179                                                                                       1:0      reset link2, link1                                              3
180          00010             +08            R   status                                 31:30     feb2 cav, feb1 cav
181                                                                                      29:28     feb2 dav, feb1 dav
182                                                                                      27:24     mem_lock2, mem_ lock1, mem_rst2, mem-rst1                  Fxxxxxx
183                                                                                      23:20     fifo stag flag23 :full2, 22 full1,21 empty2, 20 empty1      Fxxxxx
184                                                                                      19:18     18 mem fifo2 empty 19 mem fifo2 full                         Cxxxx
185                                                                                      17:16     16 mem fifo1 empty 17 mem fifo1 full                         3xxxx
186                                                                                       15:8     si injector bit8= mem_error_feb2 else count_feb2_error        FFxx
187                                                                                       7:0      si injector bit0= mem_error_feb1 else count_feb1_error          FF
188          00100             +10          R/W   configuration register                   9:0     nb mots/event                                                  3FF
189                                                                                      31:16     nb de events                                             FFFFxxxx
190          00101             +14          R/W   config2 register                         28      1 reset Glink automatic 0 pas de reset automatic          1xxxxxxx
191                                                                                      27:16     delay entre events                                        FFFxxxx
192                                                                                        15      0 databit17 bit toggle 1 databit17=1 for dummy PU
193                                                                                        14      1 input non stoppées si Glink non locké                         4xxx
194                                                                                        13      1 infinite loop                                                 2xxx
195                                                                                        12      1 block emision avec busy from PU                               1xxx
196                                                                                      11:10     bit 11=1 led= error glink bit 10=1 led= erreur gen opt           8xx
197                                                                                                00 led high= light low= start_emit
198                                                                                          8     1 feb_input to PU 0 stagingRam to PU                            1xx
199                                                                                          6     1'                                                               4x
200                                               stag2puOK                                  5      en mode staging 1 out sur own PU, 0 sur autre                   2x
201                                               staging                                    4     1 mode staging 0 pas en staging                                  1x
202                                               sel_out                                    3     0=> datafeb2s=0, 1=>datafeb2s=data_ram(31-16)                     8
203                                                                                          2     0=> datafeb2=0, 1=>datafeb2=data_ram(31-16)                       4
204                                                                                          1     0=> datafeb1s=0, 1=>datafeb1s=data_ram(15-0)                      2
205                                                                                          0     0=> datafeb1=0, 1=>datafeb1=data_ram(15-0)                        1
206          00111             +1C          R/W   adresse de départ                         9:0
207          00110             +18          R/W   data dans Ram
208          01000             +20           W    start emission                             0
209          01001             +24          R/W   link_condfig                              5:4    div1,div0
210                                                                                         3,2    feb_eqn 2,1
211                                                                                         1:0    feb_flag 2,1
212
213        10000-10111       +40=>+5C         R   temp                                      23:0 23:16 max, 15:8 min, 7:0 actuel
214           11111             +7C               version
215       INTERNAL BIN       VME Hex        R/W   FUNCTION                               BITS                                                                       init value




                                                            968800e7-d4b0-4528-ad9c-e7edf480c276.xlsx
                                                ROD VME Mapping CRCSR
                                                      Version 1.0
                                                     04 June 2010

     A     B            E         G                  H                    I                             J                             K           L

                        MOTHER BOARD CR/CSR REGISTERS
1
2 DEC INTERNAL BIN INTERNAL Hex   R/W           FONCTION                BITS                       VMEDATA                                    S
 3         ROM Registers    AM=2F, A24, A24-A20=GEADD
 4                    03(00)      R              checksum                       =CB + board ID et Revision ID
 5                    07(04)      R                                             =00                                                00000000   00000000
 6                    0B(08)      R            lenght of ROM                    =10                                                00010000   00010000
 7                    0F(0C)      R                                             =00                                                00000000   00010000
 8                    13(10)      R         Rom data Access                     =84 ID D32 or D16 or D08                           10000100   10010100
 9                    17(14)      R         CSR data Access                     =84 ID D32 or D16 or D08                           10000100   00011000
10                    1B(18)      R     CR/CSR Space Specification              =2                                                 00000010   00011010
11                    1F(1C)      R               ???                           = 43 ( ASCII C)                                    01000011   01011101
12                    23(20)      R               ???                           = 52 ( ASCII R)                                    01010010   10101111
13                    27(24)      R                                             =08                                                00001000   10110111
14                    2B(28)      R           manufacturer ID                   =0                                                 00000000   10110111
15                    2F(2C)      R                                             =30                                                00110000   11100111
16                    33(30)      R
17                    37(34)      R                                             ???
                                                  Board ID
18                    3B(38)      R
19                    3F(3C)      R
20                    43(40)      R
21                    47(44)      R                                             ???
                                                Revision ID
22                    4B(48)      R
23                    4F(4C)      R
24                    53(50)      R                                             =00 ecrit juste apres le serial number             00000000   11100111
25                    57(54)      R          Pointer to a string                =10                                                00010000   11110111
26                    5B(58)      R                                             =07                                                01110000   01100111
27                    CB(C8)      R                                             =00 8 bits ecrits juste apres la ROM               00000000   01100111
28                    CF(CC)      R     Offset to Begin Serial Number           =10                                                00010000   01110111
29                    D3(D0)      R                                             =03                                                00000011   01111010
30                    D7(D4)      R                                             =00                                                00000000   01111010
31                    DB(D8)      R      Offset to End Serial Number            =10                                                00010000   10001010
32                    DF(DC)      R                                             =03                                                00000011   10001101
33                    E3(E0)      R           slave characteristic              =06                                                00000110   10010011
34                    F7(F4)      R                Interrupter                  =7E depend des cartes               01111110
35                   103(100)     R       function 0 Acces DAWPR                =84                                                10000100   00010111
36                   123(120)     R        funct 0 AM Code 8 bytes              =000000000000AA00                                  00000000   00010111
37                      ..        R                                             AM = 09,0B, 0D, 0F                                 00000000   00010111
38                   13B(138)                                                                                                      10101010   11000001
39                   13F(13C)     R                                                                                                00000000   11000001
40                   623(620)     R                                     31:24    =FF depend carte               11111111
41                   627(624)     R                                     23:16    =FF                           11111111
                                            funct 0 ADEM 4 bytes
42                   62B(628)     R                                     15:8     =F8                           11111000
43                   62F(62C)     R                                      7:0     =00
44                                                                              checsum pour carte ROD           01110100          11001011 00110101
45         CSR Registers    AM=2F, A24, A24-A20=GEADD
46                 7FFFF(7FFFC)   R/W       BAR( base addresse)          7:3    geadd
47                 7FFFB(7FFF8)   R/W          Bit set register           4     enable module---- all others not used in module
48                 7FFF7(7FFF4)   R/W         Bit clear register          4     disable module---- all others not used in module
49                 7FF63(7FF60)   R/W               ader0               31:24
50                 7FF67(7FF64)   R/W               ader1               23:16   28:24 par defaut adresse geographique
                                                                                                                            funct 0 ADER 4bytes
51                 7FF6B(7FF68)   R/W               ader2               15:8    permet de changer l'adresse de base
52                 7FF6F(7FF6C)   R/W               ader3                7:0




                                        968800e7-d4b0-4528-ad9c-e7edf480c276.xlsx
                                                   ROD VME Mapping pu_uni
                                                         Version 1.0
                                                        04 June 2010


     A     B            E         G                H                 I                                    J                  K        L   M
                         MOTHER BOARD REGISTERS
1                         GEOGRAPHICAL ADDRESS + A(10:7) + INTERNAL ADDRESS( 5 bits)
2 DEC INTERNAL BIN INTERNAL Hex   R/W         FONCTION             BITS                             VMEDATA                       init value
3
 4        PU Transparent Registers (A10:7) = 0100 -> 0111                  pu-nul6
 5   0     0           200        W/R   dummy 32 bits register
 6   1     1           204         W           reset                5:4    5:fifo_int 4:fifo-ext
 7                                                                   8     reset count event
 8                                                                  3:2    reset feb2s, feb1s
 9                                                                  1:0    reset feb2, feb1
10   2     10          208        R              status             5:0    paf2, paf1, full2, full1, empty2, empty1 EXT
11                                                                 11:8     full2, full1,empty2 ,empty1 INT
12                                                                  16     config(0)
13   4    100          210        W/R    configuration register    31:16   pulse length                                   FFFFxxxx
14                                                                   0      1: fifo1-2< = feb1-2, 0: fifo1-2 <= feb1-2S
15                                                                   1     1: led_ini: 40 MHz, 80MHz WENN fifo
16                                                                   1     0 : errors et link ready
17   5    101          214         R          read fifo_int
18   6    110          218        W/R   pulse and set/reset busy   9:8     set reset9: irq2 8: irq1                         3xx
19                                                                 5:4     set reset 5: busy2 4: busy1                      3x
20                                                                 1:0     pulse busy 1 busy2, 0: busy1                      3
21   1f   11111        27C        W/R           version
22




                                         968800e7-d4b0-4528-ad9c-e7edf480c276.xlsx
                                          ROD VME Mapping ttc
                                              Version 1.0
                                             04 June 2010
            A                  B                 C                D              E           F
1
2    Registres     Taille                 Signal Enable    Adresses VME
3    dummy_reg                     none   ?                00000
4    ctrl_reg                        10   ena_ctrl_reg     00001
5    bcid_reg                        12   ena_bcid_reg     00010
6    evid_reg                        32   ena_evid_reg     00011
7    ttyp_reg                         8   ena_ttyp_reg     00100
8    stat_reg                        32   ena_stat_reg     00101
9    Ttype Subaddr                    8   ?                00110
10   EvtCntResCnt                     8   ?                00111           not implemented
11   Version                         32   ?                01111
12
13
14
15   Bits ctrl_reg       Mode         1 valide le mode
16                   0   VME
17                   1   LOCAL
18                   2   TTC (PHYSIQUE)
19                   3   CLK_SEL
20                   4   L1A_MODE
21                   5   FL_BUFF
22                   6   STAT_CLEAR
23                   7   TTC_RESET
24                   8   EV_CNT_RES_CNT_RESET
25                   9   EV_CNT_RESET
26
27
28   To get more information on these registers and bits check TTC FPGA documentation
29   https://edms.cern.ch/document/873119/2




                             968800e7-d4b0-4528-ad9c-e7edf480c276.xlsx
                                                 ROD VME Mapping deserialiseur
                                                         Version 1.0
                                                       04 June 2010
     A       B         E         G                 H                 I                       J                        K

1
                   MINIVME FOR DESERIALISEUR
2 DEC        BIN   PROG Hex     R/W FONCTION                      BITS                  VMEDATA                   vme->board
3                             BASE ADDRESS
4        0             0        W/R register
5
6                      LOCAL Register 200000
7        0 00000     200000      R   status
8        1 00001     200004      W   reset hard pour board          1    recepteur                                   0001
9                                                                   0    emetteur
10                         RECEPTEUR           80000
11       0 00000     80000       R   status                         3:0 empty fifo                                   0000
12                                                                  7:4 full fifo
13                                                                 11:8 paf fifo                                     0001
                                                                        3 si on n'a pas écrit dans config, C si
14                                                                15:12 écrit
15       1 00001     80004      W reset                             1:0 bit 0 =fifo, bit 1 count-mots
16       2 00010     80008      W/R configuration register          3:0 1 fifo parmi 4                               0010
17                                                                 31:4 bits W/R pour verification
18       3 00011     8000C      W/R link register                    3  spare0, set reset                            0010
19                                                                   2  lparity set reset
20                                                                   1  ldown set reset
21                                                                   0  lff pulse 2 clocks
22       4 00100     80010       R   lit le nb de mot recepteur    9:0 envoie 1 parmi fifo                           0100
23       5 00101     80014       R   read fifo                          envoie 1 parmi fifo                          0101
24       F 01111     8003C       R   version




                                          968800e7-d4b0-4528-ad9c-e7edf480c276.xlsx

				
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