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                          ENTITY mux IS                                   in0          mux
                            GENERIC ( tplh: TIME:= 3NS;
                                          tphl: TIME:= 5NS );             in1                output
                            PORT ( in0, in1, sel: IN BIT;
                                                                          sel   tplh         tphl
                                   output: OUT BIT );
                          END mux;

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                                                             ENTITY test_bench IS
                                                             END test_bench;




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                   ARCHITECTURE identifier OF component_name IS
                     [ declaration ]
                   BEGIN
                     specification of the functionality of the
                     component in terms of its input lines and as
                     influenced by physical and other parameters
                   END [identifier] ;



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                       ARCHITECTURE data_flow OF mux IS
                       BEGIN
                        output <= ((NOT sel) AND in0) OR (sel AND in1);
                       END data_flow;



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                                                      mux
                          in0                         i1
                                                                   g1
                                                                        int1
                                                            and2
                                                                   o1                     g3
                          in1                  int0   i2                       i1              output
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                                                      i1                       i2
                           sel     i1         g0
                                                            and2
                                        inv                             int2
                                              o1      i2           o1




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               ARCHITECTURE struct OF mux IS
                 COMPONENT inv
                 PORT( i1: IN BIT; o1: OUT BIT );
                 END COMPONENT;
                 COMPONENT and2
                 PORT( i1, i2: IN BIT; o1: OUT BIT );
                 END COMPONENT;
                 COMPONENT or2
                 PORT( i1, i2: IN BIT; o1: OUT BIT );
               END COMPONENT;
                 SIGNAL int0, int1, int2: BIT;
               BEGIN
                 g0: inv
                 PORT MAP (i1 => sel, o1 => int0);
                 g1: and2
                 PORT MAP (i1 => in0, i2 => int0, o1 => int1);
                 g2: and2
                 PORT MAP (i1 => sel, i2 => in1, o1 => int2);
                 g3: or2
                 PORT MAP (i1 => int1, i2 => int2, o1 => output);
               END struct;


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                               ARCHITECTURE behav OF mux IS
                               BEGIN
                                 PROCESS (in0, in1, sel)
                                 BEGIN
                                    IF (sel = '0') THEN
                                        output <= in0;
                                    ELSE
                                        output <= in1;
                                    END IF;
                                 END PROCESS;
                               END behav;


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                                            PACKAGE example IS
                                                 TYPE cd IS ('C', 'D');
                                                 CONSTANT pi : REAL := 3.14159;
                                                 COMPONENT ttl_74163 IS
                                                    PORT ( a, b: IN BIT;
                                                             c: OUT BIT );
                                                 END COMPONENT;
                                                 SIGNAL global_clock: BIT;
                                            END example;


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                                             PACKAGE BODY package_name IS
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                         FUNCTION mean (a, b, c : REAL) RETURN REAL;
                   END pack_funct;
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                         FUNCTION mean (a, b, c : REAL) RETURN REAL IS
                         BEGIN
                           RETURN (a + b + c)/3.0;
                         END mean;
                   END pack_funct;



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                     CONFIGURATION identifier OF entity_name IS
                          configuration_declarative_part
                     END;



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                         ENTITY and2 IS
                              GENERIC (ttl_delay : TIME := 3NS);
                              PORT ( in1, in2 : IN BIT;
                                     output : OUT BIT );
                         END and2;

                         ARCHITECTURE dataflow OF and2 IS
                         BEGIN
                              output <= in1 AND in2 AFTER ttl_delay;
                         END dataflow;

                         ARCHITECTURE behave OF and2 IS
                         BEGIN
                              PROCESS (in1, in2)
                              BEGIN
                                IF (in1 = '1' AND in2 = '1') THEN
                                    output <= '1' AFTER ttl_delay;
                                ELSE
                                output <= '0';
                              END PROCESS;
                         END behave;



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                                       CONFIGURATION dataflow_and OF and2 IS
                                            FOR dataflow
                                            END FOR;
                                       END dataflow_and;


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           ARCHITECTURE examp_config OF decode IS
             COMPONENT inv PORT (in1: IN BIT; o1: OUT BIT);
             END COMPONENT;
             COMPONENT and3 PORT (in1, in2, in3 : BIT; o1: OUT BIT);
             END COMPONENT;
             :
           END examp_config;


           CONFIGURATION decode_llcon OF decode IS
             FOR structural
                FOR i1: inv USE CONFIGURATION WORK.invcon;
                END FOR;
                FOR i2: inv USE CONFIGURATION WORK.invcon;
                END FOR;
                FOR ALL: and3 USE CONFIGURATION WORK.and3con;
                END FOR;
             END FOR;
           END decode_llcon;


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           CONFIGURATION decode_eacon OF decode IS
             FOR structural
                FOR i1: inv USE ENTITY WORK.inv (behave);
                END FOR;
                FOR OTHERS: inv USE ENTITY WORK.inv (dataflow);
                END FOR;
                FOR a1: and3 USE ENTITY WORK.and3 (behave);
                END FOR;
                FOR OTHERS: and3 USE ENTITY WORK.and3 (dataflow);
                END FOR;
             END FOR;
           END decode_eacon;


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   entity1                                                     1_entity
   ENTITY1                                                     _and_gate
   a_long_legal_identifier_with_underscores                    and
   CasE_InsEnsITIve                                            ampersand&




                                                      
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ėÇ „Èŗo˜¦µÁšnµš¸É¤¸„µ¦nŠ°„‡ªµ¤­´¤¡´œ›r¦³®ªnµŠ˜´ªÁ°Š„´®œnª¥®¨´„ ªnµÁž}œ DUFKLWHFWXUH
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                            ARCHITECTURE behavioral OF and_gate IS
                               °
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                            ARCHITECTURE dataflow OF and_gate IS



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                                    LIBRARY ttl_lib

                                    ENTITY "and_gate"
                                    ARCHITECTURE "behave"

                                    ENTITY "or_gate"
                                    ARCHITECTURE "behave"



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          „µ¦š¸É‹³šÎµÄ®o…o°¤¼¨š¸É¦¦‹»°¥¼nĜSDFNDJH­µ¤µ¦™™¼„œÎµ°°„ŞčoĜ­nªœ…°ŠHQWLW\¨³
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                                                               LIBRARY IEEE;
                                                               --
                                                               ENTITY test IS
                                                               END test;



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67'¨³:25.­µ¤µ¦™œÎµ¤µ°oµŠ°·ŠÅ—oץŤn˜o°ŠÄo‡Îµ­´ÉŠ/,%5$5<Ä®¤n


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       LIBRARY IEEE;                -- make library symbolic name "IEEE" visible
       --
       USE ieee.std_logic_1164.and;     -- make the "and" FUNCTION in package
                                        -- std_logic_1164 in library ieee visible
       --
       ENTITY test IS
       end test;



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                             ¦¼žš¸ „µ¦Äo‡µ­´Š/,%5$5<¨³86(


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                                     LIBRARY ieee;
                                     USE ieee.std_logic_1164.ALL;

                                     ENTITY test IS
                                     end test;



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                  ¦¼žš¸ „µ¦„ε®œ—čoš„°¥nµŠ£µ¥Ä˜oSDFNDJHº°67$1'$5'


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—·‹·˜°¨°¥nµŠŠnµ¥Ç ×¥°¥¼nĜ¦¼ž…°Š¦¼žÂš¸ÉÁ…¸¥œ—oª¥£µ¬µ 9+'/ Á¡ºÉ°Áž¦¸¥Áš¸¥Ä®oÁ®Èœ„´
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                                        aoi1
                                        aoi2

                                        aoi3
                                                                      aoi1_output
                                        aoi4

                                        aoi5
                                        aoi6




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         „µ¦°°„Ã—¥ª·›¸„µ¦Á…¸¥œ¦¼žÂ PRGHOLQJ —oª¥£µ¬µ 9+'/ Á¦·É¤˜oœ—oª¥„µ¦šÎµÄ®o˜¼o
Á„ȝ°»ž„¦–r ­Îµ®¦´¦³9+'/®¤µ¥™¹ŠOLEUDU\ºÉ°­´¨´„¬–rLHHHÄ®o YLVLEOH¨³nŠ°„™¹Š
¨·Êœ´„­Îµ®¦´¦³9+'/®¤µ¥™¹ŠSDFNDJHºÉ°VWGBORJLFBš¸ÉÁ„ȝ°»ž„¦–r FRPSRQHQW
š´ÊŠ­°ŠÃ—¥»—‡Îµ­´ÉŠ/,%5$5<¨³86(˜µ¤š¸É­—ŠÄœ¦¼žš¸É


                                            LIBRARY IEEE;
                                            USE ieee.std_logic_1164.ALL;
                                            ENTITY and2 IS
                                               PORT ( in1, in2: IN std_logic;
                                                        output: OUT std_logic );
                                            END and2;

                                            LIBRARY ieee;
                                            USE ieee.std_logic_1164.ALL;
                                            ENTITY nor3 IS
                                               PORT ( in1, in2, in3: IN std_logic;
                                                        output: OUT std_logic );
                                            END nor3;




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˜o°Š¦¦¥µ¥˜n°¤µÅ—o„n¡§˜·„¦¦¤…°ŠªŠ‹¦®¦º°‡ªµ¤­´¤¡´œ›r¦³®ªnµŠ­´µ–RXWSXW¨³LQSXW
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                           ARCHITECTURE and2_behave OF and2 IS
                           BEGIN
                             output <= in1 AND in2 AFTER 3 NS;
                           END and2_behave;

                           ARCHITECTURE nor3_behave OF nor3 IS
                           BEGIN
                             output <= NOT(in1 OR(in2 OR in3)) AFTER 4 NS;
                           END nor3_behave;



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                       LIBRARY ieee;
                       USE ieee.std_logic_1164.ALL;

                       ENTITY aoi IS
                       PORT ( aoi1, aoi2, aoi3, aoi4, aoi5, aoi6: IN std_logic;
                                aoi_output: OUT std_logic );
                       END aoi;



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               ARCHITECTURE struct OF aoi IS
                 COMPONENT and2
                    PORT ( in1, in2: IN std_logic;
                            output: OUT std_logic );
                 END COMPONENT;
                 COMPONENT nor3
                    PORT ( in1, in2, in3: IN std_logic;
                            output: OUT std_logic );
                 END COMPONENT;
                 SIGNAL internal1, internal2, internal3: std_logic;
               BEGIN
                 u1:and2 PORT MAP (aoi1, aoi2, internal1);
                 u2:and2 PORT MAP (aoi3, aoi4, internal2);
                 u3:and2 PORT MAP (aoi5, aoi6, internal3);
                 u4:nor3 PORT MAP (internal1, internal2, internal3, aoi_output);
               END struct;



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                       LIBRARY ieee;
                       CONFIGURATION top_level OF aoi IS
                          FOR struct
                            FOR u1: and2 USE ENTITY WORK.and2(and2_behave);
                            END FOR;
                            FOR u2: and2 USE ENTITY WORK.and2(and2_behave);
                            END FOR;
                            FOR u3: and2 USE ENTITY WORK.and2(and2_behave);
                            END FOR;
                            FOR u4: nor3 USE ENTITY WORK.nor3(nor3_behave);
                            END FOR;
                          END FOR;
                       END top_level;



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           1.     USE WORK.util.ALL;
           2.     ENTITY mac IS
           3.      GENERIC (tco: time:= 10 NS);
           4.      PORT ( in1,in2: IN BIT_VECTOR(15 DOWNTO 0);
           5.              clk,reset: IN BIT;
           6.              out1: OUT BIT_VECTOR(31 DOWNTO 0) );
           7.     END mac;
           8.     ARCHITECTURE behave OF mac IS
           9.     BEGIN
           10.     PROCESS (clk,reset)
           11.      VARIABLE reg_in1, reg_in2, reg_mul, accum: INTEGER;
           12.     BEGIN
           13.      IF reset = '0' THEN
           14.      reg_in1 := 0;
           15.      reg_in2      := 0;
           16.      reg_mul := 0;
           17.      accum        := 0;
           18.      ELSIF rising_edge (clk) THEN
           19.      accum        := accum + reg_mul;
           20.      reg_mul          := reg_in1 + reg_in2;
           21.      reg_in1      := vect_to_int (in1);
           22.      reg_in2      := vect_to_int (in2);
           23.      END IF;
           24.      out1 <= int_to_vec (accum, 32) AFTER tco;
           25.     END PROCESS;
           26.    END behave;


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1. ARCHITECTURE structure OF mac IS
2.   COMPONENT reg
3.   GENERIC (width: INTEGER:= 16);
4.   PORT ( d: IN BIT_VECTOR ((width - 1) DOWNTO 0);
5.            clk: IN BIT;
6.            q: OUT BIT_VECTOR ((width - 1) DOWNTO 0) );
7.   END COMPONENT;
8.   COMPONENT adder
9.   PORT ( port1, port2: IN BIT_VECTOR (31 DOWNTO 0);
10.           output: OUT BIT_VECTOR (31 DOWNTO 0) );
11. END COMPONENT;
12. COMPONENT multiply
13. PORT ( port1, port2: IN BIT_VECTOR (15 DOWNTO 0);
14.           output: OUT BIT_VECTOR (31 DOWNTO 0) );
15. END COMPONENT;
16. COMPONENT buf
17. PORT ( input: IN BIT_VECTOR (31 DOWNTO 0);
18.           output: OUT BIT_VECTOR (31 DOWNTO 0) );
19. END COMPONENT;
20. SIGNAL reg_in1, reg_in2: BIT_VECTOR (15 DOWNTO 0);
21. SIGNAL mul, mul_reg, adder, accum: BIT_VECTOR (31 DOWNTO 0);
22. BEGIN
23. u1: reg GENERIC MAP (16) PORT MAP (in1, clk, reg_in1);
24. u2: reg GENERIC MAP (16) PORT MAP (in2, clk, reg_in2);
25. u3: multiply PORT MAP (reg_in1, reg_in2, mul);
26. u4: reg GENERIC MAP (32) PORT MAP (mul, clk, reg_mul);
27. u5: adder PORT MAP (reg_mul, accum, adder);
28. u6: reg GENERIC MAP (32) PORT MAP (adder, clk, accum);
29. u7: buf PORT MAP (accum, out1);
30. END structure;


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                       reg_in1

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                 u2 reg_in2
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                            u2: and2
                                  GENERIC MAP (2 NS, 1 NS);
                                  PORT MAP (in1, in2, in3);

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       1. USE WORK.util.ALL;
       2.    ARCHITECTURE mixed OF mac IS
       3.       COMPONENT reg
       4.       GENERIC (width: INTEGER:= 16);
       5.       PORT ( D: IN BIT_VECTOR (width - 1 DOWNTO 0);
       6.                clk: IN BIT;
       7.                Q: OUT BIT_VECTOR (width - 1, DOWNTO 0) );
       8.       END COMPONENT;
       9.       SIGNAL reg_in1, reg_in2, accum: BIT_VECTOR (15 DOWNTO 0);
       10.   BEGIN
       11.   -- structural description
       12.      u1: reg GENERIC MAP (16) PORT MAP (in1, clk, reg_in1);
       13.      u2: reg GENERIC MAP (16) PORT MAP (in2, clk, reg_in2);
       14.   -- behavioral description
       15.      PROCESS
       16.        VARIABLE temp1,temp2,mul,adder: INTEGER:= 0;
       17.      BEGIN
       18.        WAIT UNTIL clk = '1';             -- rising edge of clk
       19.        temp1 := vect_to_int (reg_in1);
       20.        temp2 := vect_to_int (reg_in2);
       21.        mul      := temp1 * temp2;
       22.        adder := accum + mul;
       23.        accum <= int_to_vect (adder, 32);
       24.      END PROCESS;
       25.   -- dataflow description
       26.      out1 <= accum;
       27.   END mixed;


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                    TYPE color IS (red, green, blue, yellow, violet, orange);



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                     TYPE std_ulogic IS ('U', '0', '1', 'Z', 'X', 'W', 'L', 'H', '-');



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                     SIGNAL clock : std_ulogic;
                     VARIABLE crayon : color := yellow;
                     CONSTANT clear : std_ulogic := '0';

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                     PACKAGE std_logic_1164 IS
                        TYPE std_ulogic IS ('U', '0', '1', 'Z', 'X', 'W', 'L', 'H', '-');
                     END std_logic_1164;
                     --
                     LIBRARY ieee;
                     USE ieee.std_logic_1164.ALL;
                     --
                     ENTITY mux IS
                        GENERIC ( tplh: TIME := 3 NS; tphl: TIME := 5 NS;
                                    sel_out: TIME := 3 NS );
                        PORT ( in1, in2, sel: IN std_ulogic;
                                 output: OUT std_ulogic );
                     END mux;



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                   ENTITY mux IS
                     TYPE std_ulogic IS ('U', '0', '1', 'Z', 'X', 'W', 'L', 'H', '-');
                     GENERIC ( tplh: TIME := 3 NS; tphl: TIME := 5 NS;
                                 sel_out: TIME := 3 NS );
                     PORT ( in1, in2, sel: IN std_ulogic;
                             output: OUT std_ulogic );
                   END mux;



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                           Elaboration
                                                                   Elaboration



                           Initialization
                                                                   Initialize All
                                                                     Objects



                                                                Run All Concurrent
                                                                   Statements



                           Simulation Cycle

                                                                    Schedule
                                                                  Future Events




                                        DONE               NO      Any Events?


                                                                       YES



                                                     YES        Any Events Now?        NO




                                                                                      Advance Simulation
                                                                                            Time

                                    Delta = Delta + 1

                                                                                            Delta = 0




                                                                Run All Sensitive
                                                                  Statements




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                                                          ENTITY concurrent IS
                                                           PORT (a, b, c : IN BIT; z : OUT BIT);
                                                          END concurrent;
       a                            x                     ARCHITECTURE concurrency OF concurrent IS
                              g2
       b                                                   SIGNAL w, x, y : BIT;
                g1       w               g4       z       BEGIN
                                                           w <= NOT a AFTER 12 NS;
                              g3
       c                                                   x <= a AND b AFTER 12 NS;
                                    y
                                                           y <= c AND w AFTER 12 NS;
                                                           z <= x OR y AFTER 12 NS;
                                                          END concurrency;



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                                    ARCHITECTURE delta_time OF concurrent IS
                                     SIGNAL w, x, y : BIT := '0';
                                    BEGIN
                                     y <= c AND w;
                                     w <= NOT a;
                                     x <= a AND b;
                                     z <= x OR y AFTER 36 NS;
                                    END delta_time;



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                 a   1

                 b   1

                 c   1

                w    0

                 x   0

                 y   0

                 z   1


                         0 1δ 2δ 3δ 0                   12               24              36 NS.


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                            ARCHITECTURE concurrent OF delta_time IS
                              SIGNAL a, b, c : BIT := '0';
                            BEGIN
                              a <= '1';
                              b <= NOT a;
                              c <= NOT b;
                            END concurrent;




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                                 a     0


                                 b     0


                                 c     0




                                           0                 1δ           2δ          3δ          0   NS.


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                                                        ns        delta   a   b   c
                                                        0          +0     0   0   0
                                                        0          +1     1   1   1
                                                        0          +2     1   0   0
                                                        0          +3     1   0   1



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                                                        END PROCESS [label] ;



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Šµœ˜µ¤‡Îµ­´ÉŠ×¥Á¦·É¤‹µ„‡Îµ­´ÉŠÂ¦„…°Š»—‡Îµ­´ÉŠSURFHVV˜n°‹µ„‡Îµ­´ÉŠ%(*,1Á¦¸¥Š¨Îµ—´¨Š­¼n‡Îµ
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ORRS š¸ÉŤn¦¼o‹…¹Êœ£µ¥Äœ­nªœ…°Š»—‡Îµ­´ÉŠÂ¨Îµ—´…°Š»—‡Îµ­´ÉŠ SURFHVV ª·›¸„µ¦š¸É‹³žj°Š„´œ
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                                 do_nothing: PROCESS
                                             BEGIN
                                             END PROCESS do_nothing;



                                                          ž
                                                        ¦¼ š¸É 3URFHVVVWDWHPHQW



     „¨nµªÄœšš¸É


                                                                    
                                                                                                3URFHVV6WDWHPHQW




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Ĝ˜´ª°¥nµŠ˜n°Åž‹³Áž}œ»—‡Îµ­´ÉŠ SURFHVV š¸Éčo­¦oµŠ­´µ–œµ¯·„µ ­´µ–š¸ÉÁž¨¸É¥œ¦³—´‡nµ
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                                 clock: PROCESS (clk)
                                          VARIABLE periodic : BIT := 0;
                                            BEGIN
                                              periodic := NOT (periodic) AFTER 50 NS;
                                              clk <= periodic;
                                            END PROCESS clock;



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       •    WAIT ON signal_list;              --   signal sensitivity
       •    WAIT UNTIL condition;             --   condition
       •    WAIT FOR time;                    --   timeout
       •    WAIT;                             --   forever

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           ♦    WAIT FOR 10 NS;

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                                     IF condition THEN
                                     {sequential-statement(s)}
                                  [{ ELSIF condition THEN      }
                                        {sequential_statement(s)}]
                                  [ ELSE
                                        {sequential_statements}]
                                     END IF;



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IF statement

                                                                                       IF
    Format: IF condition THEN
                sequential_statement(s)
            END IF;                                                              Condition                TRUE


                                                                                                            Sequential
                                                                                      FALSE                Statement(s)

      ª µ
    ˜´ °¥n Š:     IF a = '1' THEN
                      count := count + 1;                                         END IF
                    END IF;



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IF-ELSE construct
                                                                                                 IF
    Format: IF condition THEN
                sequential_statement(s)
                                                                               FALSE          Condition          TRUE
            ELSE
                sequential_statement(s)                                 Sequential                                 Sequential
                                                                       Statement(s)                               Statement(s)
            END IF;

                                                                                              END IF




      ª µ
    ˜´ °¥n Š     IF a = '1' THEN
                     one_count := count + 1;
                    ELSE
                     two_count := count + 2;
                    END IF;



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šµŠž’·´˜·Ä®o„´šµŠÁ¨º°„°¸„®œšµŠ®œ¹ÉŠ ¨³‹µ„Äœ˜´ª°¥nµŠ…oµŠœ ‹³Á®ÈœÅ—oªnµÁž}œ„µ¦šÎµŠµœ
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                                          one_count := count + 1;




                                                        
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š¸ÉÁž}œšµŠÁ¨º°„°¸„®œšµŠ®œ¹ÉŠÅžšÎµ‡Îµ­´ÉŠÂ¦„š¸É˜n°‹µ„‡Îµ­´ÉŠ(1',)˜n°Åž­Îµ®¦´‡Îµ­´ÉŠ
                                            two_count := count + 2;

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IF - ELSIF construct
                                                                                                   IF
Format: IF condition THEN
            sequential_statement(s)                                                 FALSE      Condition    TRUE


        ELSIF condition THEN                                                                                  Sequential
                                                                           Condition        TRUE             Statement(s)
           sequential_statement(s)
                                                                                              Sequential
        END IF;                                                             FALSE            Statement(s)




                                                                                                END IF


  ª µ
˜´ °¥n Š     IF a = 'X'      THEN
                  b := b + 1;
                ELSIF a = '0'       THEN
                  c := c + 1;
                ELSIF a = '1'       THEN
                  d := d+1;
                ELSIF a = 'Z'       THEN
                  e := e + 1;
                E    N     D            I     F      ;




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®¨µ¥°´œ ¨³Äœ…–³Á—¸¥ª„´œ„Ȥ¸ ®¨µ¥®œšµŠž’·´˜· —´Šš¸É­—ŠÄœ˜´ª°¥nµŠ Ĝ„¦–¸š¸É D Áž}œ
VLJQDO®¦º°YDULDEOH­µ¤µ¦™¤¸‡nµÅ—o ‡nµŗo„n 
;




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                                                  ELSE e := e + 1;

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              IF b = '0' THEN                                           IF b = '0' THEN
                 b := b +1;                                             b := b + 1;
              ELSIF a = '0' THEN                                            IF a = '1' THEN
                 c := c + 1;                                                   c := c +1;
              END IF;                                                       END IF;
                                                                        END IF;




                            IF                                                   IF


           FALSE          b = 0?       TRUE                                    b = 0?        FALSE



   a = 0?          TRUE
                                          b := b + 1;                          TRUE


                                                                             b := b + 1;
                      c := c + 1;
   FALSE



                                                                FALSE          a = 0?
                          END IF
                                                                               TRUE


                                                                             c := c + 1;


                                                                              END IF


                                                                                                END IF




                                                
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š¸É°¥¼nªŠœ°„­»— čo­°™µ¤­´µ– FON »—š¸É­°Š°¥¼nªŠÄœ¤¸®œoµš¸É­°™µ¤…o°¤¼¨ VHO Á¡ºÉ°„µ¦
˜´—­·œÄ‹„ε®œ—‡nµRXWSXWÁœºÉ°Š‹µ„352&(66‹³šÎµŠµœÅ—o„Șn°Á¤ºÉ°Á„·—HYHQWš¸É­´µ–FONœ´Êœ
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 ENTITY clocked_mux IS

  PORT ( inputs: IN BIT_VECTOR (0 TO 3);                                                        IF
         sel: IN BIT_VECTOR (0 TO 1);
         clk: IN BIT; output: OUT BIT);                                                      clk = 1?         FALSE
 END clocked_mux;
                                                                                              TRUE
 ARCHITECTURE behave_if OF clocked_mux
 IS                                                                              TRUE       sel = "00"
 BEGIN
   PROCESS (clk)                                                      temp := inputs (0);     FALSE

      VARIABLE temp: BIT;
   BEGIN                                                                         TRUE       sel = "01"
      IF clk = '1' THEN
          IF sel = "00"        THEN                                   temp := inputs (1);     FALSE

               temp := inputs (0);
                                                                                 TRUE       sel = "10"
          ELSIF sel = "01" THEN
               temp := inputs (1);
                                                                      temp := inputs (2);     FALSE
          ELSIF sel = "10" THEN
               temp := inputs (2);                                                      temp := inputs (3);
          ELSE
               temp := inputs (3);
                                                                                             END IF
          END IF;
          output <= temp AFTER 5 NS;
      END IF;
                                                                                             END IF
   END PROCESS;
 END behave_if;




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FDVHVWDWHPHQW¤¸„‘Á„–”r„µ¦Á…¸¥œ—´Šœ¸Ê

               CASE expression IS
                 WHEN choice => sequential statement(s)
               [ WHEN choice => sequential statement(s) ]
               END CASE;



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š¸ÉÁž}œ„µ¦Á…¸¥œFORFNHGPXOWLSOH[HU…¹ÊœÄ®¤nץčo&$6(VWDWHPHQW

               ARCHITECTURE behave_case OF clocked_mux IS
               BEGIN
                 PROCESS (clk)
                 VARIABLE temp: BIT;
                 BEGIN
                    CASE clk IS
                      WHEN '1' => CASE sel IS
                                       WHEN "00" => temp := inputs (0);
                                       WHEN "01" => temp := inputs (1);
                                       WHEN "10" => temp := inputs (2);
                                       WHEN "11" => temp := inputs (3);
                                 END CASE;
                                 output <= temp AFTER 5 NS;
                      WHEN OTHERS => NULL;        -- do nothing
                    END CASE;
                 END PROCESS;
               END behave_case;



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                    [label:]    [iteration_scheme] LOOP
                                                     sequential statement(s)
                                                   END LOOP [label] ;

                    iteration schemes
                               FOR loop_iteration_range
                               WHILE condition,



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…nµ¥UDQJHš¸É„ε®œ—


                            [label:]        FOR loop_parameter IN discrete_range
                                            LOOP
                                              sequential statement(s)
                                            END LOOP [label] ;



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                            lb1:       FOR index IN 0 TO 7 LOOP
                                         ray_out (index) <= ray_in (index);
                                       END LOOP lb1;



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                                    lb1:    FOR index IN 7 DOWNTO 0 LOOP

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:+,/(/223

                            [label:]    WHILE boolean_expression
                                        LOOP
                                          sequential statement(s)
                                        END LOOP [label] ;



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       p1:PROCESS (signal_a)
                 VARIABLE index: INTEGER := 0;
               BEGIN
                 from_in_to_out:  WHILE index < 8 LOOP
                                    ray_out (index)  <=    ray_in (index);
                                               index :=    index + 1;
                                  END LOOP from_in_to_out;
               END PROCESS p1;



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                                                             ASSERT condition
                                                        [    REPORT string ]
                                                        [    SEVERITY level   ];



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                            PROCESS (clk)
                            BEGIN
                              IF clk = 'X' THEN
                                  ASSERT FALSE
                                  REPORT "Clock is unknow"
                                  SEVERITY ERROR ;
                              END IF;
                            END PROCESS;


                                                              D

                            PROCESS (clk)
                            BEGIN
                                 ASSERT (address < 1024)
                                 REPORT "Address out of range!"
                                 SEVERITY WARNING ;
                            END PROCESS;


                                                              E

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                          ASSERT (clock'LAST_EVENT >= 50 NS))
                          REPORT "Pulse width violation on clock!"
                          SEVERITY ERROR ;



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         ARCITECTURE arch1 OF and2 IS                       ARCITECTURE arch2 OF and2 IS
         BEGIN                                              BEGIN
          output <= in1 AND in2;                              PROCESS (in1, in2)
         END arch1;                                           BEGIN
                                                                 output <= in1 AND in2;
                                                              END PROCESS;
                                                            END arch2;


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               ARCHITECTURE and2 OF and2 IS
               BEGIN
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               END and2;

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                 FUNCTION rising (sig: BIT) RETURN BOOLEAN IS
                 BEGIN
                    IF sig := '0' THEN
                        RETURN FALSE;
                    ELSE
                        RETURN TRUE;
                    END IF;
                 END rising;
                 FUNCTION falling (sig: BIT) RETURN BOOLEAN IS
                 BEGIN
                    IF sig = '0' THEN
                        RETURN TRUE;
                    ELSE
                        RETURN FALSE;
                    END IF;
                 END falling;
               BEGIN
                 output <=in1 AFTER tplh       WHEN sel = '0' AND rising (in1) ELSE
                               in1 AFTER tphl    WHEN sel = '0' AND falling (in1) ELSE
                               in2 AFTER tplh    WHEN sel = '1' AND rising (in2) ELSE
                               in2 AFTER tphl    WHEN sel = '1' AND falling (in2) ELSE
                               '0' AFTER tphl;
               END rtl;




                                                    
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       ENTITY mux IS
         PORT ( input: IN BIT_VECTOR (0 TO 3);
                  sel: IN BIT_VECTOR (0 TO 1);
                  output: OUT BIT );
       END mux;
       ARCHITECTURE simple_con OF mux IS
       BEGIN
         WITH sel SELECT
            output <=input (0) AFTER 5 NS WHEN "00",
                         input (1) AFTER 5 NS WHEN ''01",
                         input (2) AFTER 5 NS WHEN "10",
                         input (3) AFTER 5 NS WHEN "11";
       END simple_con;

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       ARCHITECTURE simple_seq OF mux IS
       BEGIN
         PROCESS (input, sel)
         BEGIN
            CASE sel IS
               WHEN "00"      => output <=                     input (0)   AFTER 5 NS;
               WHEN "01"      => output <=                     input (1)   AFTER 5 NS;
               WHEN "10"      => output <=                     input (2)   AFTER 5 NS;
               WHEN "11"      => output <=                     input (3)   AFTER 5 NS;
            END CASE;
         END PROCESS;
       END simple_seq;




                                            
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   ARCHITECTURE structure OF mac IS
     COMPONENT reg
     GENERIC (width: INTEGER:= 16);
     PORT ( d: IN BIT_VECTOR ((width - 1) DOWNTO 0);
            clk: IN BIT;
            q: OUT BIT_VECTOR ((width - 1) DOWNTO 0) );
     END COMPONENT;
     COMPONENT adder
     PORT ( port1, port2: IN BIT_VECTOR (31 DOWNTO 0);
            output: OUT BIT_VECTOR (31 DOWNTO 0) );
     END COMPONENT;
     COMPONENT multiply
     PORT ( port1, port2: IN BIT_VECTOR (15 DOWNTO 0);
            output: OUT BIT_VECTOR (31 DOWNTO 0) );
     END COMPONENT;
     COMPONENT buf
     PORT ( input: IN BIT_VECTOR (31 DOWNTO 0);
            output: OUT BIT_VECTOR (31 DOWNTO 0) );
     END COMPONENT;

       SIGNAL reg_in1, reg_in2: BIT_VECTOR (15 DOWNTO 0);
       SIGNAL mul, mul_reg, adder, accum: BIT_VECTOR (31 DOWNTO 0);

   BEGIN
     u1: reg GENERIC MAP (16) PORT MAP (in1, clk, reg_in1);
     u2: reg GENERIC MAP (16) PORT MAP (in2, clk, reg_in2);
     u3: multiply PORT MAP (reg_in1, reg_in2, mul);
     u4: reg GENERIC MAP (32) PORT MAP (clk => clk, D => mul, Q => reg_mul);
     u5: adder PORT MAP (reg_mul, accum, adder);
     u6: reg GENERIC MAP (32) PORT MAP (adder, clk, accum);
     u7: buf PORT MAP (accum, out1);
   END structure;



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            ASSERT (clk /= 'X')              REPORT "Clock is unknow"
                                             SEVERITY ERROR;


            ASSERT (address < 1024) REPORT "Address out of range!"
                                    SEVERITY WARNING;


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                                 {concurrent_statements}
                              END GENERATE [generate_label] ;

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                                   | IF condition


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                    ENTITY reg_16 IS
                      PORT ( input: IN BIT_VECTOR (0 TO 15);
                               clock: IN BIT;
                               output: OUT BIT_VECTOR (0 TO 15) );
                    END reg_16;

                    ARCHITECTURE struct OF reg_16 IS
                      COMPONENT dff
                         PORT d, clk: IN BIT; q: OUT BIT);
                      END COMPONENT;
                    BEGIN
                      g1: FOR i IN 0 TO 15 GENERATE
                         g1: dff PORT MAP (input(i), clock, output (i));
                      END GENERATE g1;
                    END struct;


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         FUNCTION vect_to_int (vect : BIT_VECTOR (0 TO 3)) RETURN INTEGER;
         FUNCTION rising (SIGNAL sig : BIT) RETURN BOOLEAN;
         FUNCTION falling (SIGNAL sig : BIT) RETURN BOOLEAN;
        END util;


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               FUNCTION example (a, b : IN BIT) RETURN BOOLEAN IS
               BEGIN
               RETURN a = b;
               END example;


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      PACKAGE BODY util IS
       FUNCTION vect_to_int (vect : BIT_VECTOR (0 TO 3)) RETURN INTEGER IS
         VARIABLE result : INTEGER := 0;
         VARIABLE weight : INTEGER := 1;
       BEGIN
         FOR i IN 0 TO 3 LOOP
            IF vect (i) = '1' THEN
                result := result + weight;
            END IF;
            weight := weight * 2;
         END LOOP;
         RETURN result;
       END vect_to_int;

        FUNCTION rising (SIGNAL sig : BIT) RETURN BOOLEAN IS
        BEGIN
          IF sig = '0' THEN
              RETURN FALSE;
          ELSE
              RETURN TRUE;
          END IF;
        END rising;

       FUNCTION falling (SIGNAL sig : BIT) RETURN BOOLEAN IS
       BEGIN
         IF sig = '0' THEN
             RETURN TRUE;
         ELSE
             RETURN FALSE;
         END IF;
       END falling;
      END util;


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       PACKAGE BODY util IS
           PROCEDURE add_element (element : IN REAL;
                             VARIABLE filter_data : INOUT filter_data_type) IS
           BEGIN
             FOR IN filter_data'HIGH DOWNTO filter_data'LOW + 1 LOOP
                  filter_data (i) := filter_data (i - 1);
             END LOOP;
             filter_data (filter_data'LOW) := elememt;
           END add_element;

           PROCEDURE zero_out (input : INOUT filter_data_type) IS
           BEGIN
             FOR i IN input'RANGE LOOP
                input (i) := 0.0;
             END LOOP;
           END zero_out;

         PROCEDURE still_busy IS
         BEGIN
            ASSERT FALSE REPORT "Still Busy!" SEVERITY NOTE;
         END still_busy;
       END util;


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   PACKAGE utility IS
     PROCEDURE bin_to_int (bin_in : IN BIT_VECTOR; int_out : OUT INTEGER);
     PROCEDURE int_to_bin (int_in : IN INTEGER; bin_out : OUT BIT_VECTOR);
     FUNCTION inc_bin (x : BIT_VECTOR) RETURN BIT_VECTOR;
   END utility;
   --
   PACKAGE BODY utility IS
      PROCEDURE bin_to_int (bin_in : IN BIT_VECTOR; int_out : OUT INTEGER) IS
        VARIABLE result : INTEGER;
      BEGIN
        result := 0;
        FOR i IN 0 TO (bin_in'LENGTH - 1) LOOP
           IF bin_in(i) = '1' THEN
              result := result + 2**i;
           END IF;
        END LOOP;
        int_out := result;
      END bin_to_int;
   --
      PROCEDURE int_to_bin (int_in : IN INTEGER; bin_out : OUT BIT_VECTOR) IS
        VARIABLE tmp : INTEGER;
      BEGIN
        tmp := int_in;
        FOR i IN 0 TO (bin_out'LENGTH - 1) LOOP
           IF (tmp MOD 2 = 1) THEN
             bin_out(i) := '1';
           ELSE bin_out(i) := '0';
           END IF;
           tmp := tmp/2;
        END LOOP;
      END int_to_bin;
      FUNCTION inc_bin (x : BIT_VECTOR) RETURN BIT_VECTOR IS
       VARIABLE i : INTEGER;
       VARIABLE t : BIT_VECTOR (x'RANGE);
      BEGIN
       bin_to_int (x, i);
       i := i + 1;
       IF i >= 2**x'LENGTH THEN i := 0;
       END IF;
       int_to_bin (i, t);
       RETURN t;
      END inc_bin;
   END utility;


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       USE WORK.utility.ALL;
       --
       ENTITY ttl_74ls163_counter IS
          GENERIC (prop_delay : TIME := 18 NS);
          PORT ( clk, clr_bar, ld_bar, enp, ent : IN BIT;
                     abcd : IN BIT_VECTOR (3 DOWNTO 0);
                     q_abcd : OUT BIT_VECTOR (3 DOWNTO 0); rco : OUT BIT );
       END ttl_74ls163_counter;
       ARCHITECTURE behavioral OF ttl_74ls163_counter IS
       BEGIN
          counting : PROCESS (clk)
             VARIABLE internal_count : BIT_VECTOR (3 DOWNTO 0) := "0000";
          BEGIN
             IF (clk = '1') THEN
                 IF (clr_bar = '0') THEN
                     internal_count := "0000";
                 ELSIF (ld_bar = '0' ) THEN
                     internal_count := abcd;
                 ELSIF (enp = '1' AND ent = '1' ) THEN
                     internal_count := inc_bin (internal_count);
                     IF (internal_count = "1111") THEN
                         rco <= '1' AFTER prop_delay;
                     ELSE
                         rco <= '0';
                     END IF;
                 END IF;
                 q_abcd <= internal_count AFTER prop_delay;
             END IF;
          END PROCESS counting;
       END behavioral;


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--
ENTITY ttl_74ls163_counter IS
    GENERIC (prop_delay : TIME := 18 NS);
    PORT ( clk, clr_bar, ld_bar, enp, ent : IN BIT;
                 abcd : IN BIT_VECTOR (3 DOWNTO 0);
                 q_abcd : OUT BIT_VECTOR (3 DOWNTO 0); rco : OUT BIT );
END ttl_74ls163_counter;
ARCHITECTURE behavioral OF ttl_74ls163_counter IS
--
   PROCEDURE bin_to_int (bin_in : IN BIT_VECTOR; int_out : OUT INTEGER) IS
     VARIABLE result : INTEGER;
   BEGIN
     result := 0;
     FOR i IN 0 TO (bin_in'LENGTH - 1) LOOP
        IF bin_in(i) = '1' THEN
           result := result + 2**i;
        END IF;
     END LOOP;
     int_out := result;
   END bin_to_int;
--
   PROCEDURE int_to_bin (int_in : IN INTEGER; bin_out : OUT BIT_VECTOR) IS
     VARIABLE tmp : INTEGER;
   BEGIN
     tmp := int_in;
     FOR i IN 0 TO (bin_out'LENGTH - 1) LOOP
        IF (tmp MOD 2 = 1) THEN
          bin_out(i) := '1';
        ELSE bin_out(i) := '0';
        END IF;
        tmp := tmp/2;
     END LOOP;
   END int_to_bin;
   FUNCTION inc_bin (x : BIT_VECTOR) RETURN BIT_VECTOR IS
    VARIABLE i : INTEGER;
    VARIABLE t : BIT_VECTOR (x'RANGE);
   BEGIN
    bin_to_int (x, i);
    i := i + 1;
    IF i >= 2**x'LENGTH THEN i := 0;
    END IF;
    int_to_bin (i, t);
    RETURN t;
   END inc_bin;
--
BEGIN
    counting : PROCESS (clk)
         VARIABLE internal_count : BIT_VECTOR (3 DOWNTO 0) := "0000";
    BEGIN
         IF (clk = '1') THEN
             IF (clr_bar = '0') THEN
                 internal_count := "0000";
             ELSIF (ld_bar = '0' ) THEN
                 internal_count := abcd;
             ELSIF (enp = '1' AND ent = '1' ) THEN



                                       
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           internal_count := inc_bin (internal_count);
           IF (internal_count = "1111") THEN
               rco <= '1' AFTER prop_delay;
           ELSE
               rco <= '0';
           END IF;
       END IF;
       q_abcd <= internal_count AFTER prop_delay;
     END IF;
  END PROCESS counting;
END behavioral;




                                          
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                      END COMPONENT;

                      COMPONENT or2 IS
                         PORT ( or1, or2: IN BIT;
                                  or_out: OUT BIT );
                      END COMPONENT;
                      SIGNAL internal_1: BIT;
                     BEGIN
                      u1:and2     PORT MAP (in1, in2, internal_1);
                      u2:or2      PORT MAP (in3, internal_1, out_1);
                     END structure;


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                                 END FOR;
                                 FOR u2: or2 USE CONFIGURATION parts.or2_con
                                 END FOR;
                               END FOR;
                            END mux_con;



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              LIBRARY parts;
              ARCHITECTURE structure OF and_or IS
                  COMPONENT and2
                     PORT ( and1, and2: IN BIT;
                               and_out: OUT BIT );
                  END COMPONENT;
              -- configuration specification in architecture
                  FOR u1: and2 USE ENTITY WORK.and2(behave);

                  COMPONENT or2
                     PORT ( or1, or2: IN BIT;
                               or_out: OUT BIT );
                  END COMPONENT;
              -- configuration specification in architecture
                  FOR u2: or2 USE CONFIGURATION parts.or2_con;

                SIGNAL internal_1: BIT;
              BEGIN
                u1:and2 PORT MAP (in1, in2, internal_1);
                u2:or2 PORT MAP (in3, internal_1, out_1);
              END structure;


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                PACKAGE util IS
                    TYPE mvl3 IS ('X', '0', '1');
                    TYPE mvl4 IS ('X', '0', '1', 'Z');
                    TYPE mvl3_vector IS ARRAY (natural RANGE <>) OF mvl3;
                    TYPE mvl4_vector IS ARRAY (natural RANGE <>) OF mvl4;
                -- overloaded functions:
                    FUNCTION rotate_left (input: mvl3_vector) RETURN mvl3_vector
                    FUNCTION rotate_left (input: mvl4_vector) RETURN mvl4_vector
                END util;


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                 ENTITY reg IS
                   GENERIC (tsu: TIME := 3 NS);
                   PORT ( d: IN BIT_VECTOR (3 DOWNTO 0);
                             clk: IN BIT;
                             q: OUT BIT_VECTOR (3 DOWNTO 0) );
                 BEGIN
                   PROCESS (clk)
                   BEGIN
                      IF clk = '1' THEN
                          ASSERT (d'LAST_EVENT > tsu)
                             REPORT "Setup Violation on th d Input!"
                             SEVERITY ERROR;
                      END IF;
                   END PROCESS;
                 END reg;


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                    TYPE mvl4 IS ('X', '0', '1', 'Z');
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  'RIGHT                      right bound         sq_4_8'RIGHT                           0
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  'HIGH                       upper bound         sq_4_8'HIGH(2)                         7

  'LOW                        lower bound         sq_4_8'LOW(2)                          0

  'RANGE                      range               sq_4_8'RANGE(2)                        0 TO 7
                                                  sq_4_8'RANGE(1)                        3 DOWNTO 0

  'REVERSE_RANGE              reverse range       sq_4_8'REVERSE_RANGE(2)                7 DOWNTO 0
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                             TYPE qit IS ('0', '1', 'Z', 'X');
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               ARCHITECTURE wired_and OF multiple_circuit IS
                 FUNCTION anding (drivers : BIT_VECTOR) RETURN BIT IS
                     VARIABLE accumulate : BIT := '1';
                 BEGIN
                     FOR i IN drivers'RANGE LOOP
                        accumulate := accumulate AND drivers(i);
                     END LOOP;
                     RETURN accumulate;
                 END anding;
                 SIGNAL circuit_node : anding BIT;
               BEGIN
                 circuit_node <= a;
                 circuit_node <= b;
                 circuit_node <= c;
                 circuit_node <= d;
                            z <= circuit_node;
               END wired_and;


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                            Test-program                         29.0%
                             generators                                35.7%           1990
                                                                                       1993

                                                                     30.9%
                          Logic synthesis
                                                                             41.1%


                                                                                                          83.1%
                       Schematic capture
                                                                                                         82.0%

                                                                         37.2%
                    Behavioral Simulation
                                                                             39.7%


                                                                                                        80.2%
                                     PCB
                                                                                                        81.5%


                                            0      10     20    30      40       50   60      70   80      90

                                                (Source: EDN P&C, EDA Survey, 1993)



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‹»—Á¦·É¤˜oœ…°Š„µ¦¡´•œµ£µ¬µš¸Éčo¦¦¥µ¥¦³š¸É¤¸­´µ–Ÿ­¤PL[HGVLJQDOV\VWHP˜n°
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                          40%

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                          20%
                                                                                       12.5%
                          15%

                          10%

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                           0%

                                            (Source: EDN P&C, EDA Survey, 1993)



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                                                                      XVI
                                                                         Ÿœª„„

                         Memory Part




         ENTITY memory_part IS
          PORT (d_in0, d_in1, clocking: IN BIT;
                 d_out0, d_out1: OUT BIT);
d_in0    END memory_part;
         ARCHITECTURE dataflow OF memory_part IS
          BEGIN
d_in1      dd: BLOCK (clocking = ‘1’ AND (NOT clocking’STABLE (2 NS)))
              BEGIN
                d_out0 <= GUARDED d_in0 AFTER 11 NS;
clocking        d_out1 <= GUARDED d_in1 AFTER 11 NS;
              END BLOCK dd;                                   d_out0
         END dataflow;
                                                                d_out1




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                         Logical Part




         ENTITY logical_part IS
          PORT (in0, in1, q0, q1: IN BIT;
                 d0, d1, out1: OUT BIT);                           d0
         END logical_part;
         ARCHITECTURE dataflow OF logical_part IS
                                                                   d1
         BEGIN
          d0 <= (in0 AND q0) OR (in0 AND q1) AFTER 12 NS;
          d1 <= (NOT q0) AND (NOT q1) AND in0 AFTER 14 NS;         q0

in0       out1 <= (NOT in0) AND (NOT in1) AND q0 AFTER 14 NS;
         END dataflow;                                             q1

in1                                                               out1




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                                XVII
                                                                                           Ÿœª„„

                   Clock Component

       ENTITY clock_component IS
        PORT (en: IN BIT;
               ck: OUT BIT);
       END clock_component;
       ARCHITECTURE behavioral OF clock_component IS
       BEGIN
        PROCESS
         VARIABLE periodic: BIT := ‘1’;
en      BEGIN                                                                         ck
         IF en = ‘1’ THEN
          periodic := NOT periodic;
         END IF;
         ck <= periodic;
         WAIT FOR 50 NS;
         END PROCESS;
       END behavioral;




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      Finite State Machine Component
      ENTITY fsm_component IS
       PORT (x, y, clk: IN BIT;
                z: OUT BIT);
      END fsm_component;                                       c2
 x    ARCHITECTURE structural
                                                          d_in0
       OF fsm_component IS
      COMPONENT logical_part                              d_in1
       PORT (in0, in1, q0, q1: IN BIT;
                                             is4   is3             d_out1
               d0, d1 out1: OUT BIT);                     clocking
      END COMPONENT;                                              d_out0

      COMPONENT memory_part
                                                                                  z
 y     PORT (d_in0, d_in1, clocking: IN BIT;
               d_out0, d_out1: OUT BIT);
      END COMPONENT;
                                                                  d0
       SIGNAL is1, is2, is3, is4: BIT;                    c1
      BEGIN                                                       d1
                                                         in0                is1
       c1: logical_part PORT MAP                                  q0
           (x, y, is1, is2, is3, is4, z);                                   is2
                                                                  q1
       c2: memory_part PORT MAP                          in1
                                                               out1
clk        (is3, is4, ck, is1, is2);
      END structural;




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                                XVIII
                                                                                                              Ÿœª„„

                                           Sequence Detector

                            ENTITY sequence_detector IS
                             PORT (x_in, y_in, enable: IN BIT;
                                    z_out: OUT BIT);
                            END sequence_detector;
                            ARCHITECTURE structural OF sequence_detector IS
                            COMPONENT clock_component
                             PORT (en: IN BIT;
                                    ck: OUT BIT);
                            END COMPONENT;
                            COMPONENT fsm_component
                                                                                     z_out
              x_in           PORT (x, y, clk: IN BIT;
                                    z: OUT BIT);
                            END COMPONENT;
              y_in           SIGNAL internal_line: BIT;
                            BEGIN
                             c1: clock_component PORT MAP (enable, internal_line);
              enable         c2: fsm_component PORT MAP (x_in, y_in, internal_line, z_out);
                            END structural;




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          -------------------------------------------------------------------------------------------------
          -- Interface description for sequence detector.
          -------------------------------------------------------------------------------------------------
          -- Top-level
          -------------------------------------------------------------------------------------------------
          ENTITYsequence_detector IS
              PORT ( x_in, y_in, enable: IN BIT;
                         z_out: OUT BIT);
          END sequence_detector;
          ------------------------------------------------------------------------------------------------
          -- Interface descriptions for sequence detector
          -- after 1st partition.
          -------------------------------------------------------------------------------------------------
          -- Interface description for the finite state machine component.
          -------------------------------------------------------------------------------------------------
          ENTITYfsm_component IS
              PORT ( x, y, clk: IN BIT;
                         z: OUT BIT);
          END fsm_component;
          ------------------------------------------------------------------------------------------------
          -- Interface description for the clock component.
          ------------------------------------------------------------------------------------------------
          ENTITYclock_component IS
              PORT ( en: IN BIT;
                         clk: OUT BIT);
          END clock_component;




                                                         XIX
                                                                                                  Ÿœª„„

-----------------------------------------------------------------------------------------------
-- Interface description for sequence detector
-- after 2nd partition.
-----------------------------------------------------------------------------------------------
-- Interface description for the logical part.
-----------------------------------------------------------------------------------------------
ENTITYlogical_part IS
     PORT ( in0, in1, q0, q1: IN BIT;
               d0, d1, out1: OUT BIT);
END logical_part;
-----------------------------------------------------------------------------------------------
-- Interface description for the memory part.
-----------------------------------------------------------------------------------------------
ENTITYmemory_part IS
     PORT ( d_in1, d_in1, clocking: IN BIT;
               d_out0, d_out1: OUT BIT);
END memory_part;
-----------------------------------------------------------------------------------------------
-- Architecture description for memory part.
-----------------------------------------------------------------------------------------------
ARCHITECTURE dataflow OF memory_part IS
BEGIN
  dd: BLOCK (clocking = '1' AND (NOT clocking'STABLE(2 NS)))
     BEGIN
       d_out0 <= GUARDED d_in0 AFTER 11 NS;
       d_out1 <= GUARDED d_in1 AFTER 11 NS;
     END BLOCK dd;
END dataflow;
---------------------------------------------------------------------------------------------
-- Architecture description for logical part.
---------------------------------------------------------------------------------------------
ARCHITECTURE dataflow OF logical_part IS
BEGIN
  d0       <= (in0 AND q0) OR (in0 AND q1) AFTER 12 NS;
  d1       <= (NOT q0) AND (NOT q1) AND in0 AFTER 14 NS;
  out1 <= (NOT in0) AND (NOT in1) AND q0 AFTER 14 NS;
END dataflow;
--------------------------------------------------------------------------------------------
-- Archtecture description for clock component.
--------------------------------------------------------------------------------------------
ARCHITECTURE behavioral OF clock_component IS
BEGIN
  PROCESS
    VARIABLE periodic: BIT := '1';
  BEGIN
    IF en = '1' THEN
      periodic := NOT periodic;
    END IF;
    ck <= periodic;
    WAIT FOR 50 NS;
  END PROCESS;
END behavioral;




                                                XX
                                                                                                             Ÿœª„„

           -----------------------------------------------------------------------------------------------
           -- Architecture description for finite state machine component.
           -----------------------------------------------------------------------------------------------
           ARCHITECTURE structural OF fsm_component IS
           -- component declaration
             COMPONENT logical_part
              PORT (in0, in1, q0, q1: IN BIT;
                        d0, d1, out1: OUT BIT);
             END COMPONENT;
             COMPONENT memory_part
              PORT (d_in0, d_in1, clocking: IN BIT;
                        d_out0, d_out1: OUT BIT);
             END COMPONENT;
           --
             SIGNAL is1, is2, is3, is4: BIT; -- intermediate signals
           BEGIN
            c1: logical_part PORT MAP (x, y, is1, is2, is3, is4, z);
            c2: memory_part PORT MAP (is3, is4, clk, is1, is2);
           END structural;
           -----------------------------------------------------------------------------------------------
           -- Archtecture description for sequence_detector.
           -----------------------------------------------------------------------------------------------
           ARCHITECTURE structural_1 OF sequence_detector IS
           -- component declaration
                 COMPONENT clock_component
                 PORT ( en: IN BIT;
                            ck: OUT BIT);
                 END COMPONENT;
                 COMPONENT fsm_component
                 PORT ( x, y, clk: IN BIT;
                            z: OUT BIT);
                 END COMPONENT;
                 FOR ALL: fsm_component
                      USE ENTITY WORK.fsm_component(structural);
                 SIGNAL internal_line: BIT; -- internal line (signal)
           BEGIN
             c1: clock_component PORT MAP (enable, internal_line);
             c2: fsm_component PORT MAP (x_in, y_in, internal_line, z_out);
           END structural_1;



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                                                          XXI
                                                                                           Ÿœª„„

                                         Seq_Detector_Test_Bench1


                                                    test_vector1


                                                    structure_1
                                  data       x_in




                                 level       y_in                  z_out   detect


                                switch       enable




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           -- VHDL Description of Test Bench
           --
           ENTITY seq_detector_test_bench1 IS
           END seq_detector_test_bench1;
           --
           ARCHITECTURE test_vector_1 OF seq_detector_test_bench1 IS
            COMPONENT sequence_detector
               PORT ( x_in, y_in, enable: IN BIT;
                         z_out: OUT BIT );
              END COMPONENT;
              FOR ALL: sequence_detector
                 USE ENTITYWORK.sequence_detector(structural_1);
              SIGNAL data:       BIT:= '0';
              SIGNAL level:       BIT:= '0';
              SIGNAL switch: BIT:= '0';
              SIGNAL detect: BIT;
           BEGIN
            c1: sequence_detector PORT MAP (data, level, switch, detect);
            c2: data <= '0',
                     '1' AFTER 80 NS,
                     '0' AFTER 180 NS,
                     '1' AFTER 280 NS,
                     '0' AFTER 480 NS,
                     '1' AFTER 580 NS,
                     '0' AFTER 780 NS,
                     '1' AFTER 880 NS,
                     '0' AFTER 1080 NS,
                     '1' AFTER 1280 NS;
            c3: switch <= '1' AFTER 20 NS,
                            '0' AFTER 1000 NS;
           END test_vector_1;




                                                       XXII
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            ARCHITECTURE behavioral OF fsm_component IS
             TYPE state IS (reset, got1, got11);
             SIGNAL present_state: state := reset;
            BEGIN
             st: PROCESS (clk)
                BEGIN
                 IF clk = '1' THEN
                  CASE present_state IS
                   WHEN reset =>
                    IF x = '1' THEN
                       present_state <= got1;
                    ELSE
                      present_state <= reset;
                    END IF;
                   WHEN got1 =>
                    IF x = '1' THEN
                      present_state <= got11;
                    ELSE
                      present_state <= reset;
                    END IF;
            WHEN got11 =>
                    IF x = '1' THEN
                      present_state <= got11;
                    ELSE
                      present_state <= reset;
                    END IF;
                   END CASE;
                 END IF;
                END PROCESS st;
             ot: PROCESS (x)
                BEGIN
                  IF (present_state = got11 AND x = '0') THEN
                  z <= TRANSPORT '1' AFTER 14 NS;
                  z <= TRANSPORT '0' AFTER 45 NS;
                  ELSE
                  z <= '0';
                  END IF;
                END PROCESS ot;
            END behavioral;




                                                    XXIV
                                                                                                      Ÿœª„„

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            ARCHITECTURE structural_2 OF sequence_detector IS

            -- component declaration
              COMPONENT clock_component
               PORT (en: IN BIT;
                       ck: OUT BIT );
              END COMPONENT;
              COMPONENT fsm_component
               PORT (x, y, clk: IN BIT;
                       z: OUT BIT);
              END COMPONENT;
              FOR ALL: fsm_component USE ENTITY
              WORK.fsm_component(behavioral);
            --
              SIGNAL internal_line: BIT; -- internal line (signal)
            BEGIN
              c1: clock_component PORT MAP (enable, internal_line);
              c2: fsm_component PORT MAP (x_in, y_in, internal_line, z_out);
            END structural_2;




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                                                      XXV
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                                                 XXVI
                                          Ÿœª„…
                        STANDARD MSI 74LS PACKAGES




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….1   Package utility
      LIBRARY ieee;
      USE ieee.std_logic_1164.ALL;
      --
      PACKAGE utility IS
        PROCEDURE stdlogicvector_to_int (stdlogicvector_in : IN std_logic_vector;
          int_out : OUT INTEGER);
        PROCEDURE int_to_stdlogicvector (int_in : IN INTEGER;
          stdlogicvector_out : OUT std_logic_vector);
        FUNCTION inc_int (x : std_logic_vector) RETURN std_logic_vector;
      END utility;
      PACKAGE BODY utility IS
         PROCEDURE stdlogicvector_to_int (stdlogicvector_in : IN std_logic_vector;
          int_out : OUT INTEGER) IS
          VARIABLE result : INTEGER;
         BEGIN
           result := 0;
           FOR i IN 0 TO (stdlogicvector_in'LENGTH - 1) LOOP
             ASSERT NOT((stdlogicvector_in(i) /= '0') OR (stdlogicvector_in(i) /= '1'))
               REPORT "Input data contents not '0' and '1' values!"
               SEVERITY NOTE;
             IF stdlogicvector_in(i) = '1' THEN
                result := result + 2**i;
             END IF;
           END LOOP;
           int_out := result;
         END stdlogicvector_to_int;
        PROCEDURE int_to_stdlogicvector (int_in : IN INTEGER;
          stdlogicvector_out : OUT std_logic_vector) IS
          VARIABLE tmp : INTEGER;
         BEGIN
           tmp := int_in;
           FOR i IN 0 TO (stdlogicvector_out'LENGTH - 1) LOOP
             IF (tmp MOD 2 = 1) THEN
               stdlogicvector_out(i) := '1';
             ELSE stdlogicvector_out(i) := '0';
             END IF;
             tmp := tmp/2;
           END LOOP;
         END int_to_stdlogicvector;




                                             XXVII
                                                                                 Ÿœª„…

       FUNCTION inc_int (x : std_logic_vector) RETURN std_logic_vector IS
        VARIABLE i : INTEGER;
        VARIABLE t : std_logic_vector (x'RANGE);
       BEGIN
        stdlogicvector_to_int (x, i);
        i := i + 1;
        IF i >= 2**x'LENGTH THEN i := 0;
        END IF;
        int_to_stdlogicvector (i, t);
        RETURN t;
       END inc_int;
      END utility;



…2   74LS85 4-BIT MAGNITUDE COMMPARATOR

      LIBRARY ieee;
      USE ieee.std_logic_1164.ALL;
      USE WORK.utility.ALL;

      ENTITY ttl_74ls85_comparator IS
       GENERIC (prop_delay : TIME := 11 NS);
      PORT ( a,b : IN std_logic_vector (3 DOWNTO 0); gt, eq, lt :IN std_logic;
                a_gt_b, a_eq_b, a_lt_b : OUT std_logic );
      END ttl_74ls85_comparator;
      ARCHITECTURE behavioral OF ttl_74ls85_comparator IS
      BEGIN
       PROCESS (a, b, gt, eq, lt)
       VARIABLE ai, bi : INTEGER;
       BEGIN
            stdlogicvector_to_int (a, ai);
            stdlogicvector_to_int (b, bi);
        IF ai > bi THEN                        -- a greater than b
            a_gt_b <= '1' AFTER prop_delay;
            a_eq_b <= '0' AFTER prop_delay;
            a_lt_b    <= '0' AFTER prop_delay;
        ELSIF ai < bi THEN                         -- a least than b
            a_gt_b <= '0' AFTER prop_delay;
            a_eq_b <= '0' AFTER prop_delay;
            a_lt_b    <= '1' AFTER prop_delay;
        ELSIF ai = bi THEN                         -- a equal b
            a_gt_b <= gt AFTER prop_delay;
            a_eq_b <= eq AFTER prop_delay;
            a_lt_b    <= lt AFTER prop_delay;
        END IF;
       END PROCESS;
      END behavioral;




                                          XXVIII
                                                                               Ÿœª„…

…3   74LS157 QUADRUPLE 2- LINE TO 1-LINE MULTIPLEXER

      LIBRARY ieee;
      USE ieee.std_logic_1164.ALL;
      USE WORK.utility.ALL;

      ENTITY ttl_74Is157 IS
        GENERIC (prop_delay : TIME := 18 NS);
        PORT ( g_bar, s : IN std_logic;
                    a4, b4 : IN std_logic_vector (3 DOWNTO 0 );
                    y4 : OUT std_logic_vector (3 DOWNTO 0) );
      END ttl_74Is157;
      ARCHITECTURE dataflow OF ttl_74Is157 IS
      BEGIN
        PROCESS (a4, b4, g_bar, s)
        BEGIN
            IF g_bar = '0' THEN
                IF s = '0' THEN
                    y4 <= a4 AFTER prop_delay;
                ELSE
                    y4 <= b4 AFTER prop_delay;
                END IF;
            ELSE
            y4 <= "0000";
            END IF;
        END PROCESS;
      END dataflow;

…4   74LS373 OCTAL D-TYPE TRANSPARENT LATCHES

      LIBRARY ieee;
      USE ieee.std_logic_1164.ALL;
      USE WORK.utility.ALL;

      ENTITY ttl_74Is373_register IS
        GENERIC (prop_delay : TIME := 15 NS);
        PORT ( enable, oc_bar : IN std_logic; d8 : IN std_logic_vector (7 DOWNTO 0);
                   q8 : OUT std_logic_vector ( 7 DOWNTO 0) );
      END ttl_74Is373_register;
      ARCHITECTURE dataflow OF ttl_74Is373_register IS
        SIGNAL state : std_logic_vector (7 DOWNTO 0);
      BEGIN
        reg: BLOCK ( enable = '1')
        BEGIN
            state <= GUARDED d8 AFTER prop_delay;
        END BLOCK reg;
        q8 <= state WHEN oc_bar = '0' ELSE "ZZZZZZZZ";
      END dataflow;




                                           XXIX
                                                                                 Ÿœª„…

…5   74LS163 SYNCHRONOUS 4-BIT COUNTER

      LIBRARY ieee;
      USE ieee.std_logic_1164.ALL;
      USE WORK.utility.ALL;

      ENTITY ttl_74ls163_counter IS
         GENERIC (prop_delay : TIME := 18 NS);
         PORT ( clk, clr_bar, Id_bar, enp, ent : IN std_logic;
                    abcd : IN std_logic_vector (3 DOWNTO 0);
                    q_abcd : OUT std_logic_vector (3 DOWNTO 0); rco : OUT
      std_logic );
      END ttl_74ls163_counter;
      ARCHITECTURE behavioral OF ttl_74ls163_counter IS
      BEGIN
         counting : PROCESS (clk)
            VARIABLE internal_count : std_logic_vector (3 DOWNTO 0) := "0000";
         BEGIN
            IF (clk = '1') THEN
                IF (clr_bar = '0') THEN
                    internal_count := "0000";
                ELSIF (Id_bar = '0' ) THEN
                    internal_count := abcd;
                ELSIF (enp = '1' AND ent = '1' ) THEN
                    internal_count := inc_int (internal_count);
                    IF (internal_count = "1111") THEN
                        rco <= '1' AFTER prop_delay;
                    ELSE
                        rco <= '0';
                    END IF;
                END IF;
                q_abcd <= internal_count AFTER prop_delay;
            END IF;
         END PROCESS counting;
      END behavioral;

…6   74LS541 TRANCEIVER

      LIBRARY ieee;
      USE ieee.std_logic_1164.ALL;
      USE WORK.utility.ALL;

      ENTITY ttl_74ls541 IS
        GENERIC (prop_delay : TIME := 10 NS);
        PORT ( g_bar : IN std_logic_vector ( 1 DOWNTO 0);
                  a8 : IN std_logic_vector ( 7 DOWNTO 0);
                  y8 : OUT std_logic_vector ( 7 DOWNTO 0) );
      END ttl_74ls541;
      ARCHITECTURE dataflow OF ttl_74ls541 IS
      BEGIN
        y8 <= a8 AFTER prop_delay WHEN g_bar = "00" ELSE "ZZZZZZZZ";
      END dataflow;




                                         XXX
                                                                               Ÿœª„…

…7   74LS283 4- BIT BINARY FULL ADDER

      LIBRARY ieee;
      USE ieee.std_logic_1164.ALL;
      USE WORK.utility.ALL;

      ENTITY ttl_74Is283 IS
       GENERIC (prop_delay : TIME := 14 NS; prop_delay1 : TIME := 16 NS);
        PORT ( c_in : IN std_logic; c_out : OUT std_logic;
                   a4,b4 : IN std_logic_vector (3 DOWNTO 0 );
                   sum : OUT std_logic_vector (3 DOWNTO 0 ) );
      END ttl_74Is283;
      ARCHITECTURE behavioral OF ttl_74Is283 IS
      BEGIN
        adder : PROCESS (a4,b4,c_in)
            VARIABLE atemp,btemp,ytemp : INTEGER := 0;
            VARIABLE stemp : std_logic_vector (3 DOWNTO 0) := "0000";
        BEGIN
            stdlogicvector_to_int (a4,atemp);
            stdlogicvector_to_int (b4,btemp);
            IF (c_in = '1') THEN
                ytemp := atemp + btemp + 1;
            ELSE
                ytemp := atemp + btemp;
            END IF;
            IF ytemp > 15 THEN
                c_out <= '1' AFTER prop_delay;
            ELSE
                c_out <= '0' AFTER prop_delay;
            END IF;
            int_to_stdlogicvector (ytemp,stemp);
            sum <= stemp AFTER prop_delay1;
        END PROCESS adder;
      END behavioral;



…8   74LS377 OCTAL D-TYPE FILP-FLOPS

      LIBRARY ieee;
      USE ieee.std_logic_1164.ALL;
      USE WORK.utility.ALL;

      ENTITY ttl_74Is377_register IS
        GENERIC (prop_delay : TIME := 17 NS);
        PORT ( clk, g_bar : IN std_logic; d8 : IN std_logic_vector (7 DOWNTO 0);
                  q8 : OUT std_logic_vector ( 7 DOWNTO 0) );
      END ttl_74Is377_register;
      ARCHITECTURE dataflow OF ttl_74Is377_register IS
        SIGNAL GUARD : BOOLEAN;
      BEGIN
        GUARD <= NOT clk'STABLE AND clk = '1' AND (g_bar = '0');
        q8 <= GUARDED d8 AFTER prop_delay;
      END dataflow;




                                         XXXI
                                                                                   Ÿœª„…

…9   74LS299 UNIVERSAL SHIFT-REGISTER

      LIBRARY ieee;
      USE ieee.std_logic_1164.ALL;
      USE WORK.utility.ALL;

      ENTITY ttl_74ls299 IS
        GENERIC (prop_delay : TIME := 27 NS);
        PORT ( clk, clr_bar, lin, rin : IN std_logic;
                    s, g_bar : IN std_logic_vector (1 DOWNTO 0 );
                    qa, qh : OUT std_logic;
                    qq : INOUT std_logic_vector (7 DOWNTO 0 ) );
      END ttl_74ls299;
      ARCHITECTURE behavioral OF ttl_74ls299 IS
        SIGNAL iq : std_logic_vector ( 7 DOWNTO 0);
      BEGIN
        clocking : PROCESS (clk, clr_bar)
        BEGIN
            IF clr_bar = '0' THEN
                iq <= "00000000";                                 -- clear
                ELSIF ((clk'EVENT) AND (clk = '1')) THEN
                    CASE s IS
                        WHEN "01" =>
                           iq <= rin & iq (7 DOWNTO 1 );          -- shift right
                        WHEN "10" =>
                           iq <= iq (6) & iq (5 DOWNTO 0 ) & lin; -- shift left
                        WHEN "11" =>
                           iq <= qq;                              -- load
                        WHEN OTHERS => NULL;                      -- hold
                    END CASE;
            END IF;
        END PROCESS clocking;
        tri_state: PROCESS (iq, g_bar)
        BEGIN
            IF g_bar = "00" THEN
                IF s /= "11" THEN
                    qq <= iq;
                ELSE
                    qq <= "ZZZZZZZZ";
                END IF;
            ELSE
                qq <= "ZZZZZZZZ";
            END IF;
        END PROCESS tri_state;
        qa <= iq(7);
        qh <= iq(0);
      END behavioral;




                                            XXXII
                                                                                Ÿœª„‡




                                       Ÿœª„‡
                PACKAGE STANDARD and STD_LOGIC_1164




Ĝ¦³¡´•œµ 9+'/ šµŠ­¤µ‡¤ ,((( ŗo„ε®œ—Ä®o¤¸ 3$&.$*( ˜n°Åžœ¸ÊĜ¦³ ¨³™¼„
Á„ȝŪoš¸É...\std\standard; ...\std\textio ¨³ ...\ieee\std_logic_1164

--------------------------------------------------------------------
--                                                                --
--                        STANDARD                                --
--                                                                --
--    VHDL standard types, as defined by IEEE Std 1076.           --
--                                                                --
--------------------------------------------------------------------

package Standard is

--   Predefined enumeration types:

type BOOLEAN is (FALSE, TRUE);

type BIT is ('0', '1');

type CHARACTER is      (
      NUL, SOH,        STX,    ETX,   EOT,       ENQ,   ACK,   BEL,
      BS,   HT,        LF,     VT,    FF,        CR,    SO,    SI,
      DLE, DC1,        DC2,    DC3,   DC4,       NAK,   SYN,   ETB,
      CAN, EM,         SUB,    ESC,   FSP,       GSP,   RSP,   USP,

       ' ',    '!',    '"',    '#',   '$',       '%',   '&',   ''',
       '(',    ')',    '*',    '+',   ',',       '-',   '.',   '/',
       '0',    '1',    '2',    '3',   '4',       '5',   '6',   '7',
       '8',    '9',    ':',    ';',   '<',       '=',   '>',   '?',

       '@',    'A',    'B',    'C',   'D',       'E',   'F',   'G',
       'H',    'I',    'J',    'K',   'L',       'M',   'N',   'O',
       'P',    'Q',    'R',    'S',   'T',       'U',   'V',   'W',
       'X',    'Y',    'Z',    '[',   '\',       ']',   '^',   '_',

       '`',    'a',    'b',    'c',   'd',       'e',   'f',   'g',
       'h',    'i',    'j',    'k',   'l',       'm',   'n',   'o',
       'p',    'q',    'r',    's',   't',       'u',   'v',   'w',
       'x',    'y',    'z',    '{',   '|',       '}',   '~',   DEL);




                                             I
                                                                  Ÿœª„‡



type SEVERITY_LEVEL is (NOTE, WARNING, ERROR, FAILURE);

-- Predefined numeric types:

type INTEGER is range -2147483647 to 2147483647;

type REAL is range -1.0E38 to 1.0E38;

-- Predefined type TIME:

type TIME is range INTEGER'LOW to INTEGER'HIGH
            units
            fs;                     -- femtosecond
            ps    = 1000 fs;        -- picosecond
            ns    = 1000 ps;        -- nanosecond
            us    = 1000 ns;        -- microsecond
            ms    = 1000 us;        -- milisecond
            sec   = 1000 ms;        -- second
            min   = 60    sec;      -- minute
            hr    = 60    min;      -- hour
      end units;

--------------------------------------------------------------------
--
--             STANDARD PACKAGE TEXTIO (DECLARATION)              --
--
--------------------------------------------------------------------
package Textio is
--------------------------------------------------------------------
-- Type Definitions for Text I/O

type LINE is access STRING ;            -- a LINE is a pointer to a
STRING value

type TEXT is file of STRING ;           -- a file of variable-length
ASCII records

type SIDE is (RIGHT,LEFT) ;             -- for justifying output data
within fields

subtype WIDTH is NATURAL ;              -- for specifying widths of
output fields

-- Standard Text Files

file INPUT: TEXT is in "STD_INPUT" ;

file OUTPUT: TEXT is out "STD_OUTPUT" ;

-- Input Routines for Standard Types

procedure READLINE(variable F :in TEXT;      L:out LINE) ;

procedure READ(L:inout LINE;    VALUE:out BIT;
      GOOD:out BOOLEAN) ;
procedure READ(L:inout LINE;    VALUE:out BIT) ;

procedure READ(L:inout LINE;    VALUE:out BIT_VECTOR;
      GOOD:out BOOLEAN) ;
procedure READ(L:inout LINE;    VALUE:out BIT_VECTOR) ;




                                   II
                                                                 Ÿœª„‡



procedure READ(L:inout LINE;   VALUE:out BOOLEAN;
      GOOD:out BOOLEAN) ;
procedure READ(L:inout LINE;   VALUE:out BOOLEAN) ;

procedure READ(L:inout LINE;   VALUE:out CHARACTER;
      GOOD:out BOOLEAN) ;
procedure READ(L:inout LINE;   VALUE:out CHARACTER) ;

procedure READ(L:inout LINE;   VALUE:out INTEGER;
      GOOD:out BOOLEAN) ;
procedure READ(L:inout LINE;   VALUE:out INTEGER) ;

-- procedure READ(L:inout LINE;         VALUE:out REAL;
      GOOD:out BOOLEAN) ;
-- procedure READ(L:inout LINE;         VALUE:out REAL) ;

procedure READ(L:inout LINE;   VALUE:out STRING;
      GOOD:out BOOLEAN) ;
procedure READ(L:inout LINE;   VALUE:out STRING) ;

procedure READ(L:inout LINE;   VALUE:out TIME;
      GOOD:out BOOLEAN) ;
procedure READ(L:inout LINE;   VALUE:out TIME) ;

-- Output Routines for Standard Types

procedure WRITELINE(variable F:in TEXT;       L:inout LINE) ;

procedure STD_WRITELINE(L:inout LINE) ;

procedure WRITE(L:inout LINE; VALUE:in BIT;
            JUSTIFIED:in SIDE := RIGHT; FIELD:in WIDTH := 0) ;

procedure WRITE(L:inout LINE; VALUE:in BIT_VECTOR;
            JUSTIFIED:in SIDE := RIGHT; FIELD:in WIDTH := 0) ;

procedure WRITE(L:inout LINE; VALUE:in BOOLEAN;
            JUSTIFIED:in SIDE := RIGHT; FIELD:in WIDTH := 0) ;

procedure WRITE(L:inout LINE; VALUE:in CHARACTER;
            JUSTIFIED:in SIDE := RIGHT; FIELD:in WIDTH := 0) ;

procedure WRITE(L:inout LINE; VALUE:in INTEGER;
            JUSTIFIED:in SIDE := RIGHT; FIELD:in WIDTH := 0) ;

-- procedure WRITE(L:inout LINE;     VALUE:in REAL;
--          JUSTIFIED:in SIDE := RIGHT; FIELD:in WIDTH := 0;
--          DIGITS:in NATURAL := 0);

procedure WRITE(L:inout LINE; VALUE:in STRING;
            JUSTIFIED:in SIDE := RIGHT; FIELD:in WIDTH := 0) ;

procedure WRITE(L:inout LINE; VALUE:in TIME;
             JUSTIFIED:in SIDE := RIGHT; FIELD:in WIDTH := 0;
             UNIT:in TIME := 1 ns);
-- File Position Predicates
function ENDLINE(L:in LINE) return BOOLEAN ;
function ENDFILE(F:in TEXT) return BOOLEAN ;
end Textio ;




                                  III
                                                                 Ÿœª„‡



--------------------------------------------------------------------
--
--                 STANDARD PACKAGE TEXTIO (BODY)                 --
--
--------------------------------------------------------------------
package body Textio is

------------------------------------------------------------------

procedure READA(L:inout LINE; VALUE:out BIT;
      GOOD:out BOOLEAN) ;
procedure READB(L:inout LINE; VALUE:out BIT) ;

procedure READC(L:inout LINE; VALUE:out BIT_VECTOR;
      GOOD:out BOOLEAN) ;
procedure READD(L:inout LINE; VALUE:out BIT_VECTOR) ;

procedure READE(L:inout LINE; VALUE:out BOOLEAN;
      GOOD:out BOOLEAN) ;
procedure READF(L:inout LINE; VALUE:out BOOLEAN) ;

procedure READG(L:inout LINE; VALUE:out CHARACTER;
      GOOD:out BOOLEAN) ;
procedure READH(L:inout LINE; VALUE:out CHARACTER) ;

procedure READI(L:inout LINE; VALUE:out INTEGER;
      GOOD:out BOOLEAN) ;
procedure READJ(L:inout LINE; VALUE:out INTEGER) ;

procedure READM(L:inout LINE; VALUE:out STRING;
      GOOD:out BOOLEAN) ;
procedure READN(L:inout LINE; VALUE:out STRING) ;

procedure READO(L:inout LINE; VALUE:out TIME;
      GOOD:out BOOLEAN) ;
procedure READP(L:inout LINE; VALUE:out TIME) ;

procedure WRITEA(L:inout LINE;      VALUE:in BIT;
            JUSTIFIED:in SIDE := RIGHT; FIELD:in WIDTH := 0) ;

procedure WRITEB(L:inout LINE;      VALUE:in BIT_VECTOR;
            JUSTIFIED:in SIDE := RIGHT; FIELD:in WIDTH := 0) ;

procedure WRITEC(L:inout LINE;      VALUE:in BOOLEAN;
            JUSTIFIED:in SIDE := RIGHT; FIELD:in WIDTH := 0) ;

procedure WRITED(L:inout LINE;      VALUE:in CHARACTER;
            JUSTIFIED:in SIDE := RIGHT; FIELD:in WIDTH := 0) ;

procedure WRITEE(L:inout LINE;      VALUE:in INTEGER;
            JUSTIFIED:in SIDE := RIGHT; FIELD:in WIDTH := 0) ;

procedure WRITEG(L:inout LINE;      VALUE:in STRING;
            JUSTIFIED:in SIDE := RIGHT; FIELD:in WIDTH := 0) ;

procedure WRITEH(L:inout LINE;      VALUE:in TIME;
            JUSTIFIED:in SIDE := RIGHT; FIELD:in WIDTH := 0;
                UNIT:in TIME := 1 ns) ;




                                 IV
                                                              Ÿœª„‡



------------------------------------------------------------------
-- Input Routines for Standard Types
------------------------------------------------------------------
procedure READ(L:inout LINE; VALUE:out BIT;
      GOOD:out BOOLEAN) is
Begin
      READA(L,    VALUE,      GOOD);
end READ;
procedure READ(L:inout LINE; VALUE:out BIT)
      is
Begin
      READB(L,    VALUE) ;
end READ;

procedure READ(L:inout LINE;   VALUE:out BIT_VECTOR;
      GOOD:out BOOLEAN) is
Begin
      READC(L,    VALUE,       GOOD);
end READ;
procedure READ(L:inout LINE;   VALUE:out BIT_VECTOR)
      is
Begin
      READD(L,    VALUE);
end READ;

procedure READ(L:inout LINE;   VALUE:out BOOLEAN;
      GOOD:out BOOLEAN) is
Begin
      READE(L,    VALUE,       GOOD);
end READ;
procedure READ(L:inout LINE;   VALUE:out BOOLEAN)
      is
Begin
      READF(L,    VALUE);
end READ;

procedure READ(L:inout LINE;   VALUE:out CHARACTER;
      GOOD:out BOOLEAN) is
Begin
      READG(L,    VALUE,       GOOD);
end READ;
procedure READ(L:inout LINE;   VALUE:out CHARACTER)
      is
Begin
      READH(L,    VALUE);
end READ;

procedure READ(L:inout LINE; VALUE:out INTEGER;
      GOOD:out BOOLEAN) is
Begin
      READI(L,    VALUE,      GOOD);
end READ;
procedure READ(L:inout LINE; VALUE:out INTEGER)
      is
Begin
      READJ(L,    VALUE);
end READ;
-- procedure READ(L:inout LINE;      VALUE:out REAL;
      GOOD:out BOOLEAN) ;
-- procedure READ(L:inout LINE;      VALUE:out REAL) ;




                                  V
                                                               Ÿœª„‡



procedure READ(L:inout LINE;   VALUE:out STRING;
      GOOD:out BOOLEAN) is
Begin
      READM(L,    VALUE,       GOOD);
end READ;
procedure READ(L:inout LINE;   VALUE:out STRING)
      is
Begin
      READN(L,    VALUE);
end READ;
procedure READ(L:inout LINE;   VALUE:out TIME;
      GOOD:out BOOLEAN) is
Begin
      READO(L,    VALUE,       GOOD);
end READ;
procedure READ(L:inout LINE;   VALUE:out TIME)
      is
Begin
      READP(L,    VALUE);
end READ;

procedure WRITE(L:inout LINE; VALUE:in BIT;
      JUSTIFIED:in SIDE := RIGHT; FIELD:in WIDTH := 0)
      is
Begin
      WRITEA(L,   VALUE,
            JUSTIFIED, FIELD);
end WRITE;
procedure WRITE(L:inout LINE; VALUE:in BIT_VECTOR;
      JUSTIFIED:in SIDE := RIGHT; FIELD:in WIDTH := 0)
      is
Begin
      WRITEB(L,   VALUE,
            JUSTIFIED, FIELD);
end WRITE;

procedure WRITE(L:inout LINE; VALUE:in BOOLEAN;
      JUSTIFIED:in SIDE := RIGHT; FIELD:in WIDTH := 0)
      is
Begin
      WRITEC(L,   VALUE,
            JUSTIFIED, FIELD);
end WRITE;
procedure WRITE(L:inout LINE; VALUE:in CHARACTER;
      JUSTIFIED:in SIDE := RIGHT; FIELD:in WIDTH := 0)
      is
Begin
      WRITED(L,   VALUE,
            JUSTIFIED, FIELD);
end WRITE;
procedure WRITE(L:inout LINE; VALUE:in INTEGER;
      JUSTIFIED:in SIDE := RIGHT; FIELD:in WIDTH := 0)
      is
Begin
      WRITEE(L,   VALUE,
            JUSTIFIED, FIELD);
end WRITE;
-- procedure WRITE(L:inout LINE;     VALUE:in REAL;
--          JUSTIFIED:in SIDE := RIGHT; FIELD:in WIDTH := 0;
--          DIGITS:in NATURAL := 0);




                                  VI
                                                               Ÿœª„‡



procedure WRITE(L:inout LINE; VALUE:in STRING;
      JUSTIFIED:in SIDE := RIGHT; FIELD:in WIDTH := 0)
      is
Begin
      WRITEG(L,   VALUE,
            JUSTIFIED, FIELD);
end WRITE;
procedure WRITE(L:inout LINE; VALUE:in TIME;
      JUSTIFIED:in SIDE := RIGHT; FIELD:in WIDTH := 0;
      UNIT:in TIME := 1 ns)
      is
Begin
      WRITEH(L,   VALUE,
            JUSTIFIED, FIELD,UNIT);
end WRITE;

procedure STD_WRITELINE(L:inout LINE)
      is
Begin
       WRITELINE(OUTPUT,L);
end STD_WRITELINE;

end Textio ;
--------------------------------------------------------------------
--                                                                 --
--           PORTABLE - STD_LOGIC_1164 (DECLARATION)               --
--                                                                 --
-- This package defines the portable constructs that were defined --
-- by IEEE VHDL Model Standards Group.                             --
--                                                                 --
--------------------------------------------------------------------
--------------------------------------------------------------------
--
--
--   Title      : std_logic_1164 multi-value logic system
--   Library    : This package shall be compiled into a library
--              : symbolically named IEEE.
--              :
--   Developers: IEEE model standards group (par 1164)
--   Purpose    : This packages defines a standard for designers
--              : to use in describing the interconnection data
--              : types used in vhdl modeling.
--              :
--   Limitation: The logic system defined in this package may
--              : be insufficient for modeling switched transistors,
--              : since such a requirement is out of the scope of
--              : this effort. Furthermore, mathematics, primitives,
--              : timing standards, etc. are considered orthogonal
--              : issues as it relates to this package and are
--              : therefore beyond the scope of this effort.
--              :
--   Note       : No declarations or definitions shall be included
--              : in, excluded from this package. The "package
--              : declaration" defines the types, subtypes and
--              : declarations of std_logic_1164. The std_logic_1164
--              : package body shall be considered the formal
--              : definition of the semantics of this package. Tool
--              : developers may choose to implement the package
--              :   body in the most efficient manner to them.
--              :




                                 VII
                                                              Ÿœª„‡



--------------------------------------------------------------------
--   modification history :
--------------------------------------------------------------------
-- version | mod. date:|
--   v4.200 | 01/02/92 |
--------------------------------------------------------------------
PACKAGE Std_logic_1164 is
--------------------------------------------------------------------
-- Logic State System (unresolved)
--------------------------------------------------------------------
    TYPE std_ulogic is ( 'U', -- Uninitialized
                        'X', -- Forcing Unknown
                        '0', -- Forcing 0
                        '1', -- Forcing 1
                        'Z', -- High Impedance
                        'W', -- Weak     Unknown
                        'L', -- Weak     0
                        'H', -- Weak     1
                        '-'   -- don't care
                       );


-----------------------------------------------------------------
-- Unconstrained array of std_ulogic for use with the resolution
-- function
-----------------------------------------------------------------
    TYPE std_ulogic_vector IS ARRAY ( NATURAL RANGE <> ) of
      std_ulogic;
-----------------------------------------------------------------
-- Resolution function
-----------------------------------------------------------------
    FUNCTION resolved ( s : std_ulogic_vector ) RETURN std_ulogic;

-----------------------------------------------------------------
-- *** Industry Standard Logic Type ***
-----------------------------------------------------------------
    SUBTYPE std_logic IS resolved std_ulogic;
-----------------------------------------------------------------
-- Unconstrained array of std_logic for use in declaring signal
-- arrays
-----------------------------------------------------------------
    TYPE std_logic_vector IS ARRAY ( NATURAL RANGE <> ) of
      std_logic;
-----------------------------------------------------------------
-- Basic states + Test
-----------------------------------------------------------------
    SUBTYPE X01    is resolved std_ulogic range 'X' to '1';
-- ('X','0','1')
    SUBTYPE X01Z   is resolved std_ulogic range 'X' to 'Z';
-- ('X','0','1','Z')
    SUBTYPE UX01   is resolved std_ulogic range 'U' to '1';
-- ('U','X','0','1')
    SUBTYPE UX01Z is resolved std_ulogic range 'U' to 'Z';
-- ('U','X','0','1','Z')




                                 VIII
                                                              Ÿœª„‡



-----------------------------------------------------------------
-- Overloaded Logical Operators
-----------------------------------------------------------------
    FUNCTION "and" ( l : std_ulogic; r : std_ulogic ) RETURN UX01;
    FUNCTION "nand" ( l : std_ulogic; r : std_ulogic ) RETURN UX01;
    FUNCTION "or"   ( l : std_ulogic; r : std_ulogic ) RETURN UX01;
    FUNCTION "nor" ( l : std_ulogic; r : std_ulogic ) RETURN UX01;
    FUNCTION "xor" ( l : std_ulogic; r : std_ulogic ) RETURN UX01;
-- function "xnor" ( l : std_ulogic; r : std_ulogic ) return ux01;
    FUNCTION "not" ( l : std_ulogic                  ) RETURN UX01;

-----------------------------------------------------------------
-- Vectorized Overloaded Logical Operators
-----------------------------------------------------------------
    FUNCTION "and" ( l, r : std_logic_vector ) RETURN
      std_logic_vector;
    FUNCTION "nand" ( l, r : std_logic_vector ) RETURN
      std_logic_vector;
    FUNCTION "or"   ( l, r : std_logic_vector ) RETURN
      std_logic_vector;
    FUNCTION "nor" ( l, r : std_logic_vector ) RETURN
      std_logic_vector;
    FUNCTION "xor" ( l, r : std_logic_vector ) RETURN
      std_logic_vector;
    FUNCTION "not" ( l     : std_logic_vector ) RETURN
      std_logic_vector;
    FUNCTION "and" ( l, r : std_ulogic_vector ) RETURN
      std_ulogic_vector;
    FUNCTION "nand" ( l, r : std_ulogic_vector ) RETURN
      std_ulogic_vector;
    FUNCTION "or"   ( l, r : std_ulogic_vector ) RETURN
      std_ulogic_vector;
    FUNCTION "nor" ( l, r : std_ulogic_vector ) RETURN
      std_ulogic_vector;
    FUNCTION "xor" ( l, r : std_ulogic_vector ) RETURN
      std_ulogic_vector;
    FUNCTION "not" ( l     : std_ulogic_vector ) RETURN
      std_ulogic_vector;

--------------------------------------------------------------------
-- Note : The declaration and implementation of the "xnor" function
-- is specifically commented until at which time the VHDL language
-- has been officially adopted as containing such a function. At
-- such a point, the following comments may be removed along with
-- this notice without further "official" ballotting of this
-- std_logic_1164 package. It is the intent of this effort to
-- provide such a function once it becomes available in the VHDL
-- standard.
--------------------------------------------------------------------
-- function "xnor" ( l, r : std_logic_vector ) return
--    std_logic_vector;
-- function "xnor" ( l, r : std_ulogic_vector ) return
--    std_ulogic_vector;




                                 IX
                                                              Ÿœª„‡



-------------------------------------------------------------------
-- Conversion Functions
-------------------------------------------------------------------
    FUNCTION To_bit       ( s : std_ulogic;        xmap : BIT :=
                  '0') RETURN BIT;
    FUNCTION To_bitvector ( s : std_logic_vector ; xmap : BIT :=
                  '0') RETURN BIT_VECTOR;
    FUNCTION To_bitvector ( s : std_ulogic_vector; xmap : BIT :=
                  '0') RETURN BIT_VECTOR;
    FUNCTION To_StdULogic       ( b : BIT               )
             RETURN std_ulogic;
    FUNCTION To_StdLogicVector ( b : BIT_VECTOR         )
             RETURN std_logic_vector;
    FUNCTION To_StdLogicVector ( s : std_ulogic_vector )
             RETURN std_logic_vector;
    FUNCTION To_StdULogicVector ( b : BIT_VECTOR        )
             RETURN std_ulogic_vector;
    FUNCTION To_StdULogicVector ( s : std_logic_vector )
             RETURN std_ulogic_vector;

 -------------------------------------------------------------------
 -- strength strippers and type convertors
 -------------------------------------------------------------------

    FUNCTION To_X01 ( s    : std_logic_vector ) RETURN
      std_logic_vector;
    FUNCTION To_X01 ( s    : std_ulogic_vector) RETURN
      std_ulogic_vector;
    FUNCTION To_X01 ( s    : std_ulogic       ) RETURN
      X01;
    FUNCTION To_X01 ( b    : bit_vector       ) RETURN
      std_logic_vector;
    FUNCTION To_X01 ( b    : bit_vector       ) RETURN
      std_ulogic_vector;
    FUNCTION To_X01 ( b    : bit              ) RETURN
      X01;
    FUNCTION To_X01Z ( s   : std_logic_vector ) RETURN
      std_logic_vector;
    FUNCTION To_X01Z ( s   : std_ulogic_vector) RETURN
      std_ulogic_vector;
    FUNCTION To_X01Z ( s   : std_ulogic       ) RETURN
      X01Z;
    FUNCTION To_X01Z ( b   : bit_vector       ) RETURN
      std_logic_vector;
    FUNCTION To_X01Z ( b   : bit_vector       ) RETURN
      std_ulogic_vector;
    FUNCTION To_X01Z ( b   : bit              ) RETURN
      X01Z;
    FUNCTION To_UX01 ( s   : std_logic_vector ) RETURN
      std_logic_vector;
    FUNCTION To_UX01 ( s   : std_ulogic_vector) RETURN
      std_ulogic_vector;
    FUNCTION To_UX01 ( s   : std_ulogic       ) RETURN
      UX01;
    FUNCTION To_UX01 ( b   : bit_vector       ) RETURN
      std_logic_vector;
    FUNCTION To_UX01 ( b   : bit_vector       ) RETURN
      std_ulogic_vector;
    FUNCTION To_UX01 ( b   : bit              ) RETURN
      UX01;




                                   X
                                                              Ÿœª„‡



-------------------------------------------------------------------
-- Edge Detection
-------------------------------------------------------------------
    FUNCTION rising_edge (SIGNAL s : std_ulogic) RETURN boolean;
    FUNCTION falling_edge (SIGNAL s : std_ulogic) RETURN boolean;
-------------------------------------------------------------------
-- object contains an unknown
-------------------------------------------------------------------
    FUNCTION Is_X ( s : std_ulogic_vector ) RETURN BOOLEAN;
    FUNCTION Is_X ( s : std_logic_vector ) RETURN BOOLEAN;
    FUNCTION Is_X ( s : std_ulogic        ) RETURN BOOLEAN;

END Std_logic_1164;
-- Function that returns the current time of simulation:

function NOW return TIME;

-- Predefined numberic subtypes:

subtype NATURAL is INTEGER range 0 to INTEGER'HIGH;

subtype POSITIVE is INTEGER range 1 to INTEGER'HIGH;

-- Predefined array types:

type STRING is array (POSITIVE RANGE <>) of CHARACTER;

type BIT_VECTOR is array (NATURAL range <>) of BIT;

end Standard;


--------------------------------------------------------------------
--                                                                --
--               PORTABLE - STD_LOGIC_1164 (BODY)                 --
--                                                                --
-- This package defines the portable constructs that were defined --
-- by IEEE VHDL Model Standards Group.                            --
--                                                                --
--------------------------------------------------------------------

--------------------------------------------------------------------
--
--   Title     : std_logic_1164 multi-value logic system
--   Library   : This package shall be compiled into a library
--             : symbolically named IEEE.
--             :
--   Developers: IEEE model standards group (par 1164)
--   Purpose   : This packages defines a standard for designers
--             : to use in describing the interconnection data
--             : types used in vhdl modeling.
--             :
--   Limitation: The logic system defined in this package may
--             : be insufficient for modeling switched transistors,
--             : since such a requirement is out of the scope of
--             : this effort. Furthermore, mathematics, primitives,
--             : timing standards, etc. are considered orthogonal
--             : issues as it relates to this package and are
--             : therefore beyond the scope of this effort.
--             :




                                   XI
                                                              Ÿœª„‡



--   Note      : No declarations or definitions shall be included
--             : in, or excluded from this package. The "package
--             : declaration" defines the types, subtypes and
--             : declarations of std_logic_1164. The std_logic_1164
--             : package body shall be considered the formal
--             : definition of the semantics of this package. Tool
--             : developers may choose to implement the package
--             : body in the most efficient manner to them.
--             :
--------------------------------------------------------------------
--   modification history :
--------------------------------------------------------------------
-- version | mod. date:|
--   v4.200 | 01/02/92 |
--------------------------------------------------------------------
--
PACKAGE Std_logic_1164 is
--
--------------------------------------------------------------------
-- Logic State System (unresolved)
--------------------------------------------------------------------
    TYPE std_ulogic is ( 'U', -- Uninitialized
                        'X', -- Forcing Unknown
                        '0', -- Forcing 0
                        '1', -- Forcing 1
                        'Z', -- High Impedance
                        'W', -- Weak     Unknown
                        'L', -- Weak     0
                        'H', -- Weak     1
                        '-'   -- don't care
                       );


-------------------------------------------------------------------
-- Unconstrained array of std_ulogic for use with the resolution
-- function
-------------------------------------------------------------------
    TYPE std_ulogic_vector IS ARRAY ( NATURAL RANGE <> ) of
    std_ulogic;
-------------------------------------------------------------------
-- Resolution function
-------------------------------------------------------------------
    FUNCTION resolved ( s : std_ulogic_vector ) RETURN std_ulogic;
-------------------------------------------------------------------
-- *** Industry Standard Logic Type ***
-------------------------------------------------------------------
    SUBTYPE std_logic IS resolved std_ulogic;
-------------------------------------------------------------------
-- Unconstrained array of std_logic for use in declaring signal
-- arrays
-------------------------------------------------------------------
    TYPE std_logic_vector IS ARRAY ( NATURAL RANGE <> ) of
          std_logic;




                                 XII
                                                              Ÿœª„‡



-------------------------------------------------------------------
-- Basic states + Test
-------------------------------------------------------------------
    SUBTYPE X01    is resolved std_ulogic range 'X' to '1';
-- ('X','0','1')
    SUBTYPE X01Z   is resolved std_ulogic range 'X' to 'Z';
-- ('X','0','1','Z')
    SUBTYPE UX01   is resolved std_ulogic range 'U' to '1';
-- ('U','X','0','1')
    SUBTYPE UX01Z is resolved std_ulogic range 'U' to 'Z';
-- ('U','X','0','1','Z')

-------------------------------------------------------------------
-- Overloaded Logical Operators
-------------------------------------------------------------------
    FUNCTION "and" ( l : std_ulogic; r : std_ulogic ) RETURN UX01;
    FUNCTION "nand" ( l : std_ulogic; r : std_ulogic ) RETURN UX01;
    FUNCTION "or"   ( l : std_ulogic; r : std_ulogic ) RETURN UX01;
    FUNCTION "nor" ( l : std_ulogic; r : std_ulogic ) RETURN UX01;
    FUNCTION "xor" ( l : std_ulogic; r : std_ulogic ) RETURN UX01;
-- function "xnor" ( l : std_ulogic; r : std_ulogic ) return ux01;
    FUNCTION "not" ( l : std_ulogic                  ) RETURN UX01;

-------------------------------------------------------------------
-- Vectorized Overloaded Logical Operators
-------------------------------------------------------------------
    FUNCTION "and" ( l, r : std_logic_vector )        RETURN
      std_logic_vector;
    FUNCTION "nand" ( l, r : std_logic_vector )       RETURN
      std_logic_vector;
    FUNCTION "or"   ( l, r : std_logic_vector )       RETURN
      std_logic_vector;
    FUNCTION "nor" ( l, r : std_logic_vector )        RETURN
      std_logic_vector;
    FUNCTION "xor" ( l, r : std_logic_vector )        RETURN
      std_logic_vector;
    FUNCTION "not" ( l     : std_logic_vector )       RETURN
      std_logic_vector;
    FUNCTION "and" ( l, r : std_ulogic_vector )       RETURN
      std_ulogic_vector;
    FUNCTION "nand" ( l, r : std_ulogic_vector )      RETURN
      std_ulogic_vector;
    FUNCTION "or"   ( l, r : std_ulogic_vector )      RETURN
      std_ulogic_vector;
    FUNCTION "nor" ( l, r : std_ulogic_vector )       RETURN
      std_ulogic_vector;
    FUNCTION "xor" ( l, r : std_ulogic_vector )       RETURN
      std_ulogic_vector;
    FUNCTION "not" ( l     : std_ulogic_vector )      RETURN
      std_ulogic_vector;




                                 XIII
                                                              Ÿœª„‡



-- Note : The declaration and implementation of the "xnor" function
-- is specifically commented until at which time the VHDL language
-- has officially adopted as containing such a function. At such a
-- point, the following comments may be removed along with this
-- notice further "official" ballotting of this std_logic_1164
-- package. It the intent of this effort to provide such a function
-- once it becomes available in the VHDL standard.
--------------------------------------------------------------------
-- function "xnor" ( l, r : std_logic_vector ) return
-- std_logic_vector;
-- function "xnor" ( l, r : std_ulogic_vector ) return
-- std_ulogic_vector;
--------------------------------------------------------------------
-- Conversion Functions
--------------------------------------------------------------------
    FUNCTION To_bit ( s : std_ulogic; xmap : BIT := '0')
            RETURN BIT;
    FUNCTION To_bitvector ( s : std_logic_vector ;
            xmap : BIT := '0') RETURN BIT_VECTOR;
    FUNCTION To_bitvector ( s : std_ulogic_vector;
            xmap : BIT := '0') RETURN BIT_VECTOR;
    FUNCTION To_StdULogic       ( b : BIT                )
            RETURN std_ulogic;
    FUNCTION To_StdLogicVector ( b : BIT_VECTOR          )
            RETURN std_logic_vector;
    FUNCTION To_StdLogicVector ( s : std_ulogic_vector )
            RETURN std_logic_vector;
    FUNCTION To_StdULogicVector ( b : BIT_VECTOR         )
            RETURN std_ulogic_vector;
    FUNCTION To_StdULogicVector ( s : std_logic_vector )
            RETURN std_ulogic_vector;
-------------------------------------------------------------------
-- strength strippers and type convertors
-------------------------------------------------------------------
    FUNCTION To_X01 ( s : std_logic_vector ) RETURN
      std_logic_vector;
    FUNCTION To_X01 ( s : std_ulogic_vector) RETURN
      std_ulogic_vector;
    FUNCTION To_X01 ( s : std_ulogic        ) RETURN
      X01;
    FUNCTION To_X01 ( b : bit_vector        ) RETURN
      std_logic_vector;
    FUNCTION To_X01 ( b : bit_vector        ) RETURN
      std_ulogic_vector;
    FUNCTION To_X01 ( b : bit               ) RETURN
      X01;
    FUNCTION To_X01Z ( s : std_logic_vector ) RETURN
      std_logic_vector;
    FUNCTION To_X01Z ( s : std_ulogic_vector) RETURN
      std_ulogic_vector;
    FUNCTION To_X01Z ( s : std_ulogic       ) RETURN
      X01Z;
    FUNCTION To_X01Z ( b : bit_vector       ) RETURN
      std_logic_vector;
    FUNCTION To_X01Z ( b : bit_vector       ) RETURN
      std_ulogic_vector;
    FUNCTION To_X01Z ( b : bit              ) RETURN
      X01Z;
    FUNCTION To_UX01 ( s : std_logic_vector ) RETURN
      std_logic_vector;




                                 XIV
                                                               Ÿœª„‡



    FUNCTION To_UX01 ( s   : std_ulogic_vector) RETURN
      std_ulogic_vector;
    FUNCTION To_UX01 ( s   : std_ulogic       ) RETURN
      UX01;
    FUNCTION To_UX01 ( b   : bit_vector       ) RETURN
      std_logic_vector;
    FUNCTION To_UX01 ( b   : bit_vector       ) RETURN
      std_ulogic_vector;
    FUNCTION To_UX01 ( b   : bit              ) RETURN UX01;

-------------------------------------------------------------------
-- Edge Detection
-------------------------------------------------------------------
    FUNCTION rising_edge (SIGNAL s : std_ulogic) RETURN boolean;
    FUNCTION falling_edge (SIGNAL s : std_ulogic) RETURN boolean;
-------------------------------------------------------------------
-- object contains an unknown
-------------------------------------------------------------------
    FUNCTION Is_X ( s : std_ulogic_vector ) RETURN BOOLEAN;
    FUNCTION Is_X ( s : std_logic_vector ) RETURN BOOLEAN;
    FUNCTION Is_X ( s : std_ulogic        ) RETURN BOOLEAN;

END Std_logic_1164;
--

PACKAGE BODY Std_logic_1164 is

--------------------------------------------------------------------
-- Local Types
--------------------------------------------------------------------
    TYPE stdlogic_1d    is array (std_ulogic) of std_ulogic;
    TYPE stdlogic_table is array (std_ulogic, std_ulogic) of
      std_ulogic;

--------------------------------------------------------------------
-- Resolution Function
--------------------------------------------------------------------
    CONSTANT resolution_table : stdlogic_table := (
--------------------------------------------------------------------
--        | U     X    0    1    Z    W    L    H    -        |   |
-----------------------------------------------------------
          ( 'U', 'U', 'U', 'U', 'U', 'U', 'U', 'U', 'U' ), -- | U |
          ( 'U', 'X', 'X', 'X', 'X', 'X', 'X', 'X', 'X' ), -- | X |
          ( 'U', 'X', '0', 'X', '0', '0', '0', '0', 'X' ), -- | 0 |
          ( 'U', 'X', 'X', '1', '1', '1', '1', '1', 'X' ), -- | 1 |
          ( 'U', 'X', '0', '1', 'Z', 'W', 'L', 'H', 'X' ), -- | Z |
          ( 'U', 'X', '0', '1', 'W', 'W', 'W', 'W', 'X' ), -- | W |
          ( 'U', 'X', '0', '1', 'L', 'W', 'L', 'W', 'X' ), -- | L |
          ( 'U', 'X', '0', '1', 'H', 'W', 'W', 'H', 'X' ), -- | H |
          ( 'U', 'X', 'X', 'X', 'X', 'X', 'X', 'X', 'X' ) -- | - |
                                                );




                                   XV
                                                                Ÿœª„‡



      FUNCTION resolved ( s : std_ulogic_vector ) RETURN std_ulogic IS
        VARIABLE result : std_ulogic := 'Z'; -- weakest state default
      BEGIN
--   the test for a single driver is essential otherwise the
--   loop would return 'X' for a single driver of '-' and that
--   would conflict with the value of a single driver unresolved
--   signal.
--   aw        IF     (s'LENGTH = 1) THEN RETURN s(s'LOW);
--   aw           ELS
--   Iterate through all inputs
             FOR i IN s'RANGE LOOP
               result := resolution_table (result, s(i));
             END LOOP;
             -- Return the resultant value
             RETURN result;
--   aw END If;
      END resolved;

-------------------------------------------------------------------
-- Tables for Logical Operations
-------------------------------------------------------------------
-- truth table for "and" function
    CONSTANT and_table : stdlogic_table := (
-------------------------------------------------------------------
--     | U     X    0    1    Z    W    L    H    -       |   |
-------------------------------------------------------------------
       ( 'U', 'U', '0', 'U', 'U', 'U', '0', 'U', 'U' ), -- | U |
       ( 'U', 'X', '0', 'X', 'X', 'X', '0', 'X', 'X' ), -- | X |
       ( '0', '0', '0', '0', '0', '0', '0', '0', '0' ), -- | 0 |
       ( 'U', 'X', '0', '1', 'X', 'X', '0', '1', 'X' ), -- | 1 |
       ( 'U', 'X', '0', 'X', 'X', 'X', '0', 'X', 'X' ), -- | Z |
       ( 'U', 'X', '0', 'X', 'X', 'X', '0', 'X', 'X' ), -- | W |
       ( '0', '0', '0', '0', '0', '0', '0', '0', '0' ), -- | L |
       ( 'U', 'X', '0', '1', 'X', 'X', '0', '1', 'X' ), -- | H |
       ( 'U', 'X', '0', 'X', 'X', 'X', '0', 'X', 'X' ) -- | - |
                                          );

-- truth table for "or" function
    CONSTANT or_table : stdlogic_table := (
----------------------------------------------------------------
--        | U     X    0    1    Z    W     L   H    -        |     |
----------------------------------------------------------------
          ( 'U', 'U', 'U', '1', 'U', 'U', 'U', '1', 'U' ), -- | U   |
          ( 'U', 'X', 'X', '1', 'X', 'X', 'X', '1', 'X' ), -- | X   |
          ( 'U', 'X', '0', '1', 'X', 'X', '0', '1', 'X' ), -- | 0   |
          ( '1', '1', '1', '1', '1', '1', '1', '1', '1' ), -- | 1   |
          ( 'U', 'X', 'X', '1', 'X', 'X', 'X', '1', 'X' ), -- | Z   |
          ( 'U', 'X', 'X', '1', 'X', 'X', 'X', '1', 'X' ), -- | W   |
          ( 'U', 'X', '0', '1', 'X', 'X', '0', '1', 'X' ), -- | L   |
          ( '1', '1', '1', '1', '1', '1', '1', '1', '1' ), -- | H   |
                                         );




                                   XVI
                                                               Ÿœª„‡



-- truth table for "xor" function
      CONSTANT xor_table : stdlogic_table := (
-------------------------------------------------------------------
--         | U     X    0    1    Z    W    L    H    -        |    |
-------------------------------------------------------------------
           ( 'U', 'U', 'U', 'U', 'U', 'U', 'U', 'U', 'U' ), -- | U |
           ( 'U', 'X', 'X', 'X', 'X', 'X', 'X', 'X', 'X' ), -- | X |
           ( 'U', 'X', '0', '1', 'X', 'X', '0', '1', 'X' ), -- | 0 |
           ( 'U', 'X', '1', '0', 'X', 'X', '1', '0', 'X' ), -- | 1 |
           ( 'U', 'X', 'X', 'X', 'X', 'X', 'X', 'X', 'X' ), -- | Z |
           ( 'U', 'X', 'X', 'X', 'X', 'X', 'X', 'X', 'X' ), -- | W |
           ( 'U', 'X', '0', '1', 'X', 'X', '0', '1', 'X' ), -- | L |
           ( 'U', 'X', '1', '0', 'X', 'X', '1', '0', 'X' ), -- | H |
           ( 'U', 'X', 'X', 'X', 'X', 'X', 'X', 'X', 'X' ) -- | - |
                                          );

-- truth table for not function
    CONSTANT not_table : stdlogic_1D :=
--------------------------------------------------------------------
--    | U      X   0    1    Z    W     L   H    - |
--------------------------------------------------------------------
      ( 'U', 'X', '1', '0', 'X', 'X', '1', '0', 'X' );
--------------------------------------------------------------------
-- Overloaded Logical Operators ( with optimizing hints )
--------------------------------------------------------------------
    FUNCTION "and" ( l : std_ulogic; r : std_ulogic ) RETURN UX01
      IS
    BEGIN
      RETURN (and_table(L, R));
    END "and";

     FUNCTION "nand" ( l : std_ulogic; r : std_ulogic ) RETURN UX01
       IS
     BEGIN
       RETURN (not_table (and_table(L, R)));
     END "nand";

     FUNCTION "or"   ( l : std_ulogic; r : std_ulogic ) RETURN UX01
       IS
     BEGIN
       RETURN (or_table(L, R));
     END "or";

     FUNCTION "nor" ( l : std_ulogic; r : std_ulogic ) RETURN UX01
       IS
     BEGIN
       RETURN (not_table (or_table(L, R)));
     END "nor";

     FUNCTION "xor" ( l : std_ulogic; r : std_ulogic ) RETURN UX01
       IS
     BEGIN
       RETURN (xor_table(L, R));
     END "xor";

--   function "xnor" ( l : std_ulogic; r : std_ulogic ) return ux01
--     is
--   begin
--        return not_table(xor_table(l, r));
--   end "xnor";




                                  XVII
                                                              Ÿœª„‡



    FUNCTION "not" ( l : std_ulogic ) RETURN UX01 IS
    BEGIN
      RETURN (not_table(L));
    END "not";

--------------------------------------------------------------------
-- Vectorized Overloaded Logical Operators (resolved vectors)
--------------------------------------------------------------------

    FUNCTION "and" ( L,R : std_logic_vector ) RETURN
      std_logic_vector IS
      ALIAS LV : std_logic_vector ( 1 to L'length ) IS L;
      ALIAS RV : std_logic_vector ( 1 to R'length ) IS R;
      VARIABLE result : std_logic_vector ( 1 to L'length );
    begin
      if ( L'length /= R'length ) then
           assert false
           report
"Arguments of overloaded 'and' operator are not of the same length"
           severity FAILURE;
      else
           for i in result'range loop
             result(i) := and_table (LV(i), RV(i));
           end loop;
      end if;
      return result;
    end "and";

-----------------------------------------------------------------
    FUNCTION "nand" ( L,R : std_logic_vector ) RETURN
      std_logic_vector IS
      ALIAS LV : std_logic_vector ( 1 to L'length ) IS L;
      ALIAS RV : std_logic_vector ( 1 to R'length ) IS R;
      VARIABLE result : std_logic_vector ( 1 to L'length );
    begin
      if ( L'length /= R'length ) then
           assert false
           report
"Arguments of overloaded 'nand' operator are not of the same length"
           severity FAILURE;
      else
           for i in result'range loop
             result(i) := not_table(and_table (LV(i), RV(i)));
           end loop;
      end if;
      return result;
    end "nand";

-----------------------------------------------------------------




                                XVIII
                                                               Ÿœª„‡



    FUNCTION "or" ( L,R : std_logic_vector ) RETURN
      std_logic_vector IS
      ALIAS LV : std_logic_vector ( 1 to L'length ) IS L;
      ALIAS RV : std_logic_vector ( 1 to R'length ) IS R;
      VARIABLE result : std_logic_vector ( 1 to L'length );
    begin
      if ( L'length /= R'length ) then
           assert false
           report "Arguments of overloaded 'or' operator are not of
the same length"
           severity FAILURE;
      else
           for i in result'range loop
             result(i) := or_table (LV(i), RV(i));
           end loop;
      end if;
      return result;
    end "or";

-----------------------------------------------------------------
    FUNCTION "nor" ( L,R : std_logic_vector ) RETURN
      std_logic_vector IS
      ALIAS LV : std_logic_vector ( 1 to L'length ) IS L;
      ALIAS RV : std_logic_vector ( 1 to R'length ) IS R;
      VARIABLE result : std_logic_vector ( 1 to L'length );
    begin
      if ( L'length /= R'length ) then
           assert false
           report
"Arguments of overloaded 'nor' operator are not of the same length"
           severity FAILURE;
      else
           for i in result'range loop
             result(i) := not_table(or_table (LV(i), RV(i)));
           end loop;
      end if;
      return result;
    end "nor";

-----------------------------------------------------------------
    FUNCTION "xor" ( L,R : std_logic_vector ) RETURN
      std_logic_vector IS
      ALIAS LV : std_logic_vector ( 1 to L'length ) IS L;
      ALIAS RV : std_logic_vector ( 1 to R'length ) IS R;
      VARIABLE result : std_logic_vector ( 1 to L'length );
    begin
      if ( L'length /= R'length ) then
           assert false
           report
"Arguments of overloaded 'xor' operator are not of the same length"
           severity FAILURE;
      else
           for i in result'range loop
             result(i) := xor_table (LV(i), RV(i));
           end loop;
      end if;
      return result;
    end "xor";

-----------------------------------------------------------------




                                 XIX
                                                              Ÿœª„‡



    FUNCTION "not" ( L : std_logic_vector ) RETURN std_logic_vector
      IS
      ALIAS LV : std_logic_vector ( 1 to L'length ) IS L;
      VARIABLE result : std_logic_vector ( 1 to L'length ) :=
      (Others => 'X');
    begin
      for i in result'range loop
          result(i) := not_table(LV(i));
      end loop;
      return result;
    end "not";

-----------------------------------------------------------------
-- Vectorized Overloaded Logical Operators (unresolved vectors)
-----------------------------------------------------------------

    FUNCTION "and" ( L,R : std_ulogic_vector ) RETURN
      std_ulogic_vector IS
      ALIAS LV : std_ulogic_vector ( 1 to L'length ) IS L;
      ALIAS RV : std_ulogic_vector ( 1 to R'length ) IS R;
      VARIABLE result : std_ulogic_vector ( 1 to L'length );
    begin
      if ( L'length /= R'length ) then
           assert false
           report
"Arguments of overloaded 'and' operator are not of the same length"
           severity FAILURE;
      else
           for i in result'range loop
             result(i) := and_table (LV(i), RV(i));
           end loop;
      end if;
      return result;
    end "and";

-----------------------------------------------------------------
    FUNCTION "nand" ( L,R : std_ulogic_vector ) RETURN
      std_ulogic_vector IS
      ALIAS LV : std_ulogic_vector ( 1 to L'length ) IS L;
      ALIAS RV : std_ulogic_vector ( 1 to R'length ) IS R;
      VARIABLE result : std_ulogic_vector ( 1 to L'length );
    begin
      if ( L'length /= R'length ) then
           assert false
           report
"Arguments of overloaded 'nand' operator are not of the same length"
           severity FAILURE;
      else
           for i in result'range loop
             result(i) := not_table(and_table (LV(i), RV(i)));
           end loop;
      end if;
      return result;
    end "nand";

-----------------------------------------------------------------




                                 XX
                                                              Ÿœª„‡



    FUNCTION "or" ( L,R : std_ulogic_vector ) RETURN
      std_ulogic_vector IS
      ALIAS LV : std_ulogic_vector ( 1 to L'length ) IS L;
      ALIAS RV : std_ulogic_vector ( 1 to R'length ) IS R;
      VARIABLE result : std_ulogic_vector ( 1 to L'length );
    begin
      if ( L'length /= R'length ) then
           assert false
           report
"Arguments of overloaded 'or' operator are not of the same length"
           severity FAILURE;
      else
           for i in result'range loop
             result(i) := or_table (LV(i), RV(i));
           end loop;
      end if;
      return result;
    end "or";

-----------------------------------------------------------------
    FUNCTION "nor" ( L,R : std_ulogic_vector ) RETURN
      std_ulogic_vector IS
      ALIAS LV : std_ulogic_vector ( 1 to L'length ) IS L;
      ALIAS RV : std_ulogic_vector ( 1 to R'length ) IS R;
      VARIABLE result : std_ulogic_vector ( 1 to L'length );
    begin
      if ( L'length /= R'length ) then
           assert false
           report
"Arguments of overloaded 'nor' operator are not of the same length"
           severity FAILURE;
      else
           for i in result'range loop
             result(i) := not_table(or_table (LV(i), RV(i)));
           end loop;
      end if;
      return result;
    end "nor";
-----------------------------------------------------------------
    FUNCTION "xor" ( L,R : std_ulogic_vector ) RETURN
      std_ulogic_vector IS
      ALIAS LV : std_ulogic_vector ( 1 to L'length ) IS L;
      ALIAS RV : std_ulogic_vector ( 1 to R'length ) IS R;
      VARIABLE result : std_ulogic_vector ( 1 to L'length );
    begin
      if ( L'length /= R'length ) then
           assert false
           report
"Arguments of overloaded 'xor' operator are not of the same length"
           severity FAILURE;
      else
           for i in result'range loop
             result(i) := xor_table (LV(i), RV(i));
           end loop;
      end if;
      return result;
    end "xor";
-----------------------------------------------------------------




                                 XXI
                                                              Ÿœª„‡



    FUNCTION "not" ( L : std_ulogic_vector ) RETURN
      std_ulogic_vector IS
      ALIAS LV : std_ulogic_vector ( 1 to L'length ) IS L;
      VARIABLE result : std_ulogic_vector ( 1 to L'length ) :=
      (Others => 'X');
    begin
      for i in result'range loop
          result(i) := not_table(LV(i));
      end loop;
      return result;
    end "not";
-----------------------------------------------------------------
-- Conversion Tables
-----------------------------------------------------------------
    TYPE logic_x01_table is array (std_ulogic'low to
      std_ulogic'high) of X01;
    TYPE logic_x01z_table is array (std_ulogic'low to
      std_ulogic'high) of X01Z;
    TYPE logic_ux01_table is array (std_ulogic'low to
      std_ulogic'high) of UX01;

-----------------------------------------------------------------
-- table name : cvt_to_x01
--
-- parameters :
--         in : std_ulogic -- some logic value
-- returns    : x01          -- state value of logic value
-- purpose    : to convert state-strength to state only
--
-- example    : if (cvt_to_x01 (input_signal) = '1' ) then ...
--
-----------------------------------------------------------------
    CONSTANT cvt_to_X01 : logic_x01_table := (
                      'X', -- 'U'
                      'X', -- 'X'
                      '0', -- '0'
                      '1', -- '1'
                      'X', -- 'Z'
                      'X', -- 'W'
                      '0', -- 'L'
                      '1', -- 'H'
                      'X'   -- '-'
                                           );

-----------------------------------------------------------------
-- table name : cvt_to_x01z
--
-- parameters :
--         in : std_ulogic -- some logic value
-- returns    : x01z         -- state value of logic value
-- purpose    : to convert state-strength to state only
--
-- example    : if (cvt_to_x01z (input_signal) = '1' ) then ...
--
-----------------------------------------------------------------




                                 XXII
                                                              Ÿœª„‡



    CONSTANT cvt_to_x01z : logic_x01z_table := (
                        'X', -- 'U'
                        'X', -- 'X'
                        '0', -- '0'
                        '1', -- '1'
                        'Z', -- 'Z'
                        'X', -- 'W'
                        '0', -- 'L'
                        '1', -- 'H'
                        'X'  -- '-'
                                                 );
-----------------------------------------------------------------
-- table name : cvt_to_ux01
--
-- parameters :
--         in : std_ulogic -- some logic value
-- returns     : ux01         -- state value of logic value
-- purpose     : to convert state-strength to state only
--
-- example     : if (cvt_to_ux01 (input_signal) = '1' ) then ...
--
-----------------------------------------------------------------
    CONSTANT cvt_to_ux01 : logic_ux01_table := (
                        'U', -- 'U'
                        'X', -- 'X'
                        '0', -- '0'
                        '1', -- '1'
                        'X', -- 'Z'
                        'X', -- 'W'
                        '0', -- 'L'
                        '1', -- 'H'
                        'X'  -- '-'
                                                 );
--------------------------------------------------------------------
-- Conversion Functions
--------------------------------------------------------------------
    FUNCTION To_bit ( s : std_ulogic;         xmap : BIT := '0')
              RETURN BIT IS
    BEGIN
             CASE s IS
                 WHEN '0' | 'L' => RETURN ('0');
                 WHEN '1' | 'H' => RETURN ('1');
                 WHEN OTHERS => RETURN xmap;
             END CASE;
    END;
--------------------------------------------------------------------
    FUNCTION To_bitvector ( s : std_logic_vector ;
      xmap : BIT := '0') RETURN BIT_VECTOR IS
         ALIAS sv : std_logic_vector ( s'LENGTH-1 DOWNTO 0 ) IS s;
         VARIABLE result : BIT_VECTOR ( s'LENGTH-1 DOWNTO 0 );
    BEGIN
         FOR i IN result'RANGE LOOP
             CASE sv(i) IS
                 WHEN '0' | 'L' => result(i) := '0';
                 WHEN '1' | 'H' => result(i) := '1';
                 WHEN OTHERS => result(i) := xmap;
             END CASE;
         END LOOP;
         RETURN result;
    END;




                                XXIII
                                                              Ÿœª„‡



--------------------------------------------------------------------
    FUNCTION To_bitvector ( s : std_ulogic_vector;
      xmap : BIT := '0') RETURN BIT_VECTOR IS
         ALIAS sv : std_ulogic_vector ( s'LENGTH-1 DOWNTO 0 ) IS s;
         VARIABLE result : BIT_VECTOR ( s'LENGTH-1 DOWNTO 0 );
    BEGIN
         FOR i IN result'RANGE LOOP
             CASE sv(i) IS
                 WHEN '0' | 'L' => result(i) := '0';
                 WHEN '1' | 'H' => result(i) := '1';
                 WHEN OTHERS => result(i) := xmap;
             END CASE;
         END LOOP;
         RETURN result;
    END;
--------------------------------------------------------------------
    FUNCTION To_StdULogic        ( b : BIT               )
              RETURN std_ulogic IS
    BEGIN
         CASE b IS
             WHEN '0' => RETURN '0';
             WHEN '1' => RETURN '1';
         END CASE;
    END;
--------------------------------------------------------------------
    FUNCTION To_StdLogicVector ( b : BIT_VECTOR          )
              RETURN std_logic_vector IS
         ALIAS bv : BIT_VECTOR ( b'LENGTH-1 DOWNTO 0 ) IS b;
         VARIABLE result : std_logic_vector ( b'LENGTH-1 DOWNTO 0 );
    BEGIN
         FOR i IN result'RANGE LOOP
             CASE bv(i) IS
                 WHEN '0' => result(i) := '0';
                 WHEN '1' => result(i) := '1';
             END CASE;
         END LOOP;
         RETURN result;
    END;
--------------------------------------------------------------------
    FUNCTION To_StdLogicVector ( s : std_ulogic_vector )
              RETURN std_logic_vector IS
         ALIAS sv : std_ulogic_vector ( s'LENGTH-1 DOWNTO 0 ) IS s;
         VARIABLE result : std_logic_vector ( s'LENGTH-1 DOWNTO 0 );
    BEGIN
         FOR i IN result'RANGE LOOP
             result(i) := sv(i);
         END LOOP;
         RETURN result;
    END;
--------------------------------------------------------------------




                                XXIV
                                                               Ÿœª„‡



    FUNCTION To_StdULogicVector ( b : BIT_VECTOR         )
          RETURN std_ulogic_vector IS
         ALIAS bv : BIT_VECTOR ( b'LENGTH-1 DOWNTO 0 ) IS b;
         VARIABLE result : std_ulogic_vector ( b'LENGTH-1 DOWNTO 0 );
    BEGIN
         FOR i IN result'RANGE LOOP
             CASE bv(i) IS
                 WHEN '0' => result(i) := '0';
                 WHEN '1' => result(i) := '1';
             END CASE;
         END LOOP;
         RETURN result;
    END;
--------------------------------------------------------------------
    FUNCTION To_StdULogicVector ( s : std_logic_vector )
              RETURN std_ulogic_vector IS
         ALIAS sv : std_logic_vector ( s'LENGTH-1 DOWNTO 0 ) IS s;
         VARIABLE result : std_ulogic_vector ( s'LENGTH-1 DOWNTO 0 );
    BEGIN
         FOR i IN result'RANGE LOOP
             result(i) := sv(i);
         END LOOP;
         RETURN result;
    END;

-------------------------------------------------------------------
-- strength strippers and type convertors
-------------------------------------------------------------------
-- to_x01
-------------------------------------------------------------------
    FUNCTION To_X01 ( s : std_logic_vector ) RETURN
      std_logic_vector IS
      ALIAS SV : std_logic_vector ( 1 to s'length ) IS s;
      VARIABLE result : std_logic_vector ( 1 to s'length );
    BEGIN
      for i in result'range loop
          result(i) := cvt_to_x01 (SV(i));
      end loop;
      return result;
    END;

    FUNCTION To_X01 ( s : std_ulogic_vector ) RETURN
      std_ulogic_vector IS
      ALIAS SV : std_ulogic_vector ( 1 to s'length ) IS s;
      VARIABLE result : std_ulogic_vector ( 1 to s'length );
    BEGIN
      for i in result'range loop
          result(i) := cvt_to_x01 (SV(i));
      end loop;
      return result;
    END;

    FUNCTION To_X01 ( s : std_ulogic ) RETURN X01 IS
    BEGIN
      return (cvt_to_x01(s));
    END;




                                 XXV
                                                               Ÿœª„‡



   FUNCTION To_X01 ( b : bit_vector ) RETURN std_logic_vector IS
      ALIAS BV : bit_vector ( 1 to b'length ) IS b;
      VARIABLE result : std_logic_vector ( 1 to b'length );
    BEGIN
      for i in result'range loop
          case BV(i) is
            when '0' => result(i) := '0';
            when '1' => result(i) := '1';
          end case;
      end loop;
      return result;
    END;

    FUNCTION To_X01 ( b : bit_vector ) RETURN std_ulogic_vector IS
      ALIAS BV : bit_vector ( 1 to b'length ) IS b;
      VARIABLE result : std_ulogic_vector ( 1 to b'length );
    BEGIN
      for i in result'range loop
          case BV(i) is
            when '0' => result(i) := '0';
            when '1' => result(i) := '1';
          end case;
      end loop;
      return result;
    END;

    FUNCTION To_X01 ( b : bit ) RETURN X01 IS
    BEGIN
      case b is
          when '0' => return ('0');
          when '1' => return ('1');
      end case;
    END;

--------------------------------------------------------------------
-- to_x01z
--------------------------------------------------------------------

    FUNCTION To_X01Z ( s : std_logic_vector ) RETURN
      std_logic_vector IS
      ALIAS SV : std_logic_vector ( 1 to s'length ) IS s;
      VARIABLE result : std_logic_vector ( 1 to s'length );
    BEGIN
      for i in result'range loop
          result(i) := cvt_to_x01z (SV(i));
      end loop;
      return result;
    END;

    FUNCTION To_X01Z ( s : std_ulogic_vector ) RETURN
      std_ulogic_vector IS
      ALIAS SV : std_ulogic_vector ( 1 to s'length ) IS s;
      VARIABLE result : std_ulogic_vector ( 1 to s'length );
    BEGIN
      for i in result'range loop
          result(i) := cvt_to_x01z (SV(i));
      end loop;
      return result;
    END;




                                XXVI
                                                              Ÿœª„‡



    FUNCTION To_X01Z ( s : std_ulogic ) RETURN X01Z IS
    BEGIN
      return (cvt_to_x01z(s));
    END;

    FUNCTION To_X01Z ( b : bit_vector ) RETURN std_logic_vector IS
      ALIAS BV : bit_vector ( 1 to b'length ) IS b;
      VARIABLE result : std_logic_vector ( 1 to b'length );
    BEGIN
      for i in result'range loop
          case BV(i) is
            when '0' => result(i) := '0';
            when '1' => result(i) := '1';
          end case;
      end loop;
      return result;
    END;

    FUNCTION To_X01Z ( b : bit_vector ) RETURN std_ulogic_vector IS
      ALIAS BV : bit_vector ( 1 to b'length ) IS b;
      VARIABLE result : std_ulogic_vector ( 1 to b'length );
    BEGIN
      for i in result'range loop
          case BV(i) is
            when '0' => result(i) := '0';
            when '1' => result(i) := '1';
          end case;
      end loop;
      return result;
    END;

    FUNCTION To_X01Z ( b : bit ) RETURN X01Z IS
    BEGIN
      case b is
          when '0' => return ('0');
          when '1' => return ('1');
      end case;
    END;

--------------------------------------------------------------------
-- to_ux01
--------------------------------------------------------------------

    FUNCTION To_UX01 ( s : std_logic_vector ) RETURN
      std_logic_vector IS
      ALIAS SV : std_logic_vector ( 1 to s'length ) IS s;
      VARIABLE result : std_logic_vector ( 1 to s'length );
    BEGIN
      for i in result'range loop
          result(i) := cvt_to_ux01 (SV(i));
      end loop;
      return result;
    END;




                                XXVII
                                                           Ÿœª„‡



FUNCTION To_UX01 ( s : std_ulogic_vector ) RETURN
  std_ulogic_vector IS
  ALIAS SV : std_ulogic_vector ( 1 to s'length ) IS s;
  VARIABLE result : std_ulogic_vector ( 1 to s'length );
BEGIN
  for i in result'range loop
      result(i) := cvt_to_ux01 (SV(i));
  end loop;
  return result;
END;

FUNCTION To_UX01 ( s : std_ulogic ) RETURN UX01 IS
BEGIN
  return (cvt_to_ux01(s));
END;

FUNCTION To_UX01 ( b : BIT_VECTOR ) RETURN std_logic_vector IS
     ALIAS bv : BIT_VECTOR ( 1 TO b'LENGTH ) IS b;
     VARIABLE result : std_logic_vector ( 1 TO b'LENGTH );
BEGIN
     FOR i IN result'RANGE LOOP
         CASE bv(i) IS
             WHEN '0' => result(i) := '0';
             WHEN '1' => result(i) := '1';
         END CASE;
     END LOOP;
     RETURN result;
END;

FUNCTION To_UX01 ( b : BIT_VECTOR ) RETURN std_ulogic_vector
IS
     ALIAS bv : BIT_VECTOR ( 1 TO b'LENGTH ) IS b;
     VARIABLE result : std_ulogic_vector ( 1 TO b'LENGTH );
BEGIN
     FOR i IN result'RANGE LOOP
         CASE bv(i) IS
             WHEN '0' => result(i) := '0';
             WHEN '1' => result(i) := '1';
         END CASE;
     END LOOP;
     RETURN result;
END;

FUNCTION To_UX01 ( b : BIT ) RETURN    UX01 IS
BEGIN
        CASE b IS
            WHEN '0' => RETURN('0');
            WHEN '1' => RETURN('1');
        END CASE;
END;




                            XXVIII
                                                                 Ÿœª„‡



--------------------------------------------------------------------
-- Edge Detection
--------------------------------------------------------------------
    Function rising_edge (SIGNAL s : std_ulogic) RETURN boolean is
    begin
      return (s'event and (To_X01(s) = '1') and
                       (To_X01(s'last_value) = '0'));
    end;

    Function falling_edge (SIGNAL s : std_ulogic) RETURN boolean is
    begin
      return (s'event and (To_X01(s) = '0') and
                       (To_X01(s'last_value) = '1'));
    end;

--------------------------------------------------------------------
-- object contains an unknown
--------------------------------------------------------------------
    FUNCTION Is_X ( s : std_ulogic_vector ) RETURN BOOLEAN IS
    BEGIN
         FOR i IN s'RANGE LOOP
             CASE s(i) IS
                 WHEN 'U' | 'X' | 'Z' | 'W' | '-' => RETURN TRUE;
                 WHEN OTHERS => NULL;
             END CASE;
         END LOOP;
         RETURN FALSE;
    END;

    FUNCTION Is_X ( s : std_logic_vector ) RETURN BOOLEAN IS
    BEGIN
         FOR i IN s'RANGE LOOP
             CASE s(i) IS
                 WHEN 'U' | 'X' | 'Z' | 'W' | '-' => RETURN TRUE;
                 WHEN OTHERS => NULL;
             END CASE;
         END LOOP;
         RETURN FALSE;
    END;

    FUNCTION Is_X ( s : std_ulogic         ) RETURN BOOLEAN IS
    BEGIN
         CASE s IS
             WHEN 'U' | 'X' | 'Z' | 'W' | '-' => RETURN TRUE;
             WHEN OTHERS => NULL;
         END CASE;
         RETURN FALSE;
    END;

END Std_logic_1164;




                                 XXIX
                                        Ÿœª„Š
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ABS                     DISCONNECT            LABEL            PACKAGE              UNITS
ACCESS                  DOWNTO                LIBRARY          PORT              UNTIL
AFTER                                         LINKAGE          PROCEDURE            USE
ALIAS                ELSE                 LOOP           PROCESS
ALL                     ELSIF                                                    VARIABLE
AND                     END                   MAP              RANGE
ARCHITECTURE            ENTITY                MOD              RECORD               WAIT
ARRAY                   EXIT                                   REGISTER             WHEN
ASSERT                                        NAND             REM                  WHILE
ATTRIBUTE               FILE                 NEW               REPORT               WITH
                        FOR                   NEXT             RETURN
BEGIN                   FUNCTION              NOR                                   XOR
BLOCK                                         NOT              SELECT
BODY                 GENERATE             NULL              SEVERITY
BUFFER                  GENERIC                                SIGNAL
BUS                     GUARDED              OF             SUBTYPE
                                              ON
CASE                    IF                    OPEN             THEN
COMPONENT               IN                    OR               TO
CONFUGURATION           INOUT                OTHERS            TRANSPORT
CONSTANT                IS                    OUT              TYPE




                                                  LXII
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  1) Access to Driving Values
         VHDL' 87:
           • Concurrent statements do not have access to their driving values
           • Process can use variables to remember driving values
           • Concurrent signal assignments have no convenient way
         VHDL' 93:
           • 'Driving_Value returns current driving value of prefix signal
           • 'Driving returns Boolean indicating whether 'Driving_Value will succeed
           • No access to other concurrent statements' driving values

  2) Deferred Interface Object Mapping
         VHDL' 87:
           • Generics could be bound with component instance
           • Or with configuration binding indication
           • Not with both
           • Instance's unbound ports cannot be bound during configuration
         VHDL' 93:
           • Generic can bound with component instance
           • Or with configuration binding indication
           • Configuration binding indication may override instance's value
           • Instance's unbound port may be bound during configuration




                                                   I
                                                                                   Ÿœª„‹



3) Direct Instantiation
      VHDL' 87:
        • Two-step binding
              − Must instantiate component declaration
              − Then bind design entity to instance
        • Useful, especially for top-down design, design partition, and
            reconfiguration
        • Can be cumbersome
      VHDL' 93:
        • Two-step approach may still be used
        • Or may directly instantiate
              − Design entity
              − Configuration declaration
        • No reconfiguration then possible

4) Extended Character Set
      VHDL' 87:
        • ISO 646-1983 (7-bit) character set
        • Inadequate outside of U.S.
      VHDL' 93:
        • ISO 8859-1 (8-bit) character set
        • Adequate for users employing roman alphabets

5) Extended Identifiers
      VHDL' 87:
        • Identifiers must contain only letters, digits and underscores
        • Begin with a letter
        • Not end and underscore or contain consecutive underscores
        • Identifiers differing only in the case of their letter are equivalent
        • Cannot be used if reserved by VHDL
      VHDL' 93:
        • Basic identifiers unchanged
        • Extended identifiers can contain any printing characters, in any order
        • Surrounded by backslashes (\), embedded backslashes doubled
        • Case sensitive
        • Not equivalent to any basic identifier or reserved word

6) Foreign Language Interface
      VHDL' 87:
        • Subprogram bodies did not have to be implemented in VHDL
        • Only a note in the LRM
        • What about architecture?
      VHDL' 93:
        • Std.Standard.FOREIGN
        • Can decorate any architecture or subprogram name
        • Architecture or subprogram is not elaborated
        • Attribute value tells implementation what to do
        • Interface object types, modes, etc. of foreign bodies may be restricted by
            implementation
        • Not portable!




                                            II
                                                                                    Ÿœª„‹



7) Generalized Aliasing
     VHDL' 87:
       • Only objects may have aliases
     VHDL' 93:
       • Anything with a name (except labels and loop and generate indices)
           may be aliased
       • Subprogram aliases may take a signature
       • Aliasing an enumaration type creates implicit aliases for all enumaration
           values and implicitly defined operators for the type
       • Can be used to build packages out of other packages:

              LIBRARY IEEE, project;
              PACKAGE my_pack IS
               ALIAS my_bit IS IEEE.std_logic_1164.std_logic;
               ALIAS "+" [MVL, MVL RETURN MVL] IS
                  project.my_arith."+"[MVL, MVL RETURN MVL];
              END PACKAGE my_pack;

8) Groups
     VHDL' 87:
       • No way to express, annotate relationships
       • E.g., regions of code, between ports
     VHDL' 93:
       • Groups: named relationships between names
       • Groups may be attributed
       • Every statement may be labelled; regions of code expressible as groups
       • A group may relate two ports; pin-to-pin timing may be expressed

     GROUP pin2pin IS (SIGNAL, SIGNAL);                   -- a group template declaration
     GROUP clk2q: pin2pin (clk, q);                       -- a group declaration

     ATTRIBUTE timing; DELAY_LENGTH;
     ATTRIBUTE timing of clk2q: GROUP IS 12 NS;           -- an attribute specification

     q <= GUARDED d after clk2q'timing;                   -- use of attribute


9) Hierarchical Pathnames
     VHDL' 87:
       • No standard way of expressing hierarchical paths
       • E.g., assertions, error messages, tool navigation
     VHDL' 93:
       • 'SIMPLE_NAME: a string representation of the name of the prefix
       • 'PATH_NAME: a string describing the hierarchical path from the root of
           the design hierarchy to the prefix, including the design entity names
       • Values may not be unique
       • If the prefix is an alias, for these attributes only, the attribute applies to
           the alias




                                          III
                                                                             Ÿœª„‹



10) Impure Functions
     VHDL' 87:
       • Functions are pure
       • Same arguments, same return value
       • Allow optimization across function calls
       • Consequently, no access to gobal signals or variables
       • Unfortunately, Std.Standard.NOW not pure
     VHDL' 93:
       • Introduces impure functions
       • Can access gobal signals and variables
       • Std.Standard.NOW now impure
       • VHDL' 87 functions are pure
       • Keyword pure may also be used for emphasis

11) "No Change" Assignment
     VHDL' 87:
       • Conditional signal assignments require terminal, unconditional
           waveform
       • Selected signal assignment require a waveform in every selected
           waveform
       → Every time a concurrent signal assignment executes, it must assign to
           its target
       • Can assign the target's effective value
       • Effective value ≠ Driving value!
     VHDL' 93:
       • Conditional signal assignments no longer require unconditional
           waveform
       • All concurrent signal assignments may assign unaffected
       → Concurrent assignment needn't assign to target

12) Port Driven With Expressions
     VHDL' 87:
       • Only actual signals may be associated with ports
       • Constant driving values must be assigned to declared signal, then
           declared signal associated with ports
     VHDL' 93:
       • Expressions may be associated with ports of mode IN
       • Supplies constant driving value port
       • No events ever occur on port

13) Postponed Processes
     VHDL' 87:
       • Processes and concurrent statements access signals' present values
       • Cannot determine if the value is stable at the current simulated time
     VHDL' 93:
       • Processes and concurrent statements may be POSTPONED
       • Postponed processes execute just before time changes
       • Stable values of signal are accessed
       • May not cause delta cycles
       • Non-postponed processes act as before




                                        IV
                                                                             Ÿœª„‹



14) Pulse Rejection
     VHDL' 87:
       • Inertial delay ≡ propagation delay
               s <= '1' AFTER 12 NS;
       • Two signals must be used to model inertial delay < propagation delay
       • temp <= TRANSPORT '1' AFTER 7 NS;
               s <= temp AFTER 5 NS;
     VHDL' 93:
       • 0 ≤ inertial delay ≤ propagation delay
               s <= REJECT 5 NS INERTIAL '1' AFTER 12 NS;
             − Propagation delay = 12 NS
             − Inertial delay = 5 NS

15) Regularized Syntax
     VHDL' 87:
       • Three rules for bracketing keywords:
             − Design units, subprograms:       END [simple_name];
             − All other statements:            END keyword [simple_name];
             − Records:                         END RECORD;
             − ENTITY identifier IS ...
             − COMPONENT identifier             -- no IS permitted!
     VHDL' 93:
       • One rule may be used for all:          END keyword [simple_name];
       • COMPONENT identifier [IS]
       • Entirely upward compatible!

16) Report Statement
     VHDL' 87:
       • When assertion violation triggers actions, IF statement and
           "ASSERT FALSE ...;" must be used
       • "ASSERT FALSE ...;" may also be used to generate messages
             − Dose not provide good documentation
     VHDL' 93:
       • Adds report statement:
             − Has report clause
             − Has severity clause (defaults to "NOTE")

17) Revamped File I/O
     VHDL' 87:
       • File objects are special variables
       • Can be read from, or written to, but not both
       • Opened when file declaration is elaborated
       • Closed when file declaration is "de-elaborated"
       • External formats incompletely specified
       • Files are pipes
     VHDL' 93:
       • Files are a fourth class of object
       • Can be opened and closed as needed
       • Can be read from, written to, or appended to
       • External formats (more) completely specified
       • Not upward-compatible!




                                         V
                                                                        Ÿœª„‹



18) Shared Variables
     VHDL' 87:
       • Signal only communication path between process
       • Models (largely) deterministic
       • Very high-level, stochastic models difficult to write
     VHDL' 93:
       • Multiple processes may access SHARED variables
       • Inherently non-deterministic!
       • No language-defined synchronization mechanism
             − Models may exhibit non-algorithmic behavior on certain
                implementations
       • Working group established to add synchronization
             − Currently favored approach is the monitor

19) Shift and Rotate Operators
     VHDL' 87:
       • Shifting and rotating via slicing and concatenation only
               s := s (30 DOWNTO 0) & '0'; -- shift left logical
               s := s (0) & s (31 DOWNTO 1); -- rotate right
       • Difficult for tools to understand
     VHDL' 93:
       • SLL, SRL, SLA, SRA, ROL and ROR
       • Predefined for 1-D arrays of BIT or BOOLEAN
       • May be overloaded for all other types
       • Predefined arithmetic shifts assume MSB is sign bit!

20) XNOR Operator
     VHDL' 87:
       • Logical operators: AND, OR, NAND, NOR, XOR and NOT
       • No XNOR
       • can use "="
       • May have to overload
       • May want different 'X' handling
     VHDL' 93:
       • Introduces XNOR operator
       • Same precedence as dyadic logical operators
       • Associative
       • Overloadable




                                         VI

				
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Description: VHDL