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									  IN THE NAME OF GOD
         ADOPTED FROM:
  IEEE JOURNAL OF SOLID-STATE
CIRCUITS,VOL.41,NO.1,JANUARY 2006

         Presented by:
     Samane Soleimani Amiri
     Advanced VLSI Course
       Class presentation

                                    1
   A 146mm2 8Gb NAND Flash Memory
       with 70nm CMOS Technology

     T. Hara1, K. Fukuda1, K. Kanazawa1, N. Shibata1, K. Hosono1,
       H. Maejima1, M. Nakagawa1, T. Abe1, M. Kojima1, M. Fujiu1,
     Y. Takeuchi1, K. Amemiya1, M. Morooka1, T. Kamei2, H. Nasu2,
        K. Kawano2, C. Wang2, K. Sakurai3, N. Tokiwa3, H. Waki3,
T. Maruyama1, S. Yoshikawa1, M. Higashitani2, T.D. Pham2, T. Watanabe1

       1Toshiba Corporation, Yokohama, Japan
       2SanDisk Corporation, Sunnyvale, CA

       3Toshiba Microelectronics Corporation, Yokohama, Japan




                                                                         2
About NAND Flash Memories
• NAND Flash memories have become the
  key devices for portable mass data
  storage.
• These memories are used in digital still
  cameras, cellular phones, handheld
  devices, USB memories, and portable
  audio and video players.
• High memory capacity, and high data
  throughput.

                                             3
                   Outline
• Introduction
• Chip architecture for small die size
  – One-sided pad arrangement
  – Compact memory core design
  – Block address expansion scheme
• MLC program techniques for high throughput
  – Program with write cache
  – Vpgm compensation for edge WLs
• Device performance
• Summary


                                               4
                                             Introduction[1]
                            100
                           100
Unit Die Size (mm2 / MB)

                                               Digital still camera
                                                                 Portable audio
                                                                         Cellular phone
                            10
                            10
                                                                         USB memory



                             1
                             1                                               This Work

                                         SLC NAND Flash
                                         MLC NAND Flash

                           0.1
                            0.1
                              1994
                               1994   1996
                                      1996     1998
                                               1998     2000
                                                        2000      2002
                                                                  2002       2004
                                                                             2004     2006
                                                                                      2006
                                                        Year
                                                                                             5
                       Chip Architecture[1]

                                          • Two 4Gb memory planes
                                            –   # of blocks: 2K
    4Gb                  4Gb                –   Page size: 2KB
Memory Array         Memory Array           –   Block size: 256KB
  (Plane0)             (Plane1)
                                            –   # of pages / block: 128
                                          • One-sided pad arrangement
                                            and simple memory core design
 Row decoder          Row decoder           – Half size of pad region
                                            – Small wiring area
                                            – Short data path

BL control circuit   BL control circuit         ⇒ Small die size
   Peripheral         Charge pump
    circuits                 Pads


                                                                          6
Memory Core Design (Conventional) [1]
                                                           Pads
                       BLCTRL                   CELSRC BLCTRL       CPWEL
                                                   BL selector 1 (BLS1)
                       BLS1




                                      Decoder




                                                                                Decoder
                           CELSRC                    4Gb cell array
                           CPWEL
                                                   BL selector 2 (BLS2)
                     BLo
  BLe




                                                    BL control circuit
                                                CELSRC              CPWEL
                                                           Pads

                       BLS2
                                                    Read    Program    Erase
                                    CELSRC          Vss       ~2V     floating
        BL control                  BLCTRL          Vss       Vcc         Vss
         circuit
                                    CPWEL           Vss       Vss         ~20V

                                                                                          7
  Memory Core Design (This Work) [1]
• To realize compact core design with simple power lines
  and signal wirings
      – Remove core drivers from the upper side of 4Gb cell array
      – Merge two BL selectors

                     Pads
           CELSRC BLCTRL     CPWEL
              BL selector 1 (BLS1)
 Decoder




                                     Decoder

                                               Decoder




                                                                                 Decoder
                4Gb cell array                               4Gb cell array

              BL selector 2 (BLS2)                          BL selector (BLS)
               BL control circuit                           BL control circuit
           CELSRC            CPWEL                       CELSRC BLCTRL CPWEL
                     Pads                                         Pads

               Conventional                                   This Work
                                                                                           8
            BL Selector (1) [1]
                     BLCTRL
                                                           CELSRC
                     BLS1




                                                     BLo
                                  BLe
                         CELSRC



                   BLo
BLe




                                                       BLCTRL


                                                       BLS
                     BLS2

      BL control                        BL control
       circuit                           circuit

Conventional                            This Work
                                                                    9
                BL Selector (2) [1]
               BLCTRL
                              • No field isolation
                              • Similar M1 connection
                       BLS1
               BIASo               Cell Array
               BIASe
                                   8 BL pairs

 Cell Array                                     BLCTRL
  8 BL pairs

               BLSe                                      BLS
               BLSo
                                                BIASe
                       BLS2                     BLSe
                                                BLSo
                                                BIASo

 BL control                        BL control
  circuit                           circuit

Conventional                      This Work                    10
                     Block Configuration[1]
                • Block address expansion scheme
                      – No block redundancy control circuit
                      – No unused “valid” block
            Plane0                  Plane1                             Plane0                  Plane1
               0                     2048                                 0                     2048
               1                     2049                                 1                     2049
Row dec.




                        Row dec.




                                                Row dec.



                                                           Row dec.




                                                                                   Row dec.




                                                                                                           Row dec.
             2046                    4094                               2046                    4094
             2047                    4095                               2047                    4095
           Block RD                Block RD                             4096                    4128

           Block RD                Block RD                             4127                    4159
           BL control              BL control                         BL control              BL control
            circuit                 circuit                            circuit                 circuit

               Block redundancy
                 control circuit

                     X-Add                                                      X-Add
              Conventional                                                    This work                               11
        Die Size Reduction[1]
 153.0mm2       - 7.5mm2        145.5mm2
  (100%)         (- 4.9%)        (95.1%)

                - 7.1mm2
                Pad area
          Power & signal wiring         Peripheral circuit
         Block R/D control circuit

                - 0.4mm2                BL control circuit
                                        Row decoder
                                        Cell array




Conventional                     This Work
                                                             12
                        MLC Program[1]




                                  BLo_n+1
                        BLe_n+1
                BLo_n
        BLe_n
                                                  Even            Odd



WLn+1                                       Upper   Lower   Upper Lower
                                            “0”      “0”    “0”     “0”
WLn
                                            “1”      “1”    “1”     “1”
WLn-1

                                              “X2” “X1”

                                            • One WL includes four pages




                                                                           13
        MLC Program (Lower page) [1]
                                                Bit-by-bit
                               VREG     DTG     verify circuit

                                                 Latch<B>
                  BLPRE
                                      REG
                BLCLAMP               BLCB
  BLo
BLe
      (2) Lower page program
                                      (1) Transfer Latch<A>
                                                                     / IO

                                                                  CSL
                                      BLCA

                                                                      IO


                                                     (0) Data load (N)
                                                     (3) Data load (N+1)

                                                                            14
        MLC Program (Upper page) [1]
                                                Bit-by-bit
                               VREG     DTG     verify circuit

                                                 Latch<B>
                  BLPRE
                                      REG
                 BLCLAMP              BLCB
  BLo
BLe
      (6) Upper page program
                                      (4) Transfer Latch<A>
      (5) Lower page read
                                                                     / IO

                                                                  CSL
                                      BLCA

                                                                      IO


                                                     (3) Data load (N+1)
                                                     (7) Data load (N+2)

                                                                            15
 Program Voltage Compensation
• The program time depends on the number of
  program pulses.
• The coupling ratio of floating gate is different in
  each WL.
• If the coupling ratio of WL 0 and 31 are higher
  than the others, the program speed of WL 0 and
  31 becomes faster.
• If the program start voltages for other WLs are
  set higher, the total numbers of program pulses
  become small and program speed becomes
  faster.


                                                        16
                          Vpgm Compensation[1]




                                             Number of Cells
                                                                                      Voffset
                                  WL1~30
                                                                WL1~30                           WL0, 31
                      Voffset
Program Voltage




                  DVPGM           WL0, 31
                                                                        Vth Distribution
                                                                    (Single pulse program)

                                        C0 < C1                                       WL
                                             SGS                    0        1        2    29 30 31 SGD

                                                               C0       C1       C1         C1   C1   C0

                                        N+                                                                 N+
                  Program Loops
                                                                                  Pwell

                                                                                                                17
                             Program Time[1]
• Average program time: 670ms
  Program time = (Upper page prog. + Lower page prog.) / 2

                   60

                   50
   Frequency (%)




                   40

                   30

                   20

                   10

                   0
                        600 620 640 660 680 700 720 740 760 780 800

                                 Program Time (ms)
                                                                      18
       Program Throughput[1]
                            • tPROG=670ms, tWC=30ns

Program Throughput (MB/s)
                            7
                                    x8 I/O
                            6
                                   Write cache &
                                Vpgm compensation         +30%
                            5

                            4

                            3
                                          Without write cache &
                            2             Vpgm compensation

                            0
                                0     2                  4
                                     Page Length (KB)
                                                                  19
                                 Shmoo Plot[1]
  • Condition: 85℃, Cload=50pF

                   tREA                                         tRC (tRP=15ns)
(TREA)    10NS     15NS      20NS      25NS         (TRC)     15NS     20NS      25NS      30NS
  VCC :   |----+----|----+----|----+----|             VCC :   |----+----|----+----|----+----|
 4.000V   FFFF.........................., 12.00NS    4.000V   FFFFFFFFFFFFFFFF.............., 23.00NS
 3.900V   FFFFF........................., 12.50NS    3.900V   FFFFFFFFFFFFFFFF.............., 23.00NS
 3.800V   FFFFF........................., 12.50NS    3.800V   FFFFFFFFFFFFFFFF.............., 23.00NS
 3.700V   FFFFF........................., 12.50NS    3.700V   FFFFFFFFFFFFFFFF.............., 23.00NS
 3.600V   FFFFF........................., 12.50NS    3.600V   FFFFFFFFFFFFFFFF.............., 23.00NS
 3.500V   FFFFF........................., 12.50NS    3.500V   FFFFFFFFFFFFFFFF.............., 23.00NS
 3.400V   FFFFF........................., 12.50NS    3.400V   FFFFFFFFFFFFFFFF.............., 23.00NS
 3.300V   FFFFFF........................, 13.00NS    3.300V   FFFFFFFFFFFFFFFF.............., 23.00NS
 3.200V   FFFFFF........................, 13.00NS    3.200V   FFFFFFFFFFFFFFFF.............., 23.00NS
 3.100V   FFFFFFF......................., 13.50NS    3.100V   FFFFFFFFFFFFFFFF.............., 23.00NS
 3.000V   FFFFFFFF......................, 14.00NS    3.000V   FFFFFFFFFFFFFFFF.............., 23.00NS
 2.900V   FFFFFFFFF....................., 14.50NS    2.900V   FFFFFFFFFFFFFFFF.............., 23.00NS
 2.800V   FFFFFFFFFFF..................., 15.50NS    2.800V   FFFFFFFFFFFFFFFF.............., 23.00NS
2.7V
 2.700V
                                    16.5ns
          FFFFFFFFFFFFF................., 16.50NS   2.7V
                                                     2.700V                             23.0ns
                                                              FFFFFFFFFFFFFFFF.............., 23.00NS
 2.600V   FFFFFFFFFFFFFFF..............., 17.50NS    2.600V   FFFFFFFFFFFFFFFF.............., 23.00NS
 2.500V   FFFFFFFFFFFFFFFFF............., 18.50NS    2.500V   FFFFFFFFFFFFFFFF.............., 23.00NS
 2.400V   FFFFFFFFFFFFFFFFFFF..........., 19.50NS    2.400V   FFFFFFFFFFFFFFFF.............., 23.00NS
 2.300V   FFFFFFFFFFFFFFFFFFFFFF........, 21.00NS    2.300V   FFFFFFFFFFFFFFFFF............., 23.50NS
 2.200V   FFFFFFFFFFFFFFFFFFFFFFFFFF...., 23.50NS    2.200V   FFFFFFFFFFFFFFFFFF............, 24.00NS




                                                                                                        20
                   Features

Technology         70nm p-sub triple-well CMOS
                   3-metal (1W, 2Al)
Cell size          0.024mm2 (effective)
Die size           145.5mm2
Organization       2112 x 128 page x 4K block x 8
                   1056 x 128 page x 4K block x 16
Power supply       2.7~3.6V
Read cycle         50ns (Normal: 100pF)
                   30ns (Burst: 50pF)
Write cycle        30ns
Prog. throughput   6MB/s
Read throughput    30MB/s (X8)
                   60MB/s (X16)

                                                     21
             Summary

• 70nm 8Gb NAND Flash memory
• Small die size: 146mm2
  – One-sided pad arrangement
  – Compact memory core design
  – Block address expansion scheme
• Fast MLC program throughput: 6MB/s
  – Program with write cache
  – Vpgm compensation for edge WLs




                                       22
                         Reference
[1]. T. Hara1, et “A 146mm2 8Gb NAND Flash Memory with 70nm CMOS
     Technology” IEEE JOURNAL OF SOLID-STATE
     CIRCUITS,VOL.41,NO.1,JANUARY 2006




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