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```					Fault-Secure Parity Prediction
Arithmetic Operators

MICHAEL NICOLAIDIS
RICARDO O. DUARTE
TIMA Laboratory
JOAN FIGUERAS
Polytechnic University of Catalonia
Outline

   What is the problem ?
   Efficient Self-Checking Arithimetic
   Analysis of fault secureness
   Single-cell fan-out networks
   Take some examples
   Multiple-cell fan-out networks
   Implementations and experiments
   Conclusions
What’s The Problem ?

DRAWBACK:
 Parity prediction may not achieve fault-
secureness , because single faults propagate o-
-utput errors of random multiplicity.
 Arithmetic codes can ensure falut secureness for
most arithmetic operators.
Problem
   1.Arithmetic code checkers are complex circuit
   2.Arithmetic code are not compatible with
parity checking
   3.Must implement whole system with A~ code
Efficient self-checking arithimetic

   Parity prediction schemes carries a lower
penalty than arithmetic coding schemes
for small and medium-size operands.

   And we are interest in efficient parity
prediction implementations.
Method :
Include arithemetic operators
Analysis of fault secureness

   Definition: In a self-checking design, a circuit is
fault secure if its output code detects all errors
generated by each modeled fault.
   Restriction: Cannot achieve fault secureness
because even-multiplicity errors escape
detection by parity code.
-Solution : 1.先分析parity prediction cellular
arithmetic operators來看不符合的原因.
2.一一排解.

continuous
Analysis of fault secureness

   Basic components of cellular arithmetic
operators : full- and half- adder cells.
   5大主題:
   Lemma1. 將不符合fault-secure的parity predictor電路給
它獨立出來.
   Lemma2. 在不符合fault-secure的parity predictor電路中,
將經由運算得到的carries,拿來推算其可能產生的parity.

continuous
Analysis of fault secureness

   Lemma3. 証明如果上圖的sum(S)和carry(C)使用同一個電
路則arithmetic operator將無法fault secure.

continuous
Analysis of fault secureness

   Lemma4. 証明如果一個cell的inputs只能生成sum,carry,跟
redundant carry任兩個,則operator也無法fault secure.
continuous
Analysis of fault secureness

   Lemma5. 証明如果說C,Cp和S在logic有fault而產生error給
C跟Cp,則儘管error會傳給下一個S,但其仍可符合fault
secureness
Single-cell fan-out networks

   Definition: any network in
which each cell output
enters exactly one input
of exactly one cell is a
single-cell fan-out
networks.
   Theorem1 : Parity
prediction in a single-cell
fan-out network using
designed as in Fig.3
achieves fault secureness.
continuous
Single-cell fan-out networks

   Theorem2 : The full-adder cell of Fig.4 prserves fault
secureness.
Examples

Examples

   Parity prediction multipliers.
Examples

   Improved parity prediction multiplier.
Multiple-cell fan-out networks

   A more complex
implementation is
required if some signals
enter an even number of
cell inputs.
   Fig.9b is one solution.
   Fig.9c is another solution
with a double-rail checker.
Examples
   Nonrestoring-array divider.
   The array’s basic cell is the controlled add/subtract cell.
Self-Checking nonrestoring-array divider
Divider points

   Each carry signal enters the row’s rightmost cell
twice.
   The divider generates two independent sets of
outputs(remainder and quotient).
   The leftmost cell’s carry and sum outputs have
opposite values,and either can provide the
quotient outputs.
   The parity of sum outputs is PS=PCp+PN+PD+1
for even number of rows,it becomes
PS=PCp+PN+1.
Implementations and experiments
Implementations and experiments
Implementations and experiments
Conclusions

   Hardware cost of these fault-secure structures is
significant.
   For small nad medium size operators,these
solution are also more efficient than operators
based on arithmetic codes which require
complex checkers and code translators for
compatibility.

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