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Analog IC design -- Powerpoint -- The Art of Analog Layout

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Analog IC design -- Powerpoint -- The Art of Analog Layout Powered By Docstoc
					Workshop on Fully Layout Technology         2002 / 03 / 23




THE ART OF ANALOG LAYOUT

                主講㆟:林正松

                矽拓科技有限公司
                   :
                TEL:03-5101949

                                      林正松 / 矽拓科技有限公司
    Workshop on Fully Layout Technology         2002 / 03 / 23




    前言

       •   瞭解Analog佈局元件
       •   熟悉analog matching guide
       •   適當技巧性的放置
       •   Design 與 layout 的共識


2                                         林正松 / 矽拓科技有限公司
    Workshop on Fully Layout Technology         2002 / 03 / 23



               ANALOG LAYOUT

        • CMOS ANALOG LAYOUT

        • BIPOLAR ANALOG LAYOUT

        • BICMOS ANALOG LAYOUT



3                                         林正松 / 矽拓科技有限公司
    Workshop on Fully Layout Technology            2002 / 03 / 23



       CMOS ANALOG LAYOUT
           • CMOS Component Layout Guide

           • CMOS Layout Application
                  •   Transistor
                  •   Capacitor
                  •   Resistor
                  •   Bipolar
                  •   Mos power transistor

           • CMOS Layout Case Study

4                                            林正松 / 矽拓科技有限公司
     Workshop on Fully Layout Technology                         2002 / 03 / 23


                CMOS LAYOUT STRUCTURE

    LV NMOS                                LV PMOS
    :(poly)&(active)&(nplus)&(psub)        :(poly)&(active)&(pplus)&(nwell)




     s     G    D                                     S   G     D
5                                                         林正松 / 矽拓科技有限公司
    Workshop on Fully Layout Technology                            2002 / 03 / 23

               CMOS LAYOUT STRUCTURE
          Asymmetric HV12V Device Layout
    N++                                       P+      POLY    P+   NWELL
          N+          POLY
               DIFF          N+        PDD


                                        HV
                                                                    CONTACT
                                  HV
                                       MT1


                                       DIFF
          DRAIN GATESOURCE                         DRAIN GATE SOURCE

               NMOS                                      PMOS
6                                                            林正松 / 矽拓科技有限公司
      Workshop on Fully Layout Technology                          2002 / 03 / 23


             CMOS LAYOUT STRUCTURE
          Asymmetric HVP30V Device Layout
                                          NWELL+BL
                                                       NWELL+HPF
                                                                   POLY
                                                                           N+
                          L            HV
                                                               L           HV
     CO                                 DIFF
                                       P+
                                                                           DIFF
               DRAIN   GATE   SOURCE                 DRAIN   GATE SOURCE




    HPF+BL                POLY
                                                NMOS
             PMOS
7                                                       林正松 / 矽拓科技有限公司
    Workshop on Fully Layout Technology             2002 / 03 / 23


       CMOS-RESISTOR LAYOUT STRUCTURE
>>Diff Resistor             >>Poly register   >>Nwell Resistor
            CONTACT                   POLY1

                                                          Ndiff

                      P+
        DIFF
                                                NWELL




                    NWELL

      DUMMY                     DUMMY
8                                             林正松 / 矽拓科技有限公司
     Workshop on Fully Layout Technology                 2002 / 03 / 23
          CMOS-CAPACITOR LAYOUT STRUCTURE
                                           CO
    1、P1-P2 LAYOUT STRUCTURE
                                                 poly1
                      M1



                    M2                           POLY2


    2、MOS LAYOUT STRUCTURE                 CO
                                                       P+
                     N+
                                                poly
                   DIFF
                                                1


9                                               林正松 / 矽拓科技有限公司
     Workshop on Fully Layout Technology                   2002 / 03 / 23

      CMOS-CAPACITOR LAYOUT STRUCTURE
       3、MIN TOPMETAL 與 TOPMETAL-1之間加-MINLAYER
                                                   M
                       M4                          5
                       VIA4


                                            MIM
       4、METAL POLY STRUCTURE

                                                  NWELL
                                                  CONTACT




                                 BOTTOM=POLY1+M2
                                               TOP=M1+M3
10                                                林正松 / 矽拓科技有限公司
     Workshop on Fully Layout Technology         2002 / 03 / 23

               CMOS-PNP LAYOUT STRUCTURE




                                                  NWELL
                                                    CONTACT



                                                    DIFF
                                                     M1

                                                  P+




11                                         林正松 / 矽拓科技有限公司
     Workshop on Fully Layout Technology                          2002 / 03 / 23

                CMOS-FUSE LAYOUT STRUCTURE
               METAL FUSE       POLY1 FUSE           POLY1 FUSE
                                           CONTACT
                                                                   M1
                                              M1



                                            CONTACT               POLY1

                                                             PASS




                                           POL
                                           Y1
     STYLE-1                  STYLE-2                STYLE -3
12                                                      林正松 / 矽拓科技有限公司
     Workshop on Fully Layout Technology                  2002 / 03 / 23

        CMOS LAYOUT APPLICATION -TRANSISTOR
     >>MOS Matching Mirror                       M2

                                                           VIA

                                                           M1




                                                            P+




                                   POLY    CONTACT DIFF
13                                               林正松 / 矽拓科技有限公司
      Workshop on Fully Layout Technology           2002 / 03 / 23

        CMOS LAYOUT APPLICATION -TRANSISTOR
     >>交叉對稱(1)




                                            OUT P
                                            OUT N




14                                           林正松 / 矽拓科技有限公司
     Workshop on Fully Layout Technology         2002 / 03 / 23

        CMOS LAYOUT APPLICATION -TRANSISTOR


     >>交叉對稱(2)




                                             DUMMY POLY




15                                         林正松 / 矽拓科技有限公司
      Workshop on Fully Layout Technology         2002 / 03 / 23

           CMOS LAYOUT APPLICATION-CAPACITOR
       >>Unit Capacitor


     DUMMY
                                                 DUMMY




                                                 Well contact




                                            林正松 / 矽拓科技有限公司
16           poly
     Workshop on Fully Layout Technology                   2002 / 03 / 23

         CMOS LAYOUT APPLICATION-CAPACITOR
            >>Unit Capacitor –Input Stage Matching
                                                          POLY2

                                                         POLY1




     WELL
     CONTACT


                                                          M1



17                                                   林正松 / 矽拓科技有限公司
     Workshop on Fully Layout Technology         2002 / 03 / 23

          CMOS LAYOUT APPLICATION-RESISTOR

                          兩端拉出即可
       >> Normal Resistor-兩端拉出即可




18                                         林正松 / 矽拓科技有限公司
      Workshop on Fully Layout Technology                    2002 / 03 / 23

            CMOS LAYOUT APPLICATION-RESISTOR


     >>Crocess Resistor
                                            M2   VIA    WELLCONTACT


                                                           CONTACT



                                                                  POLY

                                                                 M1




19                                                     林正松 / 矽拓科技有限公司
     Workshop on Fully Layout Technology         2002 / 03 / 23

        CMOS LAYOUT APPLICATION -RESISTOR
     >>交叉對稱




                                           DUMMY
     DUMMY




20                                         林正松 / 矽拓科技有限公司
     Workshop on Fully Layout Technology          2002 / 03 / 23

           CMOS LAYOUT APPLICATION –PNP X 10


                  P+   NWELL
                                       P+
                               N+




21                                          林正松 / 矽拓科技有限公司
     Workshop on Fully Layout Technology                2002 / 03 / 23

             CMOS LAYOUT APPLICATION –PNP X 9
                                           N+

                                                NWELL


                                                 P+


                                                P+




22                                              林正松 / 矽拓科技有限公司
      Workshop on Fully Layout Technology                  2002 / 03 / 23


     CMOS LAYOUT APPLICATION-Power MOS Transistor(1)

     ESD PROTECTION 佈局方式不影響面積               面積效益是最好
                                            ESD PROTECTION 能力差㆒點




            STYLE -1                            STYLE -2
23                                                 林正松 / 矽拓科技有限公司
      Workshop on Fully Layout Technology             2002 / 03 / 23

 CMOS LAYOUT APPLICATION –Power MOS Transistor(2)

                                            N+ DIFF   NWELL
     阻抗考量,正方面型最好




                                                           P+ DIFF




                                                           POLY




24                                             林正松 / 矽拓科技有限公司
     Workshop on Fully Layout Technology            2002 / 03 / 23

                                             ( )
CMOS LAYOUT APPLICATION- Power MOS Transistor(3)

                                           N+DIFF
                                                    P+DIFF

                                                        NDIFF

                                                          POLY




25                                           林正松 / 矽拓科技有限公司
      Workshop on Fully Layout Technology         2002 / 03 / 23

                                             ( )
CMOS LAYOUT APPLICATION –Power MOS Transistor(4)
     >>M2 Finger Structure

M2




                                                        M1




26                                          林正松 / 矽拓科技有限公司
     Workshop on Fully Layout Technology         2002 / 03 / 23

                  CMOS LAYOUT CASE STUDY
 >>OP1


                                                  NW
                                                  OD
                                                  P+
                                                   N+
                                                   P1
                                                   P2
                                                  CO
                                                  M1
                                                  M2
                                                  VIA




27                                         林正松 / 矽拓科技有限公司
     Workshop on Fully Layout Technology                         2002 / 03 / 23
                   CMOS LAYOUT CASE STUDY
>>OP2


                                           4
                                           44    2    3

                     6    5
      IP                                                        NW
      IN                                                        OD
                                                 1    4         P+
                                           3                    N+
                                                                P1
                     5    6                                     P2
                                                                CO
                                                                M1
                                                                M2
                                                                VIA
                                           7 8       7 8
28                                                         林正松 / 矽拓科技有限公司
     Workshop on Fully Layout Technology         2002 / 03 / 23

             CMOS LAYOUT CASE STUDY-CIRCUIT




29                                         林正松 / 矽拓科技有限公司
     Workshop on Fully Layout Technology         2002 / 03 / 23



     BIPOLAR ANALOG LAYOUT

        • BIPOLAR Component Layout Guide

        • BIPOLAR Layout Application


        • BIPOLAR Layout Case Study

30                                         林正松 / 矽拓科技有限公司
     Workshop on Fully Layout Technology                   2002 / 03 / 23


            BIPOLAR LAYOUT STRUCTURE-VNPN

                                                               BL
                                                               DC
                                                               SP
                                                               SN
                                                               CO
                                                               M1

                                                               VIA
                                                               M2
                                                               TO
                                                               CAP
                                                                IR



       STYLE-1                             STYLE-2



31                                                   林正松 / 矽拓科技有限公司
     Workshop on Fully Layout Technology                   2002 / 03 / 23


             BIPOLAR LAYOUT STRUCTURE-LPNP



                                                               BL
                                                               DC
                                                               SP
                                                               SN
                                                               CO
                                                               M1

                                                               VIA
                                                               M2
                                                               TO
                                                               CAP
                                                                IR
      STYLE-1            STYLE-2           STYLE-3




32                                                   林正松 / 矽拓科技有限公司
       Workshop on Fully Layout Technology              2002 / 03 / 23

            BIPOLAR –CAPACITOR LAYOUT STRUCTURE

     >>Sn-cap type
                                 BL
      SN                       BIPOLAR-RISISTOR LAYOUT STRUCTURE


     MT1



     TO

      cap


                                   IR                  SP
33                                                林正松 / 矽拓科技有限公司
     Workshop on Fully Layout Technology         2002 / 03 / 23


           BIPOLAR LAYOUT APPLICATION-VNPN




34                                         林正松 / 矽拓科技有限公司
     Workshop on Fully Layout Technology             2002 / 03 / 23


            BIPOLAR LAYOUT APPLICATION-LPNP




             STYLE-1                       STYLE-2


35                                           林正松 / 矽拓科技有限公司
     Workshop on Fully Layout Technology         2002 / 03 / 23

           BIPOLAR LAYOUT APPLICATION-LPNP




                                STYLE-3
36                                         林正松 / 矽拓科技有限公司
     Workshop on Fully Layout Technology          2002 / 03 / 23

BIPOLAR LAYOUT APPLICATION-Power Transistor
                                      電流平均分散 讓熱不會集㆗
     EMIT 面積效應最大




            矩型                             工字型
37                                          林正松 / 矽拓科技有限公司
     Workshop on Fully Layout Technology         2002 / 03 / 23
          BIPOLAR LAYOUT APPLICATION-VNPN
         增加EMIT的周長,提昇趨動能力




38                               梯型        林正松 / 矽拓科技有限公司
     Workshop on Fully Layout Technology         2002 / 03 / 23

                 BIPOLAR LAYOUT CASE STUDY




39                                         林正松 / 矽拓科技有限公司
     Workshop on Fully Layout Technology         2002 / 03 / 23


           BIPOLAR LAYOUT CASE STUDY -CIRCUIT




40                                         林正松 / 矽拓科技有限公司
     Workshop on Fully Layout Technology         2002 / 03 / 23

                 BIPOLAR LAYOUT CASE STUDY




41                                         林正松 / 矽拓科技有限公司
     Workshop on Fully Layout Technology         2002 / 03 / 23



     BICMOS ANALOG LAYOUT

     • BICMOS Component Layout Guide

     • BICMOS Layout Application


     • BICMOS Layout Case Study


42                                         林正松 / 矽拓科技有限公司
     Workshop on Fully Layout Technology         2002 / 03 / 23

                 BICMOS LAYOUT STURCTURE




43                                         林正松 / 矽拓科技有限公司
      Workshop on Fully Layout Technology         2002 / 03 / 23

           BICMOS LAYOUT STURCTURE-VPNP

     >>Double Base
                      DIFF   PW
     CONTACT

                                      P+




                                     N+

                                   NWELL    林正松 / 矽拓科技有限公司
44
     Workshop on Fully Layout Technology           2002 / 03 / 23

          BICMOS LAYOUT STURCTURE-LPNP


                                           NWELL
                                           NDIFF

                                           N+BL

                                           PDIFF



                                            POLY


45                                          林正松 / 矽拓科技有限公司
     Workshop on Fully Layout Technology         2002 / 03 / 23

          BICMOS LAYOUT STURCTURE-VNPN
      >>Double Base-降低Base 阻抗




46                                         林正松 / 矽拓科技有限公司
       Workshop on Fully Layout Technology               2002 / 03 / 23


       BICMOS LAYOUT STURCTURE-RESISTOR



     >>Base Resistor        >>P1 resistor    >>P2 resistor




47                                                林正松 / 矽拓科技有限公司
     Workshop on Fully Layout Technology                        2002 / 03 / 23


              BICMOS LAYOUT STURCTURE

 >>SNK Capasistor                          >>P1-P2 Capasistor
                                     N+INP       NWELL          N+BL




48                                                       林正松 / 矽拓科技有限公司
     Workshop on Fully Layout Technology         2002 / 03 / 23
        BICMOS LAYOUT APPLICATION-VNPN

     >>交叉對稱




49                                         林正松 / 矽拓科技有限公司
     Workshop on Fully Layout Technology         2002 / 03 / 23

        BICMOS LAYOUT APPLICATION-VNPN
                   增加Driver 趨動能力,節省面積




50                                         林正松 / 矽拓科技有限公司
     Workshop on Fully Layout Technology                                                     2002 / 03 / 23

            BICMOS LAYOUT CASE STUDY-CASE 1
 >>OP1


                      M1 M3 M4

                       M3 M4 M2            R2           R2
                                                             R2        R2   R2 R2 R2
                                                                  R2


                       Q2      Q1

     IN
      IP
                       Q1      Q2
              DUMMY




                                                DUMMY




                       R1 R1    R1   R1   R1                 M5 M5




51                                                                                     林正松 / 矽拓科技有限公司
     Workshop on Fully Layout Technology         2002 / 03 / 23


              BICMOS CASE STUDY –OP CIRCUIT




52                                         林正松 / 矽拓科技有限公司
     Workshop on Fully Layout Technology                                                                                                2002 / 03 / 23
                                    BICMOS LAYOUT CASE STUDY-CASE 2
AMP

                                                      G1                                          M6
                                                                                                                M5
                                                                                                                       M1
                                                                                                               M4
                                                                                                          M6          M1
       DUMMY



                                      DUMMY

                                                                                             M3
                                                                                  M3        M2
                                                                             IN
                                                                                       M2                       M4
                                                                                                     M1        M5      M6
                                                      COLLECT
       DUMMY DUMMY DUMMY DUMMY




                                              DUMMY




                                                                                                          M1          M6
                                   R1 R1
                                                           Q3                     M2
                                                                                        M2
                                                                                       M3
                                                                   DUMMY


                                                                                    M3
                                                                                                          Q2         Q1
                                   R1 R1 R1                R2 R3




                                                                                                  DUMMY




                                                                                                                          DUMMY
                                                                   DUMMY DUMMY




                                                                                                          R4 R3 R4 R3
                                 R1 R1 R1 R1 R1 R1 R1 R2                                                       R3

                                                                                                  DUMMY




                                                                                                                          DUMMY
                                 R1 R1 R1 R1 R2 R2 R2 R2                            M7                    R3 R4 R3 R4



53                                                                                                                                林正松 / 矽拓科技有限公司
     Workshop on Fully Layout Technology         2002 / 03 / 23


             BICMOS CASE STUDY –AMP CIRCUIT




54                                         林正松 / 矽拓科技有限公司

				
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