Document Sample

A Fast Block Structure Preserving Model Order Reduction for Inverse Inductance Circuits Hao Yu, Yiyu Shi, Lei He Electrical Engineering Dept. UCLA David Smart Analog Devices Inc. Partially supported by NSF, SRC and UC-MICRO fund Challenge to Model Inductance 2 current C4 package Power Plane return Power IO skin depth c4 bump Cell parasitic capacitance and well capacitance current on die Power grid signal lines Load current source that models switching gates Loop inductance? Where is the return path? Current return paths are not known as a priori How to stamp a loop inductance together with other devices in the same loop to the circuit matrix? Partial inductance by PEEC [Rueli:TMTT’74] is one choice for inductive interconnect PEEC Model for Interconnect 3 No need to determine return path But did we really solve the problem? Partial inductance is associated with every piece of branch current Mutual couplings are everywhere L matrix is dense and not diagonal dominant A fast simulator needs a sparse stamping of devices Sparsifying L by truncation leads to the loss of stability Stamping inverse inductance (L-1) element is an alternative solution L-1 is similar to the diagonal dominant capacitance (C) [Devgan:ICCAD’02], and hence it is easy to sparsify How to stamp it correctly in circuit matrix? How to further reduce it by model order reduction? Inverse Inductance Element Simulation 4 First-order stamping and reduction by modified nodal analysis (MNA) Directly stamping leads to a non-passive model [Zheng et.al.:ICCAD’02] Double inversion based stamping [Chen,et.al.: ICCAD’03] needs an extra cost to invert L matrix Second-order stamping and reduction by nodal analysis (NA) NA-stamping [Sheehan:DAC99, Zheng et.al :ICCAD’02, Su et. al:ICCAD’04] has singularity at dc, and is not robust to be stamped back for time domain simulation All above methods did not consider the structure (sparsity and hierarchy), and hence are not efficient for large-scale problem Primary contributions of our work: 1. Vector potential nodal analysis (VNA) represents L-1 in a non- singular and passive stamping 2. Bordered-block-diagonal structured reduction (BVOR) preserves not only passivity but also sparsity and hierarchy Outline 5 Background of Circuit Stamping VNA Stamping using VPEC (Vector Potential Equivalent Circuit) model BVOR Method using BBD (Bordered-block- diagonal) Representation Experimental Results Conclusions Modified Nodal Analysis 6 A network is described by two state variables: nodal voltage and branch current (G sC)x(s) BI(s) vn G : frequencyindependent + C : frequencydependent R Ib vn G El C Ei x , G T i , C , B 0 l El 0 L Vn- The stamping is not symmetric but passive Check G G 0, C CT 0 (and full rank) T The stamping is non-singular State equation is still definite at dc s 0 sC 0 L is shorted and C is open at dc State matrix is not rank-deficient especially for G because it needs to be factorized many times Stamping of L-Inverse in Circuit Matrix 7 MNA is not passive Check G G T ( ?)0 vn G El C Ei x , G 1 T A , C , B 0 l L El 0 I NA stamping is symmetric, seems to be passive, but is singular Only uses nodal voltages, and it results in a susceptance S for L-1 1 State equation is indefinite at dc s 0 sC S s Both G and S become rank-deficient in NA stamping 1 (G sC S ) x( s) Ei I ( s), x vn ; s S El L1 ElT : susceptance How to Easily Have a Singular Stamping 8 Why do we need branch current variable for inductance? The inductor is shorted at dc v2 and v3 are not independent anymore Need a new constraint by adding a new row for i1 NA v1 v2 v3 i1 v1 v2 v3 v1 (1/Rg+1/R) (-1/R) (0) (0) i1 iin v2 (-1/R) (1/R) (0) 1 R L v3 (0) (0) (0) -1 Rg i1 (0) (-1) (1) sL Outline 9 Background of Circuit Stamping VNA Stamping using VPEC (Vector Potential Equivalent Circuit) model BVOR Method using BBD (Bordered-block- diagonal) Representation Experimental Results Conclusions Vector Potential Equivalent Circuit 10 Differential Maxell equation A z A J , 2 z E z z t Define branch vector potential (flux) from a volume- integral of above differential equation [Pacelli:ICCAD’02] 1 Ai d i A z i VPEC circuit equation describes L-1 elements using branch variables (ii, vi) Ai Ai A j ^ Ai ^ ^ 1 ^ 1 ii , vi Rij 1 , Ri 0 1 ^ j i ^ t Lij ( Lii L1 ) ij Ri 0 Rij i j This leads to the proof that L-1 matrix is diagonal dominant [Yu-He:TCAD’05] VNA Stamping 11 Using both branch and nodal variables, VPEC circuit equation leads to a new circuit stamping for L-1 il Al , vi vn 1 L Al il , Ai El vn 1 1 1 KCL : Gvn El L Al C vn Ei I (t ) and L El vn L Ai vn G L1El C Ei x , G 1 T A , C 1 ,B 0 l L El 0 L The resulting VNA state matrix is non-singular and passive A Circuit Example 12 MNA v1 v2 v3 v4 v5 v6 i 1 i 2 v1 v2 v3 v4 v5 v6 i 1 i 2 p1 p2 g i1 gd v1 v2 v3 gd g v2 s v1 v3 v1 g+gd -g v1 cx -cx v1 1 l c c v2 -g g 1 v2 v2 sx sx cx m cx v3 -1 v3 c v3 -sx -sx v4 g+gd -g v4 -cx cx v4 1 g i2 gd gd g v5 -g g 1 v5 v5 v4 v5 v6 v5 v6 l v4 s v6 -1 v6 c v6 c c i1 -1 1 i1 l m a1 i2 -1 1 i2 m l a2 (a) (b) (a ) ( b) ( c) VNA NA v1 v2 v3 v4 v5 v6 v1 v2 v3 v4 v5 v6 v1 v2 v3 v4 v5 v6 a1 a2 v1 v2 v3 v4 v5 v6 a1 a2 p1 p2 v1 g+gd -g v1 v2 -g g v2 s -s sx - sx v1 g+gd -g v1 cx -cx v1 1 v3 v3 -s s - sx sx v4 g+gd - g v4 v2 -g g s sx v2 v2 v5 -g g v5 sx - sx s -s v3 -s -sx v3 c v3 v6 v6 - sx sx -s s (a) (b) v4 g+gd -g v4 -cx cx v4 1 v1 v2 v3 v4 v5 v6 p1 p2 v5 -g g sx s v5 v5 v1 cx - cx v1 1 v6 -sx -s v6 c v6 v2 v2 v3 c v3 a1 -s s -sx sx a1 s sx a1 v4 - cx cx v4 1 v5 v5 a2 -sx sx -s s a2 sx s a2 v6 c v6 (a) (b) (c) (c) (d) VNA Reduction (VOR) 13 The simple first-order model order reduction such as PRIMA [Odabasioglu,et.al:TCAD’98] can be applied Find a small dimensioned and orthnormalized matrix V to reduce the original system size by projection VT ˆ G G V qxN qxq NxN If V contains the subspace of moments, the reduced system can match the original system H s H s ˆ s0 s Advantages of VNA Reduction 14 The reduced model is passive (1) L B T Sufficient conditions for passivity: (2) V T (G G T )V 0, for all V (3) V T (C CT )V 0, for all V The VNA reduction can be performed at dc (s0=0), and hence the path tracing algorithm [Odabasioglu,et.al:TCAD’98] can be used for efficient reduction The reduced model by VNA can be robustly stamped together with active device for time-domain simulation * * 0 0 * * 0 0 * * * * * * I 0 ip * 0 0 i I (s) p ~ s 0 B up T 0 0 0 u 0 0 0 I ~ p x 0 x 0 G ~ ~ 0 B 0 0 0 C SAPOR is not robust to be stamped back with active devices Outline 15 Background of Circuit Stamping VNA Stamping using VPEC (Vector Potential Equivalent Circuit) model BVOR Method using BBD (Bordered-block- diagonal) Representation Experimental Results Conclusions Two Level Decomposition by Branch Tearing 16 A flat presentation of VNA does not show hierarchy and hence leads to a globalized reduction and simulation It is not efficient for large-scale circuit with inductance Path-tracing [Odabasioglu,et.al:TCAD’98] is only effective for tree-links but not for general network Two-level decomposition of Z0 VNA circuit by branch- tearing It results in decomposed blocks Yi X10 X20 Xm-1,0 Xm0 and a global block Z0, and they are interconnected by incident Y1 Y2 Ym-1 Ym matrix Xi0 The torn branch can be a resistor, a capacitor, or an inductor A hmetis partition is applied with specified ports for each block B1 B2 Bm-1 Bm BBD Representation 17 The resulting system is in fact a bordered-block-diagonal (BBD) state matrices Each block Yi is described by a set of VNA variables (vn, Al) The global block Z0 is described by a set of torn branch variables (ib) Y ( s) x BI ( s) Y1 0 0 X 10 B1 0 0 0 0 Y2 0 X 20 0 B2 0 0 Y B 0 0 Ym X m0 0 0 Bm 0 ( X 10 )T ( X 20 )T ( X m 0 )T Z0 0 0 0 0 The BBD stamping is passive (1) L BT , (2) Y Y * 0 BVOR: Localized Reduction 18 BBD representation enables a Q1 localized model order reduction Q2 Each block Yi (Gi, Ci, Bi) can be reduced locally Q The last block is purely composed by Qm coupling branches, which is projected by Qm 1 an identity matrix Block-diagonal structured projection [Yu-He-Tan:BMAS’05] preserves BBD structure during reduction G1,1 0 0 X 1,m1 G1,1 0 0 X 1,m 1 0 G2,2 0 X 2,m 1 0 G2,2 0 X 2,m1 G G 0 0 Gm,m X m,m 1 0 0 Gm,m X m,m 1 - X T T T Gm 1,m 1 T T T 1,m1 - X 2,m1 X m,m 1 - X 1,m 1 - X 2,m 1 - X 2,m 1 Gm 1,m 1 Reduced model is not only passive but also sparse, and it can be analyzed hierarchically Outline 19 Background of Circuit Stamping VNA Stamping using VPEC (Vector Potential Equivalent Circuit) model BVOR Method using BBD (Bordered-block- diagonal) Representation Experimental Results Conclusions Waveform Comparison (1) 20 Frequency/time domain waveform comparison of full- MNA, SAPOR [Su et.al:ICCAD’04] and VNA reduction (VOR) The reduced models are expanded close to dc (s0 = 10Hz) with order 80 VOR and original are visually identical in both time/frequency domain SAPOR has larger frequency-domain error and can not converge in time- domain simulation Waveform Comparison (2) 21 Frequency domain waveform in both low and high frequency range The reduced models are expanded at s0 = 1GHz with order 80 VOR is identical to the original in both ranges, But SAPOR has large error in low-frequency range. BBD Structure Preserving 22 BBD (two-level decomposition) representation and reduction of G and C matrices The reduced model has preserved sparsity and BBD structure Runtime Scalability Study of BVOR 23 Compared to SAPOR, BVOR (BBD reduction) is 23X faster to build, 30X faster to simulate, and has 51X smaller error Compared to VOR, BVOR is 12X faster to build, 30X faster to simulate Conclusions and Future Work 24 Propose a new circuit stamping (VNA) for L-inverse element, which is passive and non-singular Apply a bordered-block-diagonal (BBD) structured reduction, which enables a localized model order reduction for large scale RCL-1 circuits We are planning to extend the structured reduction to handle nonlinear system

DOCUMENT INFO

Shared By:

Categories:

Tags:

Stats:

views: | 0 |

posted: | 4/8/2013 |

language: | Unknown |

pages: | 24 |

OTHER DOCS BY dffhrtcv3

How are you planning on using Docstoc?
BUSINESS
PERSONAL

By registering with docstoc.com you agree to our
privacy policy and
terms of service, and to receive content and offer notifications.

Docstoc is the premier online destination to start and grow small businesses. It hosts the best quality and widest selection of professional documents (over 20 million) and resources including expert videos, articles and productivity tools to make every small business better.

Search or Browse for any specific document or resource you need for your business. Or explore our curated resources for Starting a Business, Growing a Business or for Professional Development.

Feel free to Contact Us with any questions you might have.