Processes and Threads by dominic.cecilia

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									        Recitation 6
        Virtual Memory
       Sample Questions
  Project 3 – Build Pthread Lib

Extra Office Hour: Wed 4pm-5pm
            HILL 367



                                  1
                Memory Hierarchy

                                    Virtual Memory
                           Memory

                   Cache
    Registers




Answer: Pretend we had something bigger
      => Virtual Memory
                                                     2
Memory Access Cost




                     3
       Virtual Memory
            Paging (1)




The position and function of the MMU
                                       4
Paging (2)

The relation between
  virtual addresses
  and physical
  memory addres-
  ses given by
  page table




                       5
  Paging: Address Translation

      virtual address


CPU        p       d                                   f


                                    physical address       d
                                                f      d

               p

                           f


                                                               memory
                       page table

                                                                        6
           Page Tables (1)




Internal operation of MMU with 16 4 KB pages   7
Two-Level Page-Table Scheme




                              8
   Translation Lookaside Buffers
• Translation on every memory access  must be
  fast
• What to do? Caching, of course …
   – Why does caching work? Temporal locality!
   – Same as normal memory cache – cache is smaller so
     can spend more $$ to make it faster
• Cache for page table entries is called the
  Translation Lookaside Buffer (TLB)
   – Typically fully associative
   – Relatively small number of entries (e.g., 64 or 128
     entries)
• On every memory access, we look for the page 
  frame mapping in the TLB
                                                           9
Paging: Address Translation with TLB
         TLB hit/ TLB miss

      virtual address


CPU        p     d                               f


                              physical address       d
                                          f      d


                        TLB

                  p/f


                         f                               memory


                                                                  10
                      Terms
•   Page frames
•   (Virtual) Pages
•   Page fault
•   Hit /Miss
•   Page table
•   TLB




                              11
              Page Replacement
• Highly motivated to find a good replacement
  policy
   – That is, when evicting a page, how do we choose the
     best victim in order to minimize the page fault rate?
• Is there an optimal replacement algorithm? If yes,
  what is it?
• Let’s look at an example:
   – Suppose we have 3 memory frames and are running a
     program that has the following reference pattern
                   7, 0, 1, 2, 0, 3, 0, 4, 2, 3
• Algorithms: Optimal, Not Recently Used(NRU),
  Second Chance, FIFO, LRU(Least Recently
  Used), Working Set & Clock, Nth Chance …                   12
     Optimal Page Replacement
• Suppose we know the access pattern in
  advance
              7, 0, 1, 2, 0, 3, 0, 4, 2, 3
• Optimal algorithm is to replace the page
  that will not be used for the longest period
  of time
• What’s the problem with this algorithm?
• Realistic policies try to predict future
  behavior on the basis of past behavior
  – Works because of locality
                                                 13
Not Recently Used Page Replacement Algorithm

 • Each page has Reference bit, Modified bit
   – bits are set when page is referenced, modified
 • Pages are classified
   1.   not referenced, not modified
   2.   not referenced, modified
   3.   referenced, not modified
   4.   referenced, modified
 • NRU removes page at random
   – from lowest numbered non empty class
                                                      14
 FIFO Page Replacement Algorithm

• Maintain a linked list of all pages
  – in order they came into memory


• Page at beginning of list replaced (remove the
  last cell)


• Disadvantage
  – Last cells may be often used

                                                   15
       Least Recently Used (LRU)
• Assume pages used recently will used again soon
  – throw out page that has been unused for longest time

• Must keep a linked list of pages
  – most recently used at front, least at rear
  – update this list every memory reference !!

• Alternatively keep counter in each page table entry
  – choose page with lowest value counter
  – periodically zero the counter
                                                           16
            Segmentation (1)




• One-dimensional address space with growing tables
• One table may bump into another                     17
            Segmentation (2)




Allows each table to grow or shrink, independently
                                                     18
      Segmentation (3)




Comparison of paging and segmentation
                                        19
Implementation of Pure Segmentation




(a)-(d) Development of checkerboarding
(e) Removal of the checkerboarding by compaction20
Segmentation with Paging: MULTICS (1)




 • Descriptor segment points to page tables
 • Segment descriptor – numbers are field lengths 21
Segmentation with Paging: MULTICS (2)




      A 34-bit MULTICS virtual address


                                         22
           Example Question1
• 4 page frames, page requests=0172327103
• Page Fault Rate??? For FIFO, LRU, (OPT)
FIFO                   LRU
MMMMMH H HMH           MMMMMH H HMM
0172327103             0172327103
0172333300             0172327103
 017222233              017232710
  01777722               01773271
       0111177               0111327
                                            23
               Example Question 2
Assume a process is divided into 4 equal-sized segments, and that the system
   builds a 16-entry page descriptor for each segment. Thus, the system has a
   combination of segmentation & paging. Assume also that the page size is
   4KB.
a) What is the maximum size of each segment?
b) Assume that an element in physical location 0x21ABC (in hex) is
    accessed by a thread of this process. What segment, page & offset is the
    thread trying to access?


 ANSWER:
 a) 16 * 4KB
 b) 4K = 2^12, therefore, ABC is for offset.
    16=2^4,  page 1.
    and “2” is for segment

                                                                                24
                  Example Question 3
  A computer has 32-bit virtual addresses & 4-KB pages. The program and
     data together fit in the lowest page (0-4095). The stack fits in the highest
     page. How many entries are needed in the page table if one-level paging
     is used? How many for 2-level page, with 10 bits in each part?




ANSWER:
Twenty bits are used for the virtual page numbers, leaving 12
over for the offset.
This yields a 4-KB page. Twenty bits for the virtual page
implies 2^20 pages.




                                                                                    25
               Example Question 4
A computer whose processes have 1024 pages in their address spaces keeps
   its page tables in memory. The overhead required for reading a word from
   the page table is 5 ns. To reduce this overhead, the computer has a TLB,
   which hold 32 (virtual page->physical page frame) pairs, and can do a
   look up in 1 ns. What hit rate is needed to reduce the mean overhead to 2
   ns?


ANSWER:
The effective instruction time is 1h + 5(1 − h), where h is
the hit rate. If we equate this formula with 2 and solve for
h, we find that h must be at least 0.75.




                                                                               26
                 Project 3
• Nov 7, 2008 5:00 pm
• Implement basic functions of Pthread Lib.
• Use makecontext(), getcontext(),
  setcontext(), and swapcontext().
• Useful Link:
  – http://www.opengroup.org/onlinepubs/00969
    5399/functions/makecontext.html




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