CMPT 229 - Week _2 by yurtgc548

VIEWS: 0 PAGES: 89

									CMPT 229 – Week #2
     Grant MacEwan University - Fall 2010
     Mr. Marcel Berard
Topics

     MARS (MIPS Assembly and Runtime Simulator)
     MIPS Memory Layout
     MIPS Assembly Language
     MIPS Hardware Architecture
References

   Introduction to RISC Assembly Language
    Programming:
    Chapters 1, 3 and 4
MARS

  MARS (MIPS Assembly and Runtime Simulator) is
   a JAVA program to provide a simulated MIPS
   hardware and programming IDE.

  MARS is freely available and can be downloaded
   from :
   http://courses.missouristate.edu/KenVollmar/MARS

  The version of MIPS as of Aug 2010 is 4.0. The
   examples in this course are based on V4.0.
MARS

  MARS is a complete IDE, offering a source code
   editor, an assembler and a machine simulator.

  The editor is quite basic and does not include
   features such as syntax highlighting.

  The machine simulator supports the instructions
   covered in Patterson and Hennessy's Computer
   Organization and Design.
MIPS Registers

   To understand assembly language programming, a
    person must understand the concept of a register.

   A register is a memory unit located within the CPU.
    A register can be accessed very quickly compared
    to primary memory (RAM) and somewhat more
    quickly than cache memory. It is also faster to
    perform calculations with data stored in registers.
MIPS Registers

   Some CPU instructions utilize data in registers. The
    data must be in the register prior to executing the
    instruction.

   The MIPS architecture is heavily oriented towards
    instructions that use registers.
MIPS Registers

   A CPU has some dedicated registers with a specific
    function such as PC (program counter) and IR
    (instruction register). These registers are controlled
    by the CPU.

   In addition, the MIPS architecture has a general
    purpose register file containing 32 (32-bit) registers
    that are numbered from 0 to 31. These registers
    are accessible to the programmer.
MIPS Registers

   In MIPS ASM language the general purpose
    register n is designated by $n, n being any number
    from 0 to 31.

   In addition, the registers have corresponding names
    that are more descriptive such as $t0. A table of the
    register names and their intended purpose follows.
MIPS General Purpose Registers

  Register Name Number   Usage
  $zero        $0        Constant 0
  $at          $1        Reserved for ASM
  $v0-$v1      $2-$3     Expression evaluation and results of
                         a function
  $a0-$a3      $4-$7     Argument 1-4
  $t0-$t7      $8-$15    Temporary (not preserved across
                         call, caller-saved)
  $s0-$s7      $16-$23   Saved temporary (preserved across
                         call, callee-saved)
  $t8-$t9      $24-$25   Temporary (not preserved across
                         call, caller-saved)
MIPS General Purpose Registers

  Register Name Number   Usage
  $k0-$k1      $26-$27   Reserved for the OS kernel
  $gp          $28       Pointer to sdata global area
  $sp          $29       Stack pointer
  $fp          $30       Frame pointer
  $ra          $31       Return address (used by function
                         calls)
MIPS Floating Point Registers

   The MIPS architecture also has an optional co-
    processor with 32 floating point registers $f0…$f31
    to hold numbers such as 3.459x109 in single
    precision floating point form. These registers each
    contain 32 bits.

   These registers can also be combined in pairs to
    produce 16 registers with 64 bits per register. This
    technique is used for the double precision floating
    point format.
MIPS and I/O

   The lowest level software on the (non-embedded)
    computer is the OS kernel.

   Among other things, the kernel knows the location
    and particular commands that each I/O device (or
    its driver) understands.

   An application program asks the kernel to perform
    I/O by making a system call.

   The kernel implements these system calls by
    interfacing directly with the hardware (or driver).
MIPS and I/O


                     Application
    Programs make    Programs
    system calls
    asking kernel
    to do I/O
                       Kernel
    Kernel
    controls I/O
    devices
    directly or
    Indirectly via   Hardware
    a driver.
MIPS and I/O

   MARS supports dozens of MIPS OS-like services
    available through the kernel. These notes will
    consider only the 13 most basic services (codes 1
    to 12 and 17).

   The access to these services (functions) is done
    using the instruction syscall. This instruction
    invokes a software exception.

    Example:
       li $v0, 1      # system call code for print_int
       li $a0, 5      # integer value to print
       syscall        # print the value ‘5’
MIPS and I/O

   Prior to performing the syscall instruction, the
    operation code is placed in register $v0 and any
    relevant arguments are placed in the $a registers.

   A table of the O/S services is provided in the
    following slides.
MIPS and I/O

  Service         $v0 Argument(s)                   Results
  Print integer    1   $a0 = number to be
                       printed
  Print float      2   $f12 = number to be
                       printed
  Print double     3   $f12 = number to be
                       printed
  Print string     4   $a0 = address of string in
                       memory
MIPS and I/O

  Service        $v0 Argument(s)                   Results
  Read integer    5                                number returned
                                                   in $v0
  Read float      6                                number returned
                                                   in $f0
  Read double     7                                number returned
                                                   in $f0
  Read string     8   $a0 = address of input
                      buffer in memory
                      $a1 = length of buffer (n)
  Sbrk            9   $a0 = amount                 address in $v0
  Exit           10
MIPS and I/O

  Service       $v0 Argument(s)                 Results
  Print         11   $a0 = character to print
  character
  Read          12                              character read
  character                                     in $v0
  File I/O      13
  operations     –
                16
  Exit2         17   $a0 = termination result
  (terminate
  with value)
A Simple Assembly Program

   To demonstrate MIPS programming with MARS,
    consider a simple assembly program that declares
    and prints out a zero-terminated (C style) string.
    Afterwards the program exits (returns to the kernel)
    without any result.
A Simple Assembly Program

       .data
  str: .asciiz     "Hello world!!!\n"             Data Segment

     .text
     .globl main   # exports symbol “main”
  main:
     la $a0,str    # put string address into a0
     li $v0,4      # system call to print         Text Segment
     syscall       # out a string

      li $v0,10
      syscall      # exit with no result
A Simple Assembly Program

   The ‘.data’ and ‘.text’ directives tell the assembler
    where (in which segment) to place the following
    assembled source code. Directives don’t produce
    code that is loaded into memory but rather tell the
    assembler what to do with the code.

   The zero-terminated string occupies 16 bytes of
    memory including the newline character and 0
    terminator. It is placed in the data segment and its
    starting memory location is represented by the “str”
    label.
A Simple Assembly Program

   The “main” label is similar to the “main” function in a
    C program; it represents the program entry point.

   MARS provides the option to start at “main” or to
    start at the first program instruction. The default is
    the latter. The former is useful if the programmer
    provides sub-functions before “main”.

   The ‘.globl’ directive exports the label “main” so that
    it is visible to the linker. This is useful in a multi-file
    project (with start-up code or functions other than
    “main”).
Memory Layout

   The next component at the hardware level is the
    primary memory used to hold the program code and
    data.

   In a modern computer, primary memory has at least
    one level of cache memory. Cache memory is
    faster than primary memory. The first level of cache
    memory is in the CPU. It duplicates some but not
    all of primary memory.

   Cache memory will not be considered to any extent
    in this course.
Memory Layout

   The primary memory unit in the MIPS architecture is
    byte addressable (each memory cell stores 1 byte).

   Every memory cell has an address that is
    represented by 32 bits, therefore the addresses can
    vary from 0 to the maximum allowable amount of
    memory (232-1), or in other words from 0x00000000
    to 0xFFFFFFFF.

   Note: Although MIPS memory is byte addressable,
    it is usually accessed 4 bytes at a time (= 1 word)
    on a word boundary (an address evenly divisible by
    4).
Memory Layout

  Addresses of   0x00000000   0x00
  memory         0x00000001   0xA0
  cells
                 0x00000002   0x3E
                 0x00000003   0x10
                      .        .     1 byte of data
                      .        .     per cell
                      .        .

                 0xFFFFFFFF 0x00
Memory Layout

   Systems based on MIPS processors usually divide
    the user’s memory (program’s address space) into
    four parts: the text segment, the (static) data
    segment, the heap segment and the stack segment.

   Note that the user’s address space is limited to a bit
    less than half of the overall address space.
Memory Layout

    0x7FFFFFFF
                 Stack Segment




                 Dynamic Data
                                 Data Segment
                  Static Data
    0x10000000
                 Text Segment
      0x400000
                   Reserved
Text Segment

   At the bottom of the user’s address space (address
    0x400000) is the text segment, which holds the
    program instructions.

   Note: addresses below 0x400000 are reserved for
    the operating system.
Data Segment

   Above the text segment is the data segment
    starting at (0x10000000), which is divided in three
    parts: static data, dynamic data (heap) and
    automatic data (stack).
Static Data

   The static data portion contains objects whose size
    is known to the compiler / assembler and whose
    lifetime equals the lifetime of the program.

   For instance, in C, global variables are statically
    allocated since they can be referenced anytime
    during the execution of the program.

   In Java, the global variables are the static variables
    within the class entities.
Static Data

   Static data is typically referenced by a 32-bit
    address which requires 2 instructions to process.

   The static data segment also has a 64 kB region
    that allows a memory variable to be accessed with 1
    instruction (known as the sdata segment).

   MARS does not emulate the sdata construct.
Dynamic Data

   Above the static data is the dynamic data segment
    (data allocated by the program as it executes).

   In C, for instance, the malloc (or calloc) function
    finds a new block of memory and returns a pointer
    to the first location of this block of memory; since
    the compiler can’t predict how much memory a
    program will allocate the OS expands the dynamic
    area to meet the demand.

   How is dynamic memory allocation performed in
    Java?
Stack Segment

   Above the dynamic data is the stack and it resides
    at the top of the user’s virtual address space (top
    byte address at 0x7FFFFFFF).

   The stack segment is provided as an area where:
    parameters for functions can be saved, local
    variables for functions are stored, and return
    addresses for nested function calls and recursive
    functions are stored.

   Given this stack area in memory, it is possible to
    write programs with virtually no limit on the number
    of parameters passed.
Stack Segment

   Like dynamic data, the maximum size of the
    program’s stack is not known in advance; as the
    program pushes values on the stack, the OS
    expands the stack segment down, towards the
    dynamic data segment.
MARS Memory Layout

   MARS provides extensive configurability for the
    MIPS memory layout in the Settings menu.

   This course will utilize the default MARS memory
    layout as described in previous slides.
Instruction Set

    The set of all hardware instructions that can be
     executed by a computer (also known as the
     instruction set architecture – ISA).

    Different computer designs (architectures) use
     different instruction sets, for example MIPS,
     PowerPC and the Pentium.

    Can a specific architecture be implemented by
     different computer models?

    Can different architectures run the same program?
Instruction Set

    In addition to the ISA, there is the application binary
     interface (ABI).

    The ISA is the instruction set available to the kernel.
     The ABI is the instruction set available to a user
     program.

    The user program is forbidden from using various
     (privileged) instructions in the ISA.

    However, the kernel also adds functionality such as
     syscall to the ABI that is available to the user
     program.
Instruction Set

    An important design feature of an instruction set is
     the instruction size (length).

    Some architectures have a variable instruction
     length where simple instructions have a shorter
     length and complex instructions a longer length.

    MIPS uses a fixed instruction length. Every
     instruction is 4 bytes or 32 bits (1 word). Thus,
     every instruction can be fetched with a single
     memory read operation.
Instruction Set

    There are variations of the MIPS architecture (2000,
     3000, 4000, …).

    Most of the instructions are common to all
     architectures but there are minor variations.

    The Waldron text refers to the 2000 / 3000 (MIPS I)
     instructions. This is the original (now outdated) ISA.
Instruction Set

    The newer MIPS architectures support either the
     MIPS32 or MIPS64 ISA.

    This course is based on the MIPS32 architecture. It
     is mostly upwardly compatible with MIPS I.

    MARS is based on the MIPS32 ISA.
Instruction Set

    The instructions supported by MARS are available
     in the Help menu.

    These are mostly self-explanatory but the reader
     should note that an operand with a $ sign is a
     register whereas a numerical value without the $
     sign is a literal. Labels are represented by textual
     words.
MIPS ASM Instructions

   The specification of the instructions in the text
    segment (regardless of the nature of the instructions
    themselves) follows a certain pattern:
    [label:] operation [operand1], [operand2], [operand3] [# comment]
Comments

   Comments in MIPS assembly start with the # sign.

   Everything from the start of a comment to the end of
    the line is ignored by the assembler.

   Compared to high-level languages such as C, C++
    and Java, assembly source code is more
    challenging to read and interpret, and that’s why
    comments are helpful in the source code.

   Note: Don’t comment the language, comment the
    role of the instruction.
Identifiers and Keywords

   Identifiers - sequences of characters that represent
    names (e.g., name of variables, functions and
    symbolic memory locations) in the program - can
    contain alphanumeric characters, underscores and
    dots, but they can’t begin with a digit.

   Keywords are reserved words of the assembly
    language that can’t be used as identifiers, such as
    la and li (each machine instruction has a special
    symbol or mnemonic to represent it).
Labels

   Labels are declared by putting an identifier at the
    beginning of a line followed by a colon (:).

   Labels are used as symbols to represent memory
    locations and can appear in both the text and data
    segments.

   A label in the text segment represents the memory
    location of a certain instruction.

   A label in the data segment represents a storage
    location (e.g., a variable or the start of an array).
Labels

   To illustrate, the following source code declares and
    initializes integer (word) variables A and B in the
    data segment.

         .data
    A:   .word   10
    B:   .word   20
Operation Field

   The operation field contains either an assembly
    instruction or an assembly directive.

   Each assembly instruction (e.g., li, add) is a special
    symbol or mnemonic that represents one or more
    machine language instructions.

   The basic assembly instructions have a one-to-one
    relationship with machine language instructions.
Operation Field

   There are also assembly macro instructions
    (pseudo or synthetic instructions) where a macro
    instruction is mapped to one or more machine
    language instructions.

   Two example macro instructions are li (load
    immediate) and la (load address) presented in the
    first example program.

   The li instruction maps into one hardware
    instruction (adding 0 to the immediate value of 4).
Operation Field

   The la operation maps into 2 hardware instructions.

   When a synthetic operation maps into 2 hardware
    instructions, it often requires a temporary location in
    which to store the result of the first instruction. This
    location is the $at (assembler temporary) register.
    This register is off-limits for the user program.

   Support for the pseudo instructions can be switched
    on or off in MARS via the Settings menu. This
    support is on by default and will always be left on.
Operation Field

   Assembly directives are not assembled into
    machine language instructions. They produce no
    executable code.

   For instance, the .data directive just tells the
    assembler to place the code from the lines that
    follow in the data segment.

   Following the data directive is a declaration of a C
    style string (.asciiz “abcde”). This declaration
    initializes the string in memory at program start.
Load and Store Instructions

   The MIPS architecture is a Load/Store
    Architecture, which means that the only
    instructions that access main memory for their
    operands are the load and store instructions. This
    enables some efficiencies as will be discussed later.

   Therefore, all of the other instructions work entirely
    with operands in the general purpose register file.

   Some basic MIPS instructions are given in the
    following slides.
la*

      la Rdest, address

      Load the numerical (integral) value of address into
      register Rdest. The address is a primary memory
      location represented by a label and is determined by
      the assembler. Eg.

         la $a0, str # puts address ‘str’ into register $a0

      Note: la is a macro instruction.
la*

            Processor     Memory
                          0x10010000
                          0x10010001
      $t0                 0x10010002
                          0x10010003
                          0x10010004
      $t1
                          0x10010005
                          0x10010006
                          0x10010007
      $t2
                          0x10010008
                          0x10010009
                 .        0x1001000A
                 .        0x1001000B
                          0x1001000C
      la, load address,   0x1001000D
      puts an address     0x1001000E
      into a register     0x1001000F
li*

      li Rdest, imm

      Move the immediate imm into register Rdest. Eg.

        li $v0,4    # copies ‘4’ into register $v0

      Note: the term immediate means that the processor
      extracts the value from the instruction itself (a
      constant value) and not from the memory.

      The li instruction is also a macro instruction.
li*

            Processor          li $t1,3   Memory
                                          0x10010000
                                          0x10010001
      $t0                                 0x10010002
                                          0x10010003
                                          0x10010004
      $t1
                                          0x10010005
                                          0x10010006
                                          0x10010007
      $t2
                                          0x10010008
                                          0x10010009
                 .                        0x1001000A
                 .                        0x1001000B
                                          0x1001000C
      li, load immediate,                 0x1001000D
      puts a value from                   0x1001000E
      an instruction into a register      0x1001000F
li*

      The integer immediate imm can be specified in
      various ways.

        li $v0, 4         # decimal integer
        li $t0, 0x22      # hex integer
        li $s1, ‘A’       # ASCII code

      The newline character is equivalent to 10 decimal or
      0x0A hexadecimal. The carriage return is 13 decimal
      or 0x0D hexadecimal.
lw

     lw Rdest, address

     Load the 32-bit contents (word) at address into
     register Rdest. (Accesses primary memory; note
     address must be word aligned.)

     The address is typically specified by a label where the
     label represents an integer (word).

       lw $t1, A
lw

           Processor          Memory
                              0x10010000
                              0x10010001
     $t0                      0x10010002
                              0x10010003
                              0x10010004
     $t1
                              0x10010005
                              0x10010006
                              0x10010007
     $t2
                              0x10010008
                              0x10010009
                .             0x1001000A
                .             0x1001000B
                              0x1001000C
     lw, load word,           0x1001000D
     copies a word from       0x1001000E
     memory into a register   0x1001000F
lb

     lb Rdest, address

     Load the byte content at address into register Rdest.
     The byte is sign-extended by the lb instruction.
     (Accesses primary memory; address alignment?)

     The address is typically specified by a label where the
     label represents a byte (or character).
lb

           Processor          Memory
                              0x10010000
                              0x10010001
     $t0                      0x10010002
                              0x10010003
                              0x10010004
     $t1
                              0x10010005
                              0x10010006
                              0x10010007
     $t2
                              0x10010008
                              0x10010009
                .             0x1001000A
                .             0x1001000B
                              0x1001000C
     lb, load byte,           0x1001000D
     copies a byte from       0x1001000E
     memory into a register   0x1001000F
sw

     sw Rsrc, address

     Store the word from register Rsrc at address.
     (Accesses primary memory; word alignment required.)

     The address is typically specified by a label where the
     label represents an integer (word).

       sw $t1, A
sw

           Processor               Memory
                                   0x10010000
                                   0x10010001
     $t0                           0x10010002
                                   0x10010003
                                   0x10010004
     $t1
                                   0x10010005
                                   0x10010006
                                   0x10010007
     $t2
                                   0x10010008
                                   0x10010009
                .                  0x1001000A
                .                  0x1001000B
                                   0x1001000C
     sw, store word,               0x1001000D
     copies a word from a          0x1001000E
     register into a memory cell   0x1001000F
sb

     sb Rsrc, address

     Store the byte from register Rsrc at address.
     (Accesses primary memory.)

     *These are the 4 instructions used in this course that
     access primary memory.
sb

           Processor                Memory
                                    0x10010000
                                    0x10010001
     $t0                            0x10010002
                                    0x10010003
                                    0x10010004
     $t1
                                    0x10010005
                                    0x10010006
                                    0x10010007
     $t2
                                    0x10010008
                                    0x10010009
                .                   0x1001000A
                .                   0x1001000B
                                    0x1001000C
     sb, store byte,                0x1001000D
     copies the lower byte from a   0x1001000E
     register into a memory cell    0x1001000F
Arithmetic Instructions

    Arithmetic instructions use various terminologies for
     the operands. An operand starting with R is strictly
     a register. An operand starting with Imm is strictly
     an immediate (constant) value. An operand starting
     with Src is either a register or an immediate
     operand. For example:

          add Rdest, Rsrc1, Src2

   The operands ‘Rdest’ and ‘Rsrc1’ must be registers.
   ‘Src2’ means that this operand can be either a register
   or an immediate.
Arithmetic Instructions

    Many arithmetic and logic instructions can take two
     or three operands. The two operand version is a
     macro expanded by the assembler.
         add Rdest, Rsrc1, Src2
     means
         Rdest = Rsrc1 + Src2
     whereas
         add Rdest, Src
     means (for some environments, but not MARS)
         Rdest = Rdest + Src
Arithmetic Instructions

    Several arithmetic operations also have two
     variations (without overflow {u} and with overflow).

    The without overflow variation never generates an
     overflow error. For example 0x80000000 +
     0x90000000 produces the sum 0x10000000.

    The with overflow variation assumes that the
     operands are signed integers with the range
     0x80000000 to 0x7FFFFFFF. A sum (or difference)
     outside of this range produces an overflow error.
Addition

  addiu Rdest, Rsrc1, Imm
    Put the sum of the integers from register Rsrc1 and
    Imm into register Rdest (Addition immediate
    without overflow)

  addi Rdest, Rsrc1, Imm
    Put the sum of the integers from register Rsrc1 and
    Imm into register Rdest (Addition immediate with
    overflow)
Addition

  addu Rdest, Rsrc1, Src2
    Put the sum of the integers from register Rsrc1 and
    Src2 into register Rdest (Addition without overflow)

    Equivalent to addiu if Src2 is an Imm.

  add Rdest, Rsrc1, Src2
    Put the sum of the integers from register Rsrc1 and
    Src2 into register Rdest (Addition with overflow)

    Equivalent to addi if Src2 is an Imm.
Subtraction

  subu Rdest, Rsrc1, Src2
    Put the difference of the integers from register
    Rsrc1 and Src2 into register Rdest (Subtract
    without overflow)

  sub Rdest, Rsrc1, Src2
    Put the difference of the integers from register
    Rsrc1 and Src2 into register Rdest (Subtract with
    overflow)

  There are also subiu and subi variations.
Multiplication

    Multiplication differs from addition and subtraction in
     that the product of two 32 bit numbers can be as
     large as 64 bits. For this reason, in a 32 bit
     architecture, there should be two registers to
     receive the product.

    The MIPS processor has a pair of special purpose
     registers called hi and lo designed to receive the
     product of a multiplication.
Multiplication

   mult Rsrc1, Rsrc2
    Multiply the contents of the two (signed) registers.
    Place the low-order word of the product in register
    lo and the high-order word in the register hi

   multu Rsrc1, Rsrc2
    Multiply the contents of the two (unsigned) registers.
    Place the low-order word of the product in register
    lo and the high-order word in the register hi
Multiplication

    Special move instructions copy data from general
     registers (r0…r31) to/from lo and hi

   Example:

     mult $t4, $t3     # hi, lo = $t4 * $t3 (signed)
     mflo $t1          # $t1 = lo
     mfhi $t2          # $t2 = hi
Multiplication

   Some pseudo-instructions simplify multiplication.
   These instructions produce a mult or multu into hi/lo
   and then move data from lo.

   mulo Rdest, Rsrc1, Src2
    Put the product of the integers from register Rsrc1
    and Src2 into register Rdest (Signed multiply with
    overflow)
   mulou Rdest, Rsrc1, Src2
    Same description except unsigned multiply.
Division

    An integer division, like multiplication can use 64
     bits for its results. There is potentially a 32 bit
     quotient and a 32 bit remainder.

    The hi and lo registers are also used for division.
Division

   div Rsrc1, Rsrc2
     Divide the contents of the two (signed) registers
     with overflow. Leave the quotient in register lo and
     the remainder in register hi. Note that if an operand
     is negative, the remainder is unspecified by the
     MIPS architecture and depends on the conventions
     of the machine on which MIPS is run.

   divu Rsrc1, RSrc2
     Same as above except that the registers are viewed
     as unsigned values and there is no overflow.
Division

    Again, data can be moved to the general purpose
     registers (r0…r31) to/from lo and hi.

   Example:

     div $t4, $t1     # hi,lo = $t4 / $t1
     mflo $t4         # $t4 = lo -> result
     mfhi $t3         # $t3 = hi -> remainder
Division

   As with multiplication, there are various macros to
   simplify division.

   div* Rdest, Rsrc1, Src2
     Put the quotient of the integers from register Rsrc1
     and Src2 into register Rdest. Can generate an
     overflow error.

   divu* Rdest, Rsrc1, Src2
     As above but unsigned and no overflow error.
Division

   As with the quotient, there are various macros to
   obtain the remainder.

   rem* Rdest, Rsrc1, Src2
     Put the remainder of the integers from register
     Rsrc1 and Src2 into register Rdest. Can generate
     an overflow error.

   remu* Rdest, Rsrc1, Src2
     As above but unsigned and no overflow error.
Register Copying

   To copy data from one register to another use the
    move macro instruction. Its syntax is:

        move Rdest, Rsrc

   This macro is equivalent to:

        addu Rdest, $0, Rsrc
The nop Instruction

   There is a null operation called nop. It performs no
    operation but consumes the time needed to perform
    an instruction.

   Applications of nop will be considered in future
    weeks.
MIPS Hardware Architecture

   This chapter has considered two of the basic
    components of a computer, the CPU and primary
    memory. A longer list of components (given below)
    can be provided by considering functional portions
    of the CPU:
      Control unit
      Program counter
      Instruction register
      ALU
      Register file
      Primary memory
MIPS Hardware Architecture

   The program counter (PC) is a specialized CPU
    register that contains the (unsigned) address of the
    next instruction to be executed. This address is
    always word aligned (evenly divisible by 4). The PC
    is shown in the MARS simulator.

   The instruction register (IR) is also a specialized
    CPU register that contains a copy of the current
    instruction being executed. It is not shown in the
    MARS simulator.
MIPS Hardware Architecture

   The control unit (CU) is a part of the CPU that
    controls the entire computer. It fetches and
    executes the program instructions.

   The arithmetic and logic unit (ALU) is the other part
    of the CPU. It performs calculations under the
    directions of the CU.

   In the MIPS architecture, the ALU operands always
    come from the register file, never from primary
    memory.
MIPS Hardware Architecture

   Buses connect all these functional components.

   A bus is nothing more than a set of electronic
    conducting paths over which different sets of binary
    values are transmitted.

   Most of the buses in the MIPS architecture are 32
    bits wide. This is the size of a word in MIPS.

   A simplified diagram of the MIPS hardware
    architecture is given on the next slide.
MIPS Hardware Architecture
Exercises

  1.   Write a MIPS assembly program that will read a
       temperature in Celsius, convert it to Fahrenheit
       and print the result. The expression that converts
       Celsius in Fahrenheit is given below:

                      F = 9/5 *C + 32

       Note: Assume that only integers are used for
       these exercises.
Exercises

  2.   Write a MIPS assembly program that will read an
       integer (x) and print the result of the expression
       below:
                       A*x2 + B*x + C
       Where,
       A=3
       B=4
       C=5

								
To top