CECS 340 – Discrete Event System Simulation Computer Engineering and Computer Science Department Professor Ebert Lab Exercise #1: The Full Adder (Originally Authored by Tom Johnson) Suggested Time: 1 lab meeting Getting Started with SignalScan: 1. Each time you sit down to a PC terminal in ECS405, you must follow Steps 1 to 3 in order to access the Cadence Tools. Step 1: Log on to your PC. Step 2: Use ReflectionX to access cadence server via method TELNET (not OPENSSH): Click on “cadence.rxc” in LHPane and login. You can change the connection method from OPENSSH to TELNET before you login. Step 3: After logging on to the SunOS server, enter the command: “source /Cadence_Tools/user_setup/cadence.init” and answer “y” to all questions. This initializes your session on the Cadence server and allows access to Cadence Tools. Step 4: Please read the last page to find out about logging onto Cadence from a UNIX lab also. 2. Check if everything is OK and do a little organization: (a) Enter the command: “verilog” to see if you have access to the Verilog software. The response should NOT be that the Verilog tools are unavailable! If so, check that you have done Step 3 correctly. If problem persists, see the instructor. (b) At this point, create a directory for your CECS 340 files by typing: “mkdir cecs340” (c) Change to the new directory by typing: “cd cecs340” (d) Now you are in a position to create and compile Verilog files which all should be found in the cecs340 directory. This bookkeeping step is for your convenience. Using any text editor, you can create ASCII text files containing Verilog code, e.g. lab_1.v, and compile it type typing: “verilog lab_1.v” in the window. It is as simple as that. Of course the lab_1.v file must have viable Verilog source code in it for the compiler. 3. To get comfortable with the Cadence environment, practice by creating this text file consisting of a Verilog module of a full adder and a simple test bench to drive the module with various inputs and monitor its response. The test bench is used to confirm correct simulation of the device under test (DUT) which in this case is the full adder model. //LAB_1: The Full Adder //(Your name goes here!) //March 3, 2004 //HEADER module FULL_ADDER (X,Y,Z,S,C); //DECLARATIONS input X,Y,Z; // inputs to full adder output S,C; //outputs of full adder reg S,C; //LHS of equality in procedural block must be type reg //FUNCTIONALITY (structural) always @ (X or Y or Z) begin //if X,Y, or Z changes, the next statement is executed S = X^Y^Z; C = X&Y | X&Z | Y&Z; /* Could also do this behaviorally: {C,S} = X + Y + Z; //Concatenation operator “{}” makes vector out of separate bit elements */ end endmodule //The TEST BENCH module TEST; reg X,Y,Z; //inputs are type reg wire S,C; //outptus are type wire integer i; FULL_ADDER fa (X,Y,Z,S,C); //instantiate the DUT initial begin //apply the inputs for (i=0; i<=7;i=i+1) #5 {X,Y,Z} = i; //Easy way to get all combinations of inputs spaced 5 time units apart #5 $finish; //Wait an additional 5 time units then halt processing and go back to the shell end //Format the tabular output initial $monitor("T=%0d \tX=%b Y=%b Z=%b {C,S}=%b%b", $time,X,Y,Z,C,S); endmodule
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Upon compiling this code by typing “verilog lab1.v”, the TABULAR output from the test bench should give these results on the screen: TEST BENCH OUTPUT T=0 X=x Y=x Z=x {C,S}=xx NOTE: Here the signals are as yet UNDEFINED T=5 X=0 Y=0 Z=0 {C,S}=00 NOTE: The first input 0,0,0 is at t=5 T=10 X=0 Y=0 Z=1 {C,S}=01 NOTE: All following inputs/outputs are spaced T=15 X=0 Y=1 Z=0 {C,S}=01 5 time units (ticks) apart T=20 X=0 Y=1 Z=1 {C,S}=10 T=25 X=1 Y=0 Z=0 {C,S}=01 T=30 X=1 Y=0 Z=1 {C,S}=10 T=35 X=1 Y=1 Z=0 {C,S}=10 T=40 X=1 Y=1 Z=1 {C,S}=11 Note the inputs are spaced at 5 ns intervals, the (x,y,z) 2 values form the ROWS of the full adder truth table with C and S being the outputs. This table validates the Verilog model design since it is a truth table for a full adder. This section of the TEST BENCH could use a $display directive instead (or in addition to) the $monitor statement. The format of the $display instruction is the same as $monitor; the difference is that the $display instruction is output every time the instruction is encountered in the execution, whereas $monitor is sensitive to the list of parameters to output. Also only one $monitior statement may appear in a given Verilog simulation, but any number of $display instructions may be present. initial begin //apply the inputs for (i=0; i<=7;i=i+1) begin #5 {X,Y,Z} = i; //Easy way to get all combinations of inputs spaced 5 time units apart $display("T=%0d \tX=%b Y=%b Z=%b {C,S}=%b%b", $time,X,Y,Z,C,S); end #5 $finish; //Wait an additional 5 time units then halt processing and go back to the shell end This code segment would print out the values of X,Y,Z and {C,S} every time the loop is executed. The results would be the same as the $monitor output in this case. This is not always true, because the $monitor statement is sensitive to CHANGES in the output parameter list. If no change is seen, the $monitor output remains inactive. The $display statement is useful for generating tabular output when you want to and a good tool to use for debugging.
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In addition to tabular output that is generated with the $monitor (or $display) directives, you can also produce graphical output using the Cadence tool “signalscan”. This produces a trace of the simulation by keeping a history of the changes in all the variables selected as the simulation progresses and then displaying them pictorially. To use this graphical display, you must include several new lines of code in the TEST BENCH. These additional lines are shown in bold lettering in the code below: //The SIGNAL SCAN TEST BENCH module TEST; reg X,Y,Z; wire S,C; integer i; FULL_ADDER fa (X,Y,Z,S,C); initial begin $shm_open(“lab_1.shm”); //Name of signal scan output directory $shm_probe(“AC”); //Indicate that you want to capture ALL the variables for (i=0; i<=7;i=i+1) #5 {X,Y,Z} = i; #5 $finish; $shm_close(); //Close any open files before ending session end initial $monitor("T=%0d \tX=%b Y=%b Z=%b S=%b C=%b", $time,X,Y,Z,S,C); endmodule
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Compile the signalscan test bench and the module for the full adder. You’ll notice that a new directory was created, lab_1.shm, whose contents is the information needed to make the signal scan trace. To invoke the signal scan trace, type the following command at the prompt: “signalscan lab_1.shm” This should open a new window that looks like the one shown in Fig. 1. By clicking on the DesBrows:1 button in the upper right, you can access various signals that have been captured. The signals are presented in an hierarchical structure with the module name shown along with the variables that can be viewed. This is shown in Fig. 2 below. Clicking on TEST in the “Instance in current context” window will show you the variables that can be found in the
module TEST (the test bench). In Fig. 3 we see the “Current Instance” is TEST the TOP module of the hierarchy, the “Instance in current context” is fa, the instantiation of the full adder module in the TOP module TEST, and a list of signals that shown in the “Variables/Nodes in curren context” window. These variables can be selected by clicking on them one by one, or by holding the mouse button down and dragging the highlight over a collection of them. They then will appear in the rectangular box on the left. These signals will show up on the trace when you click the “AddToWave” button. Using the “GetDeepAll” will put all the signals in the simulation on the trace which may be very confusing if there are a lot of signals in a lot of modules in your design. It is quick but is often of little use, so think what you want to do and want to see before you add lots of signals on the trace. You can delete a signal by using the highlighting the signal and using the “Cut” button. Selecting all the variables shown and clicking on the “AddToWave” button gives the results seen in Fig. 4. The variable i is a 32-bit (8 hex digit!) value used as a counter. The simulation starts at t=0 with the signal variables being UNDEFINED, and ends at t=18. You can zoom in or zoom out to examine the trace elements. You can change the format of the variables from binary to hex or decimal by using the “Format” button at the top of the screen. Experiment with the features on the signal scan screen.
Figure 1 – A signal scan window
Fig. 2 – The signal scan window after clicking on the DesBrows:1 button
Fig. 3 – The display showing the modules and signals available for graphical output
Fig. 4 – A signal scan output showing a sample trace of variables You can print the signal scan screen by clicking on the “File” button and choosing “PRINT”. Click on the HEADER INFO button to include a heading with information such as the Title, Date, Author, etc. as in Fig. 5. Click on the DESTINATION button, and choose “FILE NAME”. Give the file a name such as “lab1.ps”. It must end in “.ps”, a postscript file. Other buttons allow you to select the time range to print, or the number of variables to print, etc. When finished with you selections, click on “OK”, and a file lab1.ps will be created. Now print out the file lab1.ps to get a hardcopy. You cannot print from the cadence server !!!!!! The best procedure is to go back to your DESKTOP, click on the START button, search through the available programs until you find GHOSTGUM. In GHOSTGUM, open up GSView4.4. Using the FILE option in GSView, open up the file you have created in signal scan. The signal scan output should appear on the screen. Then print out this file using the PRINT option in the FILE menu of GSView. The default printer should be the one in ECS405, and you should be able to pick up your signal scan output soon thereafter. NOTE: You must have printing privilege to be able to use the printer. Check your DESKTOP for the PaperPrivilege ICON to find out your status and how to obtain printing privileges.
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Fig. 5 – HEADER INFO button window when printing out signal scan data
Fig. 6 – DESTINATION button window when printing out signal scan data