EASTERN MEDITERRANEAN UNIVERSITY Faculty of Engineering Department of Computer Engineering
Q 3) Consider the datapath and the control of single-cycle MIPS subset implementation supporting R-type, beq and lw and sw instructions is given below:
CMPE 325: Computer Architecture II Final Exam SOLUTIONS
Date: 5 / 1 / 2005 Instructors: Asst. Prof. Dr. Mehmet BODUR (Gr. 1) Time Allowed: 140 min. Prof. Dr. Evgueni Doukhnitch (Gr. 2 & 3 ) Dr. Cem Ergün (Gr 4 & 5) Q1 [10 pts] Write the MIPS code of the following C program segment: int a[10]; addi $1,$0,100 # address a[ ] int s; addi $2,$0, 200 # address s sw $0,0($2) s=0; #for structure for (i=1; i<=9; i++) addi $4,$0,1 s=s+i*a[i]; forloop: slti $5,$4,10 beq $5,$0,forexit lw $3,0($2) sll $5,$4,2 # $5 is i*4 Use: add $5,$5,$1 # $5 is address of a[i] $1 for an address of lw $5,0($5) # $5 is value of a[i] “a” starting from 100; mul $5, $4,$5 # $5 is i*a[i] $2 for an address of add $3, $3,$5 # value of s “s” at 200; sw $3, 0($2) # value of s in memory $3 for value of “s”; addi $4,$4,1 # i++ $4 for index “i”. j forloop forexit: You must leave the result in memory location assigned for “s”. You may use pseudocode instruction like mul$1,$2,$3 for multiplication. Q2) [7 points] Suppose that $10 and $15 contains the following 32-bit binary data $10= 1111 1111 1111 1111 1111 1111 1001 0110 = –106 signed or 4294967190 unsign. $15= 0000 0000 0000 0000 0000 0000 0001 0001 = 17 What is the value of register $20 after execution of (each is 1 point): i) sra $20, $10, 5 $20 = 0xFFFF FFFC
$20= 1111 1111 1111 1111 1111 1111 1111 1100
1 0
s
y
0 s y 1 1 s y 0
1 s y 0
a) [10 pts] To perform R-type, beq and lw and sw instructions, specify the control signals for the following table.
Control Signals RegDst RegWrite ALUSrc MemRead MemWrite MemToReg Branch (for PCSrc) ALUOp R-type 0 1 0 0 0 0 0 10 beq x 0 0 0 0 x 1 01 lw 1 1 1 1 0 1 0 00 sw x 0 1 0 1 x 0 00
b) [8 pts] Design a main control unit with a PLA to support R-type, beq and lw and sw operations with the given opcodes for R-type ‘0’, beq ‘4’, lw ‘35’ and sw ‘43’.
ALU.zero Opc5 Opc4 Opc3 Opc2 Opc1 Opc0 Inputs
ii) lui iii) srl
$20, 20 $20, $10, 3
$20 = 0x0014 0000 $20 = 0x8FFF FFF2 $20 = 0x0000 0000 $20 = 0x0000 0000 $20 = 0x0000 0001 $20 = 0x0000 0001 1
$20 =0000 0000 0001 0100 0000 0000 0000 0000 $20 = 0001 1111 1111 1111 1111 1111 1111 0010
iv) sltu $20, $10, $15 4294967190 ≥ 17 ⇒ $20=0 v) sltiu $20, $10, 20 4294967190 ≥ 20 ⇒ $20=0 vi) slti $20, $10, -20 –106 < –20 ⇒ $20=1 vii) slt $20, $10, $15 –106 < 17 ⇒ $20= 1
RT
lw
sw
beq
Outputs RegDst RegWrite ALUSrc MemRead MemWrite MemtoReg Branch/PCSrc / ALUOp1 ALUOp0
2
Q4) [6 pts] Consider the following 1-bit ALU and find the ALU functions PCWriteCond Op signals binv op1 op0 0 0 0 0 0 1 0 1 0 0 1 1 1 0 0 1 0 1 1 1 0 1 1 1 1-bit ALU function r =a and b r = a or b co,r=ci+a + b r =a xor b r =a and b' r =a or b' co,r=ci+a – b r =a xor b' to the OR gate bne
0 1 mux zero
Cin
0 1 MUX
Cout
the old zero line from ALU
b) [15 pts] Draw the bne path of FSM chart describing also additional control signals: Q5) The datapath and control of the multi-cycle MIPS subset implementation supporting R-type instructions (add, sub, and, or, slt), lw, sw, beq, jr, and j instructions is given below.
IorD PCWriteCond MemRead MemWrite IRWrite RegDst MemtoReg OpCode
Main Control Unit
PCWrite PCSource TargetWrite ALUop ALUselA ALUselB RegWrite
IorD=0 MemRead IRWrite ALUSelA=0 ALUSelB=01 ALUOp=00 PCSrc=00 PCWrite
addr
MRd MWrt
26
shift left 2 RegWrt read.reg1 read data 1 read.reg2 Mux 0 out 1 Mux 00 out 01 10 Mux 0 out 1 11
Target Register
Mux 00 out 01 10
IRWrt
rs rt
PC
Mux 0 out 1
zero ALU
11
ReadData Address
Instructin
rt
WriteData Program Mem. Instruction Register.
Mux 0 out 1
Register File read data 2 write.reg write data
rd
4
ALU Control
ALUSelA=0 ALUSelB=11 ALUOp=00 TargetWrite
imm 16 funct
sign extend
shift left 2
a) [10 pts] The branch-if-not-equal (bne) instruction may be supported by the datapath given above. Show the additional units, control signals and needed connections that you want to add to execute this instruction.
ALUSelA=1 ALUSelB=00 ALUOp=01 PCSrc=01 PCWriteCond bne=1
3
4
Q6 a) [5 pts] Identify all data dependencies in the following code, assuming that we are using the 5-stage pipelined datapath. Which dependencies can be resolved via forwarding? add $2,$5,$4 add $4,$2,$5 sw $5,100($2) add $3,$2,$4 Answer The second instr. is dependent upon the first (because of $2) The third instr. is dependent upon the first (because of $2) The fourth instr. is dependent upon the first (because of $2) The fourth instr. is dependent upon the second (because of $4) ∴ All these dependencies can be solved by forwarding
Q8 [4 pts] a) Under what circumstances is microprogrammed control design preferred vs. finite-state control design?
If the instruction set is very large
b) [5 pts] Consider executing the following code on the 5-stage pipelined datapath: Which registers are read during the fifth clock cycle, and which registers are written at the end of the fifth clock cycle? Consider only the registers in the register file (i.e., $1, $2, $3, etc.)
b) [3 pts] Considering the single-cycle and multi-cycle datapath control which control unit requires memory elements in implementation ?
add $1,$2,$3 add $4,$5,$6 add $7,$8,$9 add $10,$11,$12 add $13,$14,$15
Answer Registers $11 and $12 are read during the fifth clock cycle. Register $1 is written at the end of fifth clock cycle.
Control unit for multi-cycle implementation
[3 pts] Why?
Q7 [10 pts] Multiply two single-precision float numbers and write single-precision float product C=A×B: Because this control unit is a sequential circuit A=0x3FE00000, B=0xC0800000 A=0 01111111 11000…0=1.75×2 0 B=1 10000001 00000…0= –4×20 C= –7= –1.112 ×22 Single-precision product = 0xC0E00000 c) [4 pts] For a given single-cycle datapath write the names of the additional registers to implement the multi-cycle datapath.
Instruction register and Target register.
5
6