History-based VLSI Legalization
using Network Flow
Minsik Cho, Haoxing Ren, Hua Xiang, Ruchir Puri
Introduction & Contribution
Network Flow Formulation
Conclusion & Future Work
The high density of design in a chip affects the entire physical
Take care of placement can reduce the complexity of the
buffering, gate sizing, routing, etc.
The main goal of placement
Locate all the objects without overlap
Satisfying each kinds of design objectives.
Legalization is an important step between global and detail
placement to remove all the overlaps with minimum
perturbation or impaction.
A novel gate-centric MCMF formulation
Optimize the deviation for each gate better
History scheme can be integrated smoothly
Incorporate a history-based technique into a new
network flow formulation
Propose efficient techniques to realize a flow into gate
movements based on a Subset-sum problem
A rectangle chip is partitioned into equal-sized circuit
rows, and each row is further divided into block-free
The Manhattan distance between these two positions is
defined as deviation
Problem Formulations (cont)
Average weighted sum
Base on network flow, how to set the sources and sinks
by this formula?
Set all the gates in one of overflow regions as sources, other
regions as sinks.
How to solve that general network flow cannot model
discrete sizes of gates?
Using unbounded or maximum width size of gate as limit of
flow and do the Flow Realization.
How to calculate the deviation of the y-value?
Using the center Yr+Wr/2 to evaluate the deviation, and do
the Region Placement.
Example: Compare Flow and Greedy
Step 1: Network Flow
Might move partially
Times of history failed
Step 2: Flow Realization
There is a partial flow from A to the empty space
Solve Subset-sum problem(NP class)
Partition into two set and fit the
regions with cheapest solution.
We set the size solution T < λ
Control the bounded flow and λ
can reduce run time.
It returns Failure if the problem
Step 3: Region Placement
Find y-value of all gates in a region for minimum deviation
Order the gates according to the center location (xi, yi+wi/2)
rather than (xi, yi), and it provides the less deviation according
In case of overflow region, we temporarily scale down wi with
Wr/Or, just make placement fesiable.
Solve this problem by single row placement refer to [3,4,7, 11].
Step 4: History Learning
To avoid unrealizable flow, increasing the history factor
h[wi][r][p] for the cost expensive enough.
Success flow on
the 5th iteration
Post-Optimization & Speedup
When we get a legal solution, it is possible that some gates
have large deviation.
Greedily move gates toward their initial position.
Using Flow Realization with zero flow
The complexity of network flow is:
Boundle tightly coupled gates if the total width less than maximum
width in library, it can reduce |I| effectively.
In most case, a gate migrates to the nearby regions, we can
insert the edges by user defined. (reduce |E|)
Using hierarchical approach to reduce |R|.
Implement in C++
2.4GHz Linux machine with 4G RAM
NTUPlace3-LE, FastPlace3, Dragon2006, BonnL
45nm with mixed-sized blockages and fixed gates
From the industrial global placer
Wire length optimization
Experiment Results (cont)
Failure rate comparison
Experiment Result (cont)
Compare QoR with NTUPlace
Conclusion & Future Work
Using History-based MCMF to solve the general
problems cannot solve by normal MCMF.
Simultaneously legalization often get better QoR.
Using the history-based technique
The assignment problem with the in-flow of a souce more than
The cost of SA-based problem.
By solving the Subset-sum problem
We can solve network flow out of bound to get more