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					HEP2005 International Europhysics Conference on High Energy Physics
                                 ( Lisboa-Portugal, 21-27 July 2005 )



Readout Electronics for the ALICE Time Projection Chamber

                                   Roberto Campagnolo – CERN PH-ED




           Outline:
           • The ALICE TPC FEE Design Requirements
           • Overview of the main Components
           • Measurements
           • Conclusions

 HEP2005, Lisboa 21-27 July 05           Roberto Campagnolo - CERN      1
               The ALICE Time Projection Chamber layout
                                                                                       GAS VOLUME: 88 m3
                                                                                        90% Ne - 10%CO2
                                                      E
                                  E
                                400 V / cm




                                                                    LARGE DATA VOLUME :
                                                                    • 570 132 (pads) x 1000 (time bins)
READOUT PLANE SEGMENTATION :                                        • 712 Mbytes / event
    18 trapezoidal sectors per side                                 • Pb – Pb (@200 Hz)  142 Gbyte / s
each covering 20 degrees in azimuth                                 • p-p     (@1KHz)       712 GByte / s

HEP2005, Lisboa 21-27 July 05           Roberto Campagnolo - CERN                                         2
                   ALICE TPC FEE – Design Requirements


             No. of channels :                                           570 132
              ( 1 MIP = 4.8fC , S/N = 30:1 , Dynamic = 30 MIP )

             Dynamic range :                                             10 bits

             Sampling rate (shaping time ~ 190ns) :                      10 MHz
             No. samples / channel (drift time ~88 µs):                  1000

             Zero suppr. data (<occ.> = 15%) :                           108 MByte / event
             L1 (start digitization) rate:                               ~ 200 Hz

             Tail cancellation within 1 ms (minimize pile-up) :          ~ 1‰

             Power consumption (detector ΔT =± 0.1 ºC ) :                < 100 mW / channel

             Tolerance to Radiation Single Event Effects




HEP2005, Lisboa 21-27 July 05                 Roberto Campagnolo - CERN                        3
       ALICE TPC Readout organization and components

                                Outer chamber                 P6 : 20 FECs

                                                              P5 : 20 FECs

                                                              P4 : 20 FECs
                                        FEC
       36 Sectors,                                            P3 : 18 FECs
     6 Partition each
                                Inner chamber                 P2 : 25 FECs

                                                              P1 : 18 FECs




HEP2005, Lisboa 21-27 July 05                   Roberto Campagnolo - CERN    4
                  ALICE TPC Readout organization and components

                                           Outer chamber                   P6 : 20 FECs        Example of Partition equipped with
                                                                                               FECs, Readout Backplane and RCU
                                                                           P5 : 20 FECs

                                                                           P4 : 20 FECs
                                                   FEC
                  36 Sectors,                                              P3 : 18 FECs
                6 Partition each
                                           Inner chamber                   P2 : 25 FECs
              PASA – ADC – DIG.
                                                                           P1 : 18 FECs

                              Up-to 25
              128 ch-FEC
                                                      Partition Architecture :
                                  14
DETECTOR




              128 ch-FEC                                                ON DETECTOR            COUNTING ROOM
                                  13
              128 ch-FEC                                                         SIU int.     Detector Data Link       Data Acquisition
                                                        ALTRO                   (DDL-SIU)        ( 200 MB / s )
                                                          Bus        Data                                                   RORC
                                                       Interface   assembler
                                                                                                   Ethernet
                                  12
                                                         Slow                    DCS int.         ( 1 MB/s )        Detector Control System
              128 ch-FEC
                                                        Control
                                                       Interface               Trigger int.    TTC optical Link          Timing, Trigger
                                   2
                                                                   RCU          (TTC-RX)      (Clock, L1 and L2 )          and Control
              128 ch-FEC
                                  1               Local Slow-Control (2 x 2Mb/s)
              128 ch-FEC
                                                ALTRO bus (2 x 200 MB/s)

           HEP2005, Lisboa 21-27 July 05                   Roberto Campagnolo - CERN                                                   5
                    The ALICE TPC Front End Card (4356 units in total)
                                                                8 PASA CHIPS           8 ALTRO CHIPS
                                                                ( 16 CH / CHIP )       ( 16 CH / CHIP )




                                                                                                                                          GTL bus-transceivers
                               Pad plane



DETECTOR


drift region
                                                                                                                               Board
                                               128 Channels


    88ms                                                                                                                     Controller




                                                                                                                                                                 19 cm
                                                                                                                              (FPGA)
 gating grid




                                                                                                 Digital           Multi
                                                              Pre-Ampli      10Ms/s
                                                                                                 Circuit           event
                                                               Shaper       10bitADC
                       anode                                                                                       buffer
                        wire


                                                                                   Baseline correction, Tail Cancellation,
 570132 PADS                                                                                  Zero supression



                                                                                                                             Board Supply
                                                                                                                                 And
                                                                                                                              Monitoring



                                                                                                     17 cm
               HEP2005, Lisboa 21-27 July 05                     Roberto Campagnolo - CERN                                                                           6
                       The Pre Amplifier – Shaper Amplifier
                                                                 [ADC]
                                                                           PASA RESPONSE FUNCTION
                       Q/Cf



             Cf//Rf               (RC)4                                                    Q = 149 fC
  Q

                                                                           FWHM = 190 ns   A(t / t)4e-4(t/t)
                                                           +
               OPA         CfRf   OPA           OPA
                                                           -
                 CSA                 SHA          OA
                  IN
                                                                                                              [ns]
                                                               16 CH – PASA MAIN CHARACTERISTICS
                                                                AMS 0.35 mm – Die area : 18 mm2
                                                                Gain :        12mV / fC
                                                                FWHM :        190ns
                                                                Noise :       566e ( @ 12pF )
                                                                INL :         < 0.3 %
                                                                Crosstalk :   ≤ 0.1 %
                                                                Power :       11 mW / channel
                                                                Produced 49350 chips, Yield 83%
                 OUT

HEP2005, Lisboa 21-27 July 05           Roberto Campagnolo - CERN                                         7
                                    The ALiceTpcReadOut chip




                             MAX SAMPLING CLOCK 25 MHz                 MAX READOUT CLOCK 60 MHz


        16-CH Signal Digitizer and Processor
     Process: ST 0.25 µm HCMOS7 ( 6M transistor )
     Online baseline correction / tail cancellation
     800 k-bits internal memory
     Single Event Upset-proof redundant control
     area:               64 mm2
     power:              16 mW / ch
     Resolution:         9.7 ENOB
     Readout BW: 300 MB/s
     49 000 pieces produced - Yield 84 %


    HEP2005, Lisboa 21-27 July 05          Roberto Campagnolo - CERN                              8
       ALICE TPC Readout Control Unit (216 units in total)

                                  Detector Data Link
(Data Acquisition)                                                                          SIU
                                        ( 200 MB / s )




                                                                                                                13.5 cm
                                        Ethernet
(Detector Control System)
                                       ( 1 MB / s )




                                     TTC optical Link                             DCS Interface
(Timing, Trigger and Control )

                                                                          23 cm
RCU Functions:
  Readout related:                                             Slow Control related:
• Configuration of the ALTROs                                  Supervision and monitoring :
  (via the DDL or the DCS)                                     - Configure the power state of the FECs
• Distribution of the trigger and clock signals                - Temperature, Current and Voltage variations
  (from the TTCrx)                                             - Read status parameters (L1 and L2 counters…)
• FEC data readout and transfer to the DAQ                     - Interrupt and error handling
  via the DDL
 by the ALTRO bus (VME-like custom bus)                      by the Local Slow Control bus (I2C-like custom bus)
  HEP2005, Lisboa 21-27 July 05               Roberto Campagnolo - CERN                                     9
           ALICE TPC Readout Electronics - Measurements
High Multiplicity Event in Field Cage Prototype
                                                               System Noise




                                                  ADC Counts
             ( 5500 FEE channels )




                                                                                                           Time bin
                                                                   Average Noise:
                                                                   ~ 0.68 ADC counts (r.m.s.) ≈ 730 e- [TDR: <1000e-]




                                                                                   Typical Pulse shape
 Tail Cancellation Filter and Moving Average Filter effects
  HEP2005, Lisboa 21-27 July 05        Roberto Campagnolo - CERN                                                 10
                                  Conclusions

  The ALICE TPC is readout with an innovative electronics with on-detector
  digital signal processing.




 Test performed on a sizeable fraction of the final electronics show that the
  system fulfills all requirements, in particular:
     - Power consumption : 40mW/ch
     - System Noise ~ 730 e-
     - Baseline restoration at 1 ‰ of the Dynamic Range within 1 μs




  Production and test of components is on schedule for the start installation in
   Fall 2005 and detector commissioning in Spring 2006



HEP2005, Lisboa 21-27 July 05   Roberto Campagnolo - CERN                           11
                                                            End of presentation

HEP2005, Lisboa 21-27 July 05   Roberto Campagnolo - CERN                         12
                      Digital Conditioning of the TPC signal
                    INPUT SIGNAL                                    AFTER 1st BASELINE CORRECTION




              AFTER TAIL CANCELLATION                               AFTER 2nd BASELINE CORRECTION




HEP2005, Lisboa 21-27 July 05           Roberto Campagnolo - CERN                                   13
                  Readout Control Unit – Xilinx FPGA radiation tests




                                                                Single Event Functional Interrupts
                                                                   with Xilinx Virtex-II Pro FPGA
                                                                ( Reconfiguration started after 200
                                                                   seconds, errors are then
                                                                   continuously detected and
                                                                   corrected )




                                                  • Test conditions
                                                        – Flux = 3.7 x 1011 protons/cm2/s
                                                        – Reconfiguration time = 5 s
                                                  • Real life
                                                        – Flux = 7.9 x 102 hadrons/cm2/s
                                                        – Reconfiguration time = 10 ms
                                                  • Duty cycle: 1011 times better in real life

HEP2005, Lisboa 21-27 July 05    Roberto Campagnolo - CERN                                   14
                                  Integration with the Detector
Configuration for the Test-Beam (May 2004) and Cosmic Rays (2005)
IROC in Field Cage prototype readout with:
43 FECs ( 5500 channels , ~1 % of Alice TPC ) connected to
2 RCUs by
4 branches of ALTRO readout backplanes.
2 DCS boards interfaced to the RCUs and connected to the TTC,
2 SIUs for the DDL
‘Realistic’ Power supply distribution: Wiener500 with 40 m. cables




  HEP2005, Lisboa 21-27 July 05          Roberto Campagnolo - CERN   15

				
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