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TDC in ACTEL FPGA continued

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					TDC in ACTEL FPGA
     continued
    Preliminary
         Tom Sluijk
       Hans Verkooijen
        Albert Zwart
        Fabian Jansen
                    Test Program

   A 16 channels is fitted in an A3PE1500 208 PQFP and
   programmed in the Actel Starter Kit.

   The TDC (FPGA) is connected to a GOL/AUX Board (OT FE
   Electronics)
         get TFC through OT CTRL-Box
         read out through OT FE Test System (HOLA S-link Board)

   Test Program:
        Linearity (done!)
        DNL (done!)
        Temperature (to be done)




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                                 Test Setup
Hit                             FPGA                                 GOL
Inputs              TDC
                                96 bits          Zero              32 bits
                     16        @ 40 MHz        Suppress           @ 40 MHz
                  channels

                       mask                               mode
                             I2C Interface




      I2C interface to :
        Set Channel mask
        Set Readout mode
        Set Bx Counter init value
        Read status




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                  Readout Schemes
   Two Readout schemes:
        Raw Data; if one channel has a valid hit in a Bx, the data of
        all 16 channels is sent to the GOL.
         Zero Suppress; only the data of channels with a valid hit
        is sent to the GOL.
   Event Data in Raw Data mode:
        One word (32bits) Header.
        Two words Fine time (4 bits per channel).
   Event Data in Zero Suppress mode:
        One word (32bits) Header.
        1 to 4 words Channelnr and Fine time (8 bits per channel).
   Header:
        Length (8 bits).
        Hitpattern (16 bits).
        4 bits Bx counter.
        4 bits Status Flags (truncated, raw data, watermark)

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                     Compile Report


      CORE                     Used: 5610 Total:       38400 (14.61%)
      IO (W/ clocks)           Used: 88 Total:         147 (59.86%)
      Differential IO          Used:  4 Total:         65 (6.15%)
      GLOBAL (Chip+Quadrant)   Used:  5 Total:         18 (27.78%)
      PLL                      Used:  1 Total:         2 (50.00%)
      RAM/FIFO                 Used:  9 Total:         60 (15.00%)
      Low Static ICC           Used:  0 Total:          1 (0.00%)
      FlashROM                 Used:  0 Total:          1 (0.00%)
      User JTAG                Used:  0 Total:          1 (0.00%)




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                 Test Assembly




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                 Test Setup




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                 Results up to now
 Back-annotated simulations are performed and it works fine
 Delay Scans performed




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                 Results up to now
 TDC Spectra of all 16 channels
 Differential non-linearity from 1.84 to 1.99




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          Ray Irradiation Questionnaire
    FPGA type:
      Family: ProASIC3E
      DieA3PE1500
      Package: 208 PQFP


    OT Electronics at present estimated dose of ~6 Gy per year
    at 2  1032 cm-2 s-1
      should be ~60 Gy/year at 2  1033 cm-2 s-1 (Upgrade)


    Irradiation species to be tested (neutrons, protons)

      Could provide FPGA with test-setup
       dimensions ~34  20  4 cm3




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                 Conclusions and Outlook
   16 channels 4-bits TDC implemented in ACTEL FPGA
     control and DAQ system a-la OT
     can read out data (typically ~100 kHz, limited by HOLA)
     I2C interface with triple voting (SEU protection)
   Performed a delay scan and read out data
     TDC shows the expected linear response
     correlations between the channels checked ok
     Differential non-linearity (bin sizes) checked
   Next steps
     stability checks (temperature, etc.)
     zero suppression
     implementation on dedicated PCB
     performance tests in combination with high-speed optical link




March 28, 2013              Outer Tracker Upgrade              10

				
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