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					                                           Last Time …
      Digital Logic                                   U1b
                                                  3         4

                                                      U1a

            This Time …                           2         1


            Control Path,
           Arithmetic Ops




CBP 2002          ITY 270 Computer Architecture                 1
             Digital Logic Where?
            Control Circuits – CPU control path
                                 - system board
            (later)
           ALU Structure – add, sub, and, or, not
                                                 MUXES

                          X   Y                        0
                      X
                                                       1
                      Y

             Code
                      W
            Memory                                      Data
                                          ALU          Memory

                                                                Address Decoder

                          W                            7




CBP 2002               ITY 270 Computer Architecture                      2
    Boolean Notation, Truth Tables
                       A   B     O
                       0   0     0
A                                        A and B
                       0   1     0
                   O
B                      1   0     0                         Easy Way to write
                                           AB              truth tables - count
                       1   1     1
                                                           in binary !
                       A   B     O                            A   B   C
                       0   0     0        A or B
A                      0    1    1                            0   0   0
                   O
B                      1   0     1       A+B                  0   0    1
                       1    1    1                            0   1   0
                                                              0   1    1
                                                              1   0   0
                                                              1   0    1
                       A   O
A              O                         NOT A
                                          _                   1   1   0
                       0   1
                                                              1   1    1
                       1   0               A



    CBP 2002               ITY 270 Computer Architecture                   3
    Digi Logic Design 1 - use Gates
                             Comparator Circuit –
A                    O       outputs a ‘1’ if A and B
B
                             are equal, else ouput a ‘0’



                     2. Make each individual term
        A    B   O


        0    0   1
                         0
                                               1
        0    1   0       0
        1    0   0
        1    1   1       1
                         1             1                      3. Combine the terms with
                                                                 OR gate
    1. Look for lines with out = ‘1’

CBP 2002                      ITY 270 Computer Architecture                       4
    … again with Boolean Algebra
   A       B   O
                       __
   0       0   1       AB                            “Not A and Not B”
   0       1   0
    1      0   0
    1      1   1       AB                      “A and B”


                               _        __
                               A                          __
                   A                    AB
                                                     AB + AB
                   B           _
                               B


                                   AB




CBP 2002                    ITY 270 Computer Architecture                5
       Address Decoder Exercise
                           O1
  A                        O2
  B                        O3
                           O4



               O   O   O    O
   A       B
               1   2   3    4
                                         __                         U1 a

   0       0   1   0   0    0       O1 = AB           A         1          2
                                                                                   U2 a
   0       1   0   1   0    0                                                  1
                                                                                          3
                                                                    U1 b
   1       0   0   0   1    0
                                                                               2


   1       1   0   0   0    1
                                                      B         3          4




CBP 2002                        ITY 270 Computer Architecture                                 6
                    Decoder Application
                                       Selecting Registers, e.g,
               X    Y                  add r2,r1,r0
           X
               r0
                                        add     rd     rs     rt       unused
           Y r1

               r2
           W
                                                           decoder
                                                                   0
                        MIPS has 5-bit fields
                        for registers, so are 32

                                                                                   r0
               W                                                                r0r0
                                                                           cs


                                                                            Registers

CBP 2002                   ITY 270 Computer Architecture                          7
                           MUX Exercise
   A
                           Op                                   A
   B                                                            B         O


                                                                    C=0
               C

       C   A       B   O
                                                                A
       0   0       0   0                                        B         O
       0   0       1   0
       0   1       0   1
       0   1       1   1
                                                                    C=1
       1   0       0   0
       1   0       1   1
       1   1       0   0
                                What is MUX
       1   1       1   1        doing here ?


CBP 2002                        ITY 270 Computer Architecture                 8
               MUX is a Selector

                                                       U1 a
                                                   1
                               A                              3
                                                   2
                                                                      U2 a
                                                                  1
  A                                                                          3
                                                                  2
                                                       U1 b
                 Op            B                   4
                                                              6
   B                                               5




                                               2
                                        U3 a

                                               1
           C

                                               C




CBP 2002              ITY 270 Computer Architecture                              9
                       Multibit MUX
                                                        U1 c
                                                    9
                                                               8
                                                   10

                        A                               U1 a
                                                    1                   U2 a
                                                               3    1
                                                    2                          3
A                                                                   2


                   O                                    U1 b
B                                                   4
                                                               6        U2 b
                                                    5               4
                                                                               6
                       B                                U1 d        5
                                                   12
                                                               11
               C                                   13

                                           2
                                     U3a
                                           1




                                               C
    CBP 2002                ITY 270 Computer Architecture                          10
                MUX Application
                                   Selection of Datapath
                                   into one ALU input.
               Y’
                                    Datapath Y from instruction
           Y                        add r2,r0,r1

                                   Datapth Y’ from instruction
                                   addi r2,r0,4

                                   Sam has been designed so all
                                   immediate constants come in via Y’
               ALU
                                     add   rd    rs   rt   unused



                                       Immediate bit of op-code



CBP 2002             ITY 270 Computer Architecture                  11
      Address/Data Bus MUXing

            addr
  CPU                  MEM                                  CPU                       MEM
            data                                                     add/dat




           address                                             address         data

                     data


     Pentium System Bus                                     Multiplexed Address/Data
                                                                Bus, e.g. PCI Bus



CBP 2002                    ITY 270 Computer Architecture                              12
           Digi design 2 - use MUXes
A     B        O                A    B       O


0     0        I1               0     0      0
0     1        I2               0     1      1
1     0        I3               1     0      1
                                                         0   0 0
1     1        I4               1     1      0
                                                         1   0 1
          In 1                                                     Op
                                                         1   1 0
          In 2
                              Op                         0   1 1
          In 3

          In 4

                                                             AB
                               “ Muxes can be used to
                    AB         implement arbitrary
                               combinatorial circuits “

    CBP 2002             ITY 270 Computer Architecture             13
               MUX Design Exercise

                        3 input parity detector


       A   B    C   O


       0   0    0   0
       0   0    1   1
       0   1    0   1
       0   1    1   0
       1   0    0   1
       1   0    1   0
       1   1    0   0
       1   1    1   1




CBP 2002                   ITY 270 Computer Architecture   14
      Designing Using ROM/RAM
            0    0 0
            1    0 1
                               O
            1    1 0
            0
                                                 0 1 1 0         O
                 1 1
                                                 1 1 1 0         O


0          0 0                                         decoder
                 AB
1          0 1
                  O
1          1 0
                                                       A B
1          1 1


                       Several MUX’es fed with the
                       same AB produce a multibit
           AB
                       output. So does a ROM or RAM.

CBP 2002               ITY 270 Computer Architecture                 15
           Programmable Logic Arrays

                                                            _
                                                            ABC
                    Fuse




                                                 majority
CBP 2002         ITY 270 Computer Architecture                  16
     Addition of Binary Numbers

              1   A                                     1   A
              0   B                                     1   B

           0 1                                     1 0

  Carry = 0   Sum = 1                    Carry = 1      Sum = 0



                                                  1 1
                                                  0 1
           Multibit add - cascade
           sum and carry ops.                 1 0 0


CBP 2002                ITY 270 Computer Architecture             17
                             Full Adder

   A       B   Ci   S   Co
                                                             A
                                                 Carry In          B
   0       0   0    0   0
   0       0   1    1   0
   0       1   0    1   0
   0       1   1    0   1
   1       0   0    1   0
                                                      Full Adder
   1       0   1    0   1
   1       1   0    0   1
   1       1   1    1   1




                                              Carry Out       Sum




CBP 2002                     ITY 270 Computer Architecture             18
                             Full Adder

                                  0           0 0 0              0   0 0 0
   A       B   Ci   O   Co

                                  1           0 0 1              0   0 0 1
   0       0   0    0   0
                                              0 1 0                  0 1 0        C
   0       0   1    1   0         1                              0
                                                             S                    A
   0       1   0    1   0                     0 1 1                  0 1 1
                                  0                          U   1                R
   0       1   1    0   1
                                              1 0 0          M       1 0 0        R
   1       0   0    1   0         1                              0
                                                                                  Y
   1       0   1    0   1                     1 0 1                  1 0 1
                                  0                              1
   1       1   0    0   1
                                  0           1 1 0              1   1 1 0
   1       1   1    1   1

                                  1           1 1 1              1   1 1 1




                                              A B C                  A B C


CBP 2002                     ITY 270 Computer Architecture                   19
                           4-bit Adder

                 a3              a2                  a1              a0
            b3              b2                  b1              b0        0




           Full Adder      Full Adder         Full Adder       Full Adder



Carry
 Out
                      s3              s3                  s3              s3




CBP 2002                    ITY 270 Computer Architecture                      20
           Let’s Build an ALU
                   Carry In




     A
     B




              +




           Carry Out       S1 S0

CBP 2002               ITY 270 Computer Architecture   21
     Issues Concerning Numbers

           Multiplication and Division
           Subtraction
           Negative Numbers
           Fractional and Real Numbers
           Characters and Strings




CBP 2002            ITY 270 Computer Architecture   22
           Sequential Circuits

    Traffic Lights
    Washing Machines
    Fetch-Execute Cycle




CBP 2002             ITY 270 Computer Architecture   23
                           Counters

       T0   T1      T2      T3       T4
                                                          Clock




                                                           4-bit        Reset
    0000    0001   0010   0011      0100                  Counter



                                                          0 1 0 0 (4)



                                          How to get this to sequence
                                          012340123401234?

CBP 2002                  ITY 270 Computer Architecture                     24
           Traffic Light Sequencing

       Clock




                     Reset
        4-bit
                                T0        T1      T2         T3
      Counter                                                            T2
                                                                  T1
       0 1 0 0 (4)

   Combinatorial                                                             T3
                                                                   T0
       Logic




CBP 2002                     ITY 270 Computer Architecture              25
          Fetch Execute Sequencing
     T1       T2            T3      T4       T5


                                                                           Clock
            Decode,                Mem      Reg
    Fetch                 ALU Op
            Reg Op                 Access   Write
                                                                       Counter


                                                                       Decoder
                                                             ALU
                                                                   1        3



                                                                       +           +
                   X Y                              0
                                                                                            ALU
               X                                                   --                  --
                                                    1
               Y
  Code         W
 Memory                                              Data
                                   AL               Memory
                                   U

                      W                             7

CBP 2002                           ITY 270 Computer Architecture                                  26
                Representing Numbers
                 0                                                    0
    7           000          1                           -1          000          1
          111         001                                      111         001

6   110                     010   2                 -2   110                     010   2

          101         011                                      101         011
    5           100          3                           -3          100          3
                4                                                    -4


 Let’s take some 3-bit                   “2’s Complement” – complement it
 numbers.                                (0->1 and 1->0) then add 1
CBP 2002                      ITY 270 Computer Architecture                            27
           2’s Complement Properties
                                          Most Significant Bit (MSB) gives sign.
                  0
                                          Addition ?
     -1          000          1
                                                           001     1      111      -1
           111         001
                                                           010     2      110      -2
                                                           011     3      101      -3
-2   110                     010   2

           101         011                 Subtraction by Addition
     -3          100          3
                 -4                                 001        1       011     3
                                                    111       -1       110    -2
                                                    000        0       001     1
     MSB is Sign Bit !
                                                                   3 - 2 = 3 + (-2) = 1

 CBP 2002                          ITY 270 Computer Architecture                        28
           Subtraction by Addition

            b3              b2                  b1               b0

                 a3              a2                  a1               a0
                                                                           1




           Full Adder      Full Adder         Full Adder        Full Adder




                      s3              s3                   s3              s3




CBP 2002                   ITY 270 Computer Architecture                        29
 HEX and Chars
Binary   Hex   Hexadecimal Shorthand
0000      0
               each nibble rep’d as a
0001      1    character …
0010      2
               1011 0111
0011      3
0100      4       B       7
0101      5
0110      6
               Useful in Machine Level
0111      7
1000      8
               Programming and HTML                               UNICODE
1001      9    scripting
1010      A                                                         HEX        Ascii
1011      B
1100      C
                                                                    30          0
1101      D
                                                                    41          A
1110      E
                                                                    61          a
1111      F
                                                          ASCII     6D          m
                                                                    0D         CR
  CBP 2002                ITY 270 Computer Architecture                   30
             Multiplication

   13       11 x
      x
                                                   1   1   0   1
                                                                   x
   12       21                                     1   0   1   1
   26       11                                     1   1   0   1

  130      220                                 1   1   0   1

  156      231                             0   0   0   0
                                       1   1   0   1
                                  1    0   0   0   1   1   1   1




CBP 2002       ITY 270 Computer Architecture                           31
                       Multiplication
                                                   A               B

     1101 A                                    1   1   0   1
                                      C        -   -   -   -   -   -   -       -
                    Add/no-add        0        0   0   0   0   1   0   1   1   Initial values
      adder                           0        1   1   0   1   1   0   1   1   Add A to B
                                      0        0   1   1   0   1   1   0   1   SHR
C    0000        1011 B               1        0   0   1   1   1   1   0   1   Add A to B
                                      0        1   0   0   1   1   1   1   0   SHR
                                                                               No Add
                                      0        0   1   0   0   1   1   1   1   SHR

Add A to B. Then Shift                1        0   0   0   1   1   1   1   1   Add A to B

Right (SHR). Look at LSB              0        1   0   0   0   1   1   1   1

bit. If this is 1 then Add A
to B.
                                          A=           B=          AxB =

CBP 2002                  ITY 270 Computer Architecture                                     32

				
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