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					Matrix Processor / Backplane Design Details


         John Jones
 Princeton University

        Matt Stettler
Aims Of These Slides

 Try to summarise/clarify details of the system that have not been previously discussed
       Clarify the connections on the backplane…
       …and their relationship to the matrix processor

        Clock system options
        JTAG options
        Ethernet usage
        Signal standards

 26.02.2008                    John Jones (                            2
uTCA Specifications

 uTCA is an AC-coupled serial system
     Required by specification

 Default signal standard for serial links is CML
      Use of any other standard requires card negotiation with the host
      Signals must be tristated until host ‘agrees’ to power-up
      This means we can use, e.g. Ethernet on a link, provided
      we negotiate the protocol with the host

 Standard for clocks is LVDS

 Basic specification allows for 21 serial channels and 3 clocks
      Specification was amended to provide 20 channels and 4 clocks…
      …however either is still acceptable

 26.02.2008                    John Jones (            3
Matrix Processor

    OptoTX                                                       20
                         16                                           Backplane
    OptoRX                                 72x72
                                            16   20
                                         V5-LXT110                           Enet
 Switch has 72 bi-directional links:
      16 to OptoTX/RX
      16 to V5 MGTs
                                             AC-coupled CML
      20 to backplane
      20 to V5 LVDS IOBs                     AC-coupled LVDS

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Matrix Backplane Design

 uTCA allows for 3U or 6U implementations
     In the backplane we take advantage of this to simplify routing

 Backplane is actually two identical boards
     Each supports 12 3U full-height cards or 6 6U full-height cards

 Design is intended to be fully uTCA compliant
      We can use standard commercial boards as well…

 Significant difference in the way specifications are supported:
       Typically routing of links would be handled by a host card (MCH)
       As we have a switch on the backplane that controls the links,
       the backplane takes on the full functionality of an MCH
       There is no need for an MCH slot in this design

        Dual-redundant power supplies are not included in the current schematic
        Significantly complicates backplane layout

 26.02.2008                   John Jones (                     5
Matrix (Half-)Backplane – Layout

  Input slot          S1           S2            S3     S4   S5   S6

               Clk/                              Switch

     Power            S12         S11           S10     S9   S8   S7

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Matrix Backplane – Switch connections

                                                                              Slot 1
                                   12                               10
               4                                                         10
                                                                              Slot 2
                                                                         10       5
        (TTC)                      12
      Input slot                                                              Slot 3
 Backplane switch has 144 bi-directional links:
      12x10 (120) to card slots
      12 to backplane FPGA
      12 to input card slot

 26.02.2008                       John Jones (                      7
Matrix Backplane – Clock Fan-Out

                   Control                                      1
                                                             Slot 1
     Local OSC                                       2
                   1                                            1
    Fractional-N   1              42
                                                         2   Slot 2
     Synthesis                   Fan-out

                       2                                 2      1
      Input slot                                             Slot 3

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 Use MGTs for high-bandwidth data
      Isosynchronous but the fastest transport mode

 Neighbouring slots have 5 links between each of them
      Can be used for ‘geometric’ processing (e.g. nearest-neighbour)

 Use Manchester-encoded LVDS for synchronous signal distribution
      Up to 500MHz throughput in a Virtex 5
      Routed through switch – protocol agnostic, works from DC to 4GHz

 JTAG chain in crate is controlled by FPGA/uController on backplane
      Automatically routed through active cards
      Can be reconfigured by changing FPGA settings over Ethernet
      Accessible from connector on (TTC) input card
      Backplane FPGA is isolated from chain (separate connector on backplane)

 If additional clocks needed, use the LVDS signals
       Can be routed to other cards using switch
       Cannot be used for MGTs – no obvious reason to have more than two MGT clocks

 26.02.2008                 John Jones (                      9

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