A+ Hardware Exam Cheat sheet
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A+ Hardware Exam Cheat sheet Chapter 1 Hardware Exam 220-301 Register at www.vue.com for exam. Chapter 2 Motherboard The form factor determines the actual physical shape & dimensions of the board. ISA is acronym for Instruction Set Architecture 1983 IBM released eXtended Technology XT XT motherboard used jumpers and DIP Switches. AT introduced ROM BIOS & CMOS. 1984 IBM released Advanced Technology AT form factor AT used 16-bit data path, first processor to use the AT form factor was Intel 80286. AT form factor use 5 pin DIN connector for Keyboard. 1995 Intel released Advanced Technology eXtension (ATX) form factor. It is Open Standard means that anyone can use the design freely. ATX uses a single-keyed 20-pin Power supply Connector. ATX form factor featured I/O ports built right into the board. CPU Case Low Profile eXtension (LPX) developed by Western Digital was replaced by NLX. ISA original at 4.77MHz eventually set at 8.33MHz. VESA BUS is directly attached to 32-bit Processor. PCI was introduced in 1993 by its Intel 32 bit bus running at 33/66MHz; then changing to 64 bits ate 133MHz. PCI bus ad bus mastering enable several devices to share a single expansion slot’s IRQ. IRQ 9 being shared by multiple devices. North Bridge and South Bridge o North Bridge is generally used for high speed interface card such as video accelerator, Synchronous RAM (SRAM) and memory o South Bridge is generally used for slower devices such as USB ports, IDE drives & ISA slots. South Bridge works in conjunction with what’s called a Super I/O chip. CPU L2 L1 400 MHZ Front Side Bus Fast NORTH AGP at 133 Mhz SDRAM, at 400 DIMM Processing BRIDGE Slow Processing SOUTH USB 1 & 2 IDE 1, IDE 2 BRIDGE CMOS, RTC Very Slow Processing SUPER I/O CHIP COM 1 2 LPT 1 Floppy, K/B, Mouse. Flash ROM The main difference between a PCI bus and a VL-Bus is that the PCI bus is a specifically designed, high speed main expansion bus shared by multiple devices. VL-Bus was dedicated to single device. PCI-X specifies a 64-bit bus and uses clock speeds of 133Mhz, 266Mhz and 533Mhz PCI was a 32 bit bus, clocked at 33/66MHz with 133MB/s. PCI-X (rev 1.0) provided for 133MHz clock speed allowing for 1GB/s throughput. PCI-X (rev 2.0) used 266 & 533Mhz producing 4.3GB/s throughput. DMI Desktop Management Interface ensures that the PnP device can store configuration information in Management Information Format (MIF) files. The DMI Service Layer stores the information to an MIF database. MCA IBM Micro Channel Architecture, 32bit later went away. CPU works with the North Bridge and the memory controller to move data bits in and out of Main Memory PCMCIA Personal Computer Memory Card Industry Association o Type I 3.3 mm Type II 5 mm o Type III 10.5 mm Type IV thicker than 10.5 ISA 16 bit bus ISA clocked at 8.33MHz PCI 32 bit & 64 bit bus clocked at 33/66MHz PCI –X is clocked at 133/266/533MHz Chapter 3 Memory Types and Forms Shadow RAM is a method of storing a copy of certain BIOS instructions in main memory. DRAM cells are made up of many capacitors. SRAM Static RAM works with transistors, rather than capacitors. SRAM is a lot faster than DRAM and SDRAM. SRAM is more expensive to manufacture. SRAM is typically used in Level 1 and Level 2 caches L2 cache is usually 256KB or 512KB. By keeping as much information as possible in SRAM (cache) the computer avoids having to access the slower DRAM. L1 and L2 caches run at the speed of the processor bus known as FSB SDRAM is synchronous because it waits for a clock tick before responding to instruction. SDRAM modules should be sync at 100MHz. PC100 standard was upgraded to PC133. Intel PC800 RDRAM was released with 800 series chipset running at 800MHz. PSRAM is called Pseudo Static RAM with built-in refresh and address control circuitry to make it behave similarly to SRAM. ROM BIOS is where the motherboard remembers the most basic instructions about the hardware of a particular chipset. CMOS stores system configuration settings as well as settings for additional hardware connected to basic chipset. CMOS requires small amount of electricity to maintain its settings. Upto 486 family of chips the CPU had no internal cache. The 80486 introduced 8KB internal L-1 cache which was increased to 16KB. The Pentium added 256KB or 512KB external L-2 cache. L-3 cache is to build some additional memory chips directly into the North Bridge. All three types of cache runs at the processor speed, rather than the speed of a slower memory bus. Burst Mode: Next expected information is prepared before the CPU actually makes a request. DRAM originally began with FPM Fast Page Mode. Fast Page mode simplifies the process by providing an automatic column counter. FPM automatically increments the column address when the controller selects a memory page. Using FPM, the controller doesn’t have to waste time looking for a range address for at least three more times. FPM evolved into EDO (Extended Date Output) EDO process eliminates 10ns per cycle delay of FPM generating faster throughput. FPM is like writing all zeros to disk and EDO is like changing only the first letter of the index name. Both FPM and EDO are asynchronous. In asynchronous mode the CPU and memory controller have to wait for each other to be ready before they can transfer data. RDRAM is known as narrow channel system because data is transferred only 2 byte (16bits) at a time. It reads data on both rising and falling edge of the clock signal. RDRAM use the processor memory bus timing frequency not the motherboard clock. SDRAM are synced to the CPU at multiple closer to the motherboard clock. RIMMs are connected to the bus in series. Data item has to pass through all modules before it reaches the memory bus. RDRAM uses 16-bit for data signals. DDR came about as a response to Intel’s RDRAM changing architecture and licensing fees. DDR reads data on both the rising and falling edges of the clock tick. DDR memory supports both ECC (error code correction) used in server and non-parity used in desktop/laptops. The big difference between DRAM and SDRAM is the synchronization feature. SIMMs are usually 30-pin 8-bit chip or 72-pin 32-bit chip modules and DIMMs uses 168 pin configuration. Parity is set to odd or even to make total to odd or even. Parity can detect single bit error but cannot correct. If the parity is odd and error is received circuit gets even number and vice versa. ECC requires more bits for each byte, but the benefit is that it can correct single bit error, rather than only the entire word. Because 90% of data errors are single bit ECC does very good job. Chapter 4 Processor, IRQ’s and DMA Registers are usually as wide as the CPU’s internal bus structure. CompTIA defines byte as 8 bits. Control Unit can decode, execute, or store. Decode unit translates the data into binary bits. FPU floating point unit went onto the chip die in the 486. Net Burst increases both the number of stages and the number of pipelines to enable development of high speed processors. RISC instructions are a set length whereas CISC instructions are variable length. IBM an Intel decided to use CISC architecture. The lithographic process works with ultra-violet light and a mask. 16 bit memory page addresses 1 MB requires 20 bit address bus. 32 bit processor works with 32 bit memory pages using 36 bit address bus. In other words internal highway is narrower than the external processor bus. Processor chips differ in following ways o Changes to the microcode o Manufacturing process, no of transistors, and register size. o Internal bus width o Address bus width o Front side bus speed & amount of L1 L2 cache IRQs Interrupt Requests. o An IRQ is a signal coming from a piece of hardware (such as a mouse) indicating that it needs the CPU to do something. Original XT could only handle eight IRQ’s. Starting AT motherboard began using two controllers each controller handles eight lines (0-7 and 8-15). IRQ 2 cascades to IRQ 9. By daisy chaining two controllers AT motherboard can handle 16 IRQ’s. An Interrupt controller is also known as Programmable Interrupt Controller (PIC) PIC is a chip. Depending upon which device is active, the PCI bus can allow or disallow the use of that “locked” IRQ. 16 IRQ Lines 2 Controllers IRQ 0 System Timer IRQ 8 Real Time Clock IRQ 1 Keyboard IRQ 9 Redirected Cascade to IRQ 2 IRQ 2 Cascaded from IRQ 9 IRQ 10 OPEN IRQ 3 COM 2 or COM 4 IRQ 11 OPEN IRQ 4 COM 1 or COM 3 IRQ 12 MOUSE PS/2 IRQ 5 LPT2 or Sound Card IRQ 13 Math Co-processor original XT HD Controller IRQ 6 Floppy Drive Controller IRQ 14 Primary Hard disk Controller IRQ 7 LPT1 IRQ 15 Secondary HD Controller A PnP specification requires 1. Compatible BIOS 2. Operating System 3. Device Controllers. Bus Mastering is where a device takes control of a bus during a throughput operation. PCI Steering on the other hand is where the bus itself directs data traffic to specific IRQs based on their availability. IRQ 15 is set aside for the secondary IDE drive controller not a second drive. DMA Direct Memory Access was developed to avoid bottlenecks in processing. For example if hard drive needs to access system memory for addresses or instructions, those interrupt requests don’t have to interrupt the CPU. Originally, a motherboard had only one DMA controller. The system worked so well that a second DMA controller was added. Each controller allows four channels, so today we have 8 DMA channels (0-7) available on most systems. Again two controllers, with 8 Channels. o 2 DMA Controllers 4 Channel each making it total 8 Channels COM 1 & 3 IRQ 4 03F8 03E8 COM 2 & 4 IRQ 3 02F8 02E8 Chapter 5 Processor and Chipsets Intel 8080 2MHz with 6000 transistors 8-bit system bus April 1974 Intel 8086 (5, 8 & 10MHz) 16-bit internal bus, 20 bit address bus. 1MB Memory June 1978 Intel 8088 (5 & 8MHz), 8-bit internal bus (processor bus) 20-bit address bus 1MB Memory 1979 Second Generation Intel 80286 (6,8,12.5MHz) 16-bit processor bus, 24 bit address bus allows 16MB Memory and 1GB virtual memory with swap files 1981 The problem with 286 was that when a 16-bit application requested Real Mode again, the chip couldn’t switch back Third Generation Intel 80386 (16, 20, 25,33MHz) 32-bit processor bus with extra chip Math Co-processor. o DOS (Together with Window 3.x is 16-bit OS. Windows 98 & Me are hybrid 16 and 32 bit OS. Windows 9x is mostly 32-bit OS, with a 16-bit subset of instructions to allow for backward compatibility. Windows NT, 2000, XP are all 32-bit OS. XP recently release its 64bit version. o Virtual Real Mode is the method by which Windows emulates a 16-bit DOS OS so as to run older application. o 386DX 32 bit address bus 368SX/SL 24/16-bit address bus. 16MB Addressable Memory Fourth Generation 80486 DX, DX-2 66MHz, DX-4 133MHz, SX, and SL(to save power) o First Processor to have Floating Point Processor Fifth Generation Pentium P5 o First Series 60/66 PGA o Second Series 90/100 SPGA o Third Series Pentium Pro for Servers 150/166/180/200MHz Frequency Data Address Release Cache Processor (when Register bit capacity bus bit space date size released) capacity size 16-bit general purpose 1 8086 1978 8 MHz 16 - registers (GP) MBytes 16 80286 1982 12,5 MHz 16-bit GP 16 - MBytes 4 80386DX 1985 20 MHz 32-bit GP 32 - GBytes 4 8KBytes 80486DX 1989 25 MHz 32-bit GP, 80-bit FPU 32 GBytes L1 16 4 Pentium 1993 60 MHz 32-bit GP, 80-bit FPU 64 KBytes GBytes L1 16 KBytes Pentium 64 1995 150 MHz 32-bit GP, 80-bit FPU 64 L1; 256, Pro GBytes 512, 1 K L2 32 KBytes 32-bit GP, 80-bit FPU, 64- 64 L1; 256, Pentium II 1997 266 MHz 64 bit MMX GBytes 512 KBytes L2 32 KBytes Pentium 32-bit GP, 80-bit FPU, 64- 64 L1; 256, 1999 500 MHz 64 III bit MMX, 128-bit XMM GBytes 512 KBytes L2 Intel MMX technology introduced 57 new microcode for audio, 2D, 3D, video, voice etc. SIMD Single instruction Multiple Data, is another extension of the microcode that tells dual pipeline Pentium chips how to process different instructions simultaneously. SIMD for Pentium III SSE ver 1 SSE ver 2 improved 3D Graphics, video, speech recognition. AMD uses 3DNow! and 3DNow Professional. Sixth Generation P6 is Pentium II Pentium III o Slot 1and Slot 2 for Pentium II and some PIII. Socket 370 /FC-PGA for PIII used 0.18 micron process Pentium 4 used 0.13 micro process Net Burst Technology o Net Burst technology is a combination of various features. Hyper-Threading (ht) technology A 400MHz System Bus An Execution Trace Cache Multiple ALU Rapid Execution Engine Hyper-Threading (HT) allows a single CPU to logically divide itself into multiple virtual processors. SpeedStep technology, used in mobile computers, allows a chip to shut down depending on demand. SpeedStep is a fine advantage, but HT Technology seems to cancel out the same advantage. Centrino mobile is a Pentium M processor on an i855 chipset with built in wireless(802.11b) and Power Management is directly related to battery power. Socket 4 - 273 pins (Pentiums 60-66) Socket 6 486 Socket 5 - 320 pins (K5 and Pentium 75-133) Socket 7 - 321 pins (K5-K6 and Pentium 75-300) Socket 8 - 387 pins (Pentium Pro) Socket 370 - duh… (Celeron and "flip chip" PIIIs) Slot 1 - Pentium II - Celeron - Pentium III (to about 800MHz) 440BX Chipset Slot 2 - Pentium XEON Socket 423 - For Pentium 4 Socket 478 - For Pentium 4 and Celeron Socket 418 – Intel Itanium Socket 603/604 - Pentium XEON Slot A - AMD Athlon K-7 Socket A - 462 pins - AMD Duron and Athlon (T-bird and XP) Socket 940 / 754 – AMD Opteron, Athlon 64FX, Athlon 64 MMX specialized multimedia instructions SIMD, SSE, SSE-2 original multimedia instructions 3D Now! Only supports only Intel SSE and not later versions. 32-bit internal architecture and 36-bit address bus working with a 64-bit processor bus. Mobile chips use 31-bit Net Burst, as a compilation of several ways to tweak performance at speeds over 2GHz. Chapter 6 Basic Electronics Watts = Volts + Current Continuity checking with millimeter. Power Supply converts AC current to DC. EMI Electromagnetic interference Electricity modifies a surrounding area. Modifications generated by strong electrical currents and their fields are called EMI ESD Electro-Static Discharge. Your body routinely builds up static electricity that discharges to the ground when you touch something conductive. When this takes places we call it ESD ESD you should at least ground yourself by touching a metal part of the chassis (such as powersupply) The Problem with this solution is that although the computer and your body have equalized, the charge is still contained within the combined system. ESD Kit uses a wrist strap (with a resistor) connected to ground wire. Special floor mat that discharges a current into ground, bypassing the computer. Exam might not include mat. During low humidity ESD can easily develop. Chapter 7 Input Devices Keyboard: When you press a key, it generates an electrical signal, and a microprocessor in the keyboard changes the signal to a digital code- a scan code. It then sends the scan code to the computer. o Keyboard Switch Technology Pure Mechanical: Metal contacts and a spring durable and self cleaning. Foam Element: The foam reduces bounce, but gives the k/b mushy feel lack of audible feedback metal foil contacts Rubber dome: Electrical contacts are sealed but not k/b mechanics. Have carbon button contacts. Rubber dome collapse to make contact Membrane sheet: Often used in commercial and industrial environments Spill and dust proof o Capacitive Technology: Non Mechanical Switch puts the two conductive plates of a capacitor inside a housing. Electrons are drawn onto the bottom plate by positive charge on the plunger, causing a small current to flow. MODEM MODulator DEModulator, analog signals are converted to digital signals and then back again. Phone lines work mainly in analog mode. UART Chips: Universal Asynchronous Receiver Transmitter. Converts serial data from the modem into parallel data the CPU can understand and vice versa. Three types of UART chips used in Modem o 8250 used in XT and PC-AT with 1-byte buffer o 16450 introduced with AT with 2-byte buffer o 16550A 16 byte first in first out FIFO to eliminate data overrun. Faster speed used 16550AN and 16550AFN MODEM Commands o +++ Escape or hangup ATA Answer incoming call, ATD Dial ATDP Pulse Dial ATDT Tone dial, W Wait AT H Hang up, ATZ Rest modem, ATI Identification, ATMn ATM0 Turn off the modem sound ATM1 turns sound ON, AT&C Carrier detect. SCANNER: CCD is composed of many small diodes. 300x600 horizontal vs vertical resolution or 1200x1200 dpi is dots per inch Parallel Port moves 8 bits of info at a time. Newer Scanners use USB. 24 bit scanner provides 16.77 million addresses at 256 levels of intensity To clean mouse Remove the ball and wipe it with a solvent (alcohol works well) Chapter 8 Peripherals: Storage Devices SCSI Small computer systems interface. Physical disks can contain from 1 to 24 logical drives. IDE Integrated Drive Electronics is a 16 head hard drive with a built in controller and logic board. EIDE is a 256 head hard drive developed by WD. DMA direct memory access is a way data moves into system RAM without passing through processor. CHS Addressing scheme used by BIOS to find physical cylinder, head and sector address. LBA Logical Block Addressing to translate logical CHS to Physical CHS addresses directly, bypassing BIOS translation tables. HARD DRIVE COMPONENTS o Platter: Plates or Circular very thin structure coated on both side with electromagnetic material o Spindle: Platters have a hole in center and is stack on a rotating center – the spindle o Spindle motor: High speed motor rotates spindle o Actuator: All head arms are attached to the actuator, which positions the arms simultaneously over tracks on the platters. o Logic board (controller): Integrated circuit board to control spindle motor speed, head braking, commands and controls, read-write circuit, encoding instructions, address translation and power management instructions. Track O is on the outer edge, and contains the boot sector. Modern disk have flying height of approx 5-20 nanometers (0.005-0.02 microns) Human hair is 150 microns. Head do require air in order to develop the flying height and so HD are not sealed in a vacuum. At very high altitudes, the air may be too thin for head flying and could crash. Areal Density: No of tracks per inch TPI. Bit density in given sector is bit per square inch BPSI. Taken together TPI and BPSI makes areal density. Head Actuator Motor: Head actuator is designed to extend and retract the arm to precise distance from the center of the platter. Stepper Motor and Voice Coils: Head actuators use either a stepper motor or a voice coil to move the head arms. Stepper motor are often used to move both the actuator and the spindle. The problem is that mechanical steps are limited as to how small they can be. Mechanical motions always is much larger than electrical movements. To get around this, voice coil motors use electromagnet to attract or repel the end of a head arm in faster and smaller increments. Stepper motor does not know about temperature change where as voice coil use a combination of distance movement and feedback instructions to determine the position of read write head. So the controller makes adjustments because of thermal expansion or shrinking. IDE uses IRQ 14 and 15 to communicate with CPU. The boot sector points to Head 0, Cylinder 0 track 0 and sector 0 (side 0). Boot sector is not same as MBR. Sector is usually 512 bytes. Floppy disk has 135 tracks per inch. Older disk drives used the same number of sectors in every track. Modern disks put different number of sectors on different groups of tracks. The number of sectors is based on the lengths of tracks. Therefore, outer tracks have more sector than inner tracks. Format Process defines minimum sectors per cluster. Every volume must be completely filled with clusters. FAT16 used with DOS. FAT32 & NTFS provides variable size clusters. FDISK uses BIOS interrupt 13h to determine disk size and partition information. CHS introduced a volume address limit of 528MB. LBA is a way to handle the translation between logical addresses and 28-bit physical numbers without having to bother the BIOS routines. It put limit for IDE drives to 137GB. For the moment ATA/IDE drives larger than 137GB requires Windows 2000/XP. And ATA/133 PCI Controller card and supporting chipset. Later ATA-6 Specification adopted 48-bit addressing scheme to extend max capacity to 144petabytes. CLUSTERS are groups of sectors, and sectors are 512 bytes pieces of tracks. o Tracks are divided into sectors of 512 bytes. o Sectors are combined into Clusters, starting at 2KB or 4 sectors. o Clusters must fill entire Volume. The size of volume dictates size of clusters. Volume is technical term for logical formatted partition. o Max number of FAT16 clusters is 65525. The largest cluster 16-bit DOS can make is 32KB. This limits FAT16 to 2GB as largest logical drive that DOS can address. o LBA allows for access to 8GB hard drive. o FAT32 and NTFS allow for larger logical drives, because they define cluster sizes differently than DOS. (Until recently, the maximum was 137GB.) FLOPPY DRIVE o 5.25”in DS-HD 1.2 MB and DS-DD 360KB o 3.5” in DS-HD 1.44MB and DS-DD 720KB ATA specifies how data will be combined, managed, controlled and validated as it moves from a magnetic spot on a disk through to system memory. DMA controllers, using direct memory access to offload work from the CPU. IDE refers to any drive that has a built-in controller. ATA IDE combination called a 40-pin keyed controller. The maximum length of the cable was specified as 18 inches. o I/O Interface Max Speed o ATA 3 or Fast ATA Throughput 16.7MB/s o ATA 4 or Ultra DMA/33 33MB/s o ATA 5 new 80 pin connector 66MB/s o ATA 6 Ultra ATA/100 100MB/s o ATA 7 ATA/ATAPI-7 133MB/s PCI Express supports the older PCI bus method of using A,B,C or D virtual interrupts.. MSI is optional in PCI 2.2 and 2.3 devices. A single SCSI bus can hold up to eight devices, each with a unique identification ID number. The ID number from 0 to 7 is called Logical Unit Number LUN. Don’t be confused by the 8 ID numbers and 7 devices on the overall bus. Remember that the host adapter automatically takes up one ID number. SCSI needs terminator on both end. SCSI-1 cable length was limited to 6 meters or 19 ft. SCSI-2 introduced bus-mastering. SCSI-2 specification brought change in the width of the bus from 8-bit to 16-bit. # of Bus Bus Name Specification MBps Devices Width Speed Asynchronous SCSI-1 8 8 bits 5 MHz 4 MBps SCSI Synchronous SCSI-1 8 8 bits 5 MHz 5 MBps SCSI Wide SCSI-2 16 16 bits 5 MHz 10 MBps SCSI Fast SCSI-2 8 8 bits 10 MHz 10 MBps SCSI Fast/Wide SCSI-2 16 16 bits 10 MHz 20 MBps SCSI Ultra SCSI-3 8 8 bits 20 MHz 20 MBps SCSI SPI Ultra/Wide SCSI-3 8 16 bits 20 MHz 40 MBps SCSI SPI Ultra2 SCSI-3 8 8 bits 40 MHz 40 MBps SCSI SPI-2 Ultra2/Wide SCSI-3 16 16 bits 40 MHz 80 MBps SCSI SPI-2 Ultra3 SCSI-3 160 16 16 bits 40 MHz SCSI SPI-3 MBps The 7 Generations of SCSI Up to 5 Up to 10 Up tp 20 Up to 40 Up to 80 Up to 160 Up to 320 Megabytes Megabytes Megabytes Megabytes Megabytes Megabytes Megabytes Per Second Per Second Per Second Per Second Per Second Per Second Per Second Ultra2 Ultra320 SCSI Ultra3 or SCSI Ultra160 Fast-40 SCSI Fast-160 SPI-2 Fast-80 SPI-4 LVD SCSI SPI-3 LVD SCSI LVD SCSI SCSI-2 SCSI-3 SPI Fast-20 SCSI- SE Fast & Wide Ultra SCSI 1 SE SE SCSI-2 SCSI-3 SPI Fast-20 Fast Fast & Wide Ultra SCSI Differential Differential Differential HVD SCSI HVD SCSI HVD SCSI Narrow (8 bit data) bus only Wide (16 bit data) Wide (16 bit data) bus only and narrow (8 bit data) bus QIC quarter inch cartridge analog tape format. QIC was replaced by digital audio tape (DAT). High end tape system used digital linear tape DLT. DLT is one of the several technologies developed in recent years to increase the data transfer rates and storage capacity of computer tape drives. CD o CLV Constant Linear Velocity. As the reading laser moves inward, the revolution per minute of the spindle motor increases o CAV Constant Angular Velocity uses a small buffer to vary the data stream through a microprocessor. So it doesn’t matter how slow or fast data enters the buffer because the data coming out of the buffer is adjusted for speed. DVD digital versatile disks. Dual-layer DVD have a second semi-transparent layer on top of each primary layer. The reading assembly shifts the focal point. Flash Memory works with something called Fowler-Nordheim tunneling effect. PROMs us a jolt of electricity. EEPROM use ultraviolet light as electrical source. Flash Memory cards use regular DC current to change individual transistors. Chapter 9 Peripherals: Output Devices Transient output is the stream of data being sent somewhere for fleeting observation or temporary storage. CRT or VDT or CON or LCD. o CRT the inside surface of the viewing pane is coated with a layer of dots made up of three different kinds of phosphor (a chemical). Each beam making one type of phosphor glow. Each phosphor dot on the inside of a monitor is a single pixel. Combining three color into a RGB “dot” is called a pixel triad. A standard VGA monitor has 640x480 horizontal & vertical pixels. SVGA is typically 1280x1024 or 1600x1200. o Most LCD panels have a fixed number of crystals leading to typical resolution of 1024x768. o DPI is not the same as dot pitch. Dot Pitch is the diagonal measurement between the centers of two neighboring triads or measurement as from the center of any two dots of the same color. Dot pitch range from 0.28mm to 0.25mm. o VGA 640x480 XGA 800x600 at 16million color or 1024x768 at 65536 color o SVGA 1280x1024 with 256 color Non Interlaced and Interlaced Monitors o Electron beams sweeps across the pixels from top to bottom and left to right in one pass is called non-interlaced. Non Interlaced provides more stable image (less flickering). o When electron beam sweeps from top to bottom in two passes we call it interlaced. Interlaced AGP accelerated graphics processing. But “P” stands for port not processing for exam. Maximum AGP bus length is 9 inch because of timing requirements. The AGP uses narrower bus with a clock multiplier. o AGP x1 66 MHz clock, 266MB/s throughput 3.3v o AGP x2 133MHz clock, 533MB/s throughput 3.3v o AGP x4 266MHz clock, 1066MB/s throughput or 1GB/s 1.5v o AGP x8 533MHz clock, 2.1GB/s throughput 1.5v Passive and Active Matrix LCD o Passive matrix has only one switch per column. Active matrix gives every liquid crystal its own switch address. Passive matrix typically contrast ratio of 15:1 Active matrix usually has 400:1. Early LCD monitor response time was 40-200ms current response time is 17-20 ms making them fast enough for many games. PRINTERS o Impact Printers (dot matrix), Thermal Printers (fax and portable), Ink & Bubble Jet, and Laser Printers. o Form feed involves pulling a piece of paper into a printer, aligning it in front of a printing mechanism. Impact Printer applies to dot matrix printer. Usually 9-pin, 18-pin and 24-pin. Dot matrix printers use either a tractor-feed or pressure roller. Two type of feeds are “form tractor” & “sprocket feed”. Form tractor is like a tractor belt encircling the wheels of a military tank. Sprocket feed uses a less expensive plastic tooted wheel. THE LASER PRINTING PROCESS o Step 1 Erasing: Latent images are like a memory of a picture. To remove the previously charged dots from the EP drum, a series of erase lights are set up near the drum’s surface. o Step 2 Cleaning: After Erase unit returns EP surface to neutral charge, a rubber cleaning blade gently scrapes it clean of any residual toner. o Step 3 Conditioning: (primary corona wire) The EP drum is negatively charged evenly throughout the surface. This process is called conditioning. Voltage of about -6000 is distributed by a very thin wire called the “corona wire”. The high voltage being sent through the corona wire causes a short circuit between the wire and the image drum. The air around the wire breaks down, causing a corona. And –ve charge migrate to drum. o Step 4 Writing: The writing mechanism is sophisticated device that controls the way laser beam moves over the surface of the drum. A beam of light touches the surface of the drum, it discharges a small amount of electricity usually -100 volts. Because the surrounding area of the drum is between -600 to -1000 volts, the spot(or dots) is more positively charged than the surrounding area on drum. o Step 5 Developing: The high-voltage power supply sends current, but this time through the toner cylinder, which “charges the toner particles with a negative charge. The charge is somewhere between the charge on the drum and the places where the laser light touched the surface”. Where there was light, there’s less of a charge than on the toner particles, so the toner particles are attracted to the surface of the drum in those places. o Step 6 Transfer corona Wire: (or secondary corona wire) The paper takes on a very high positive charge. The paper must be charged enough to pull the toner particles off the drum, but not so much that the paper wraps itself around the drum. o Step 7 Fusing: The fusing assembly is a quartz heating lamp inside a roller tube, positioned above a rubber pressure roller. This heating roller is made of a high quality nonstick material. o Step 8 End of Cycle: Finally, a fabric-cleaning pad, located on the opposite side of the heated upper roller, rubs off any residual melted toner. The Primary corona wire negative charges the EP drum so it can attract toner. The secondary or transfer corona wire charges the paper +ve so it can pull toner away from EP drum to paper. Separation pad, right below the pickup roller, tries to make sure only one piece of paper is pulled. Common cause of the jam is either more than one paper enters the system or the paper separation pad. Or wrong paper type can’t move the first page. “Paper out” message means that the pickup rollers can’t pickup the first piece of paper. If the page comes out of the printer completely black problem is with the primary coronal wire. If the paper comes out with a smudged image, and toner rubs off, the problem is with the fusing assembly. Bitmap fonts computer stores every single bit (dot) of the image. Raster Fonts are vector fonts change the size simply recalculates the lengths of the virtual lines. Microsoft later figured out their own raster fonts called true type fonts ttf (.ttf & .fot files) Chapter 10 Basic Networking PnP is both a hardware and software solution. PnP needs three aspects 1. PnP hardware, 2. PnP BIOS 3. PnP Operating system SCSI allows a total of 8 devices – one host adapter and seven peripherals. SCSI-2 allows up to 16 devices, including the host adapter. USB 1.0 and 1.1: USB 1.0 and 1.1 has two channels high and low. Transfer data of low channel is of 1.5Mbps and high channel is 12Mbps. 1 USB controller can sustain up to 127 devices. USB 2.0 has transfer rate of 480Mbps or 60MB/s. USB 2.0 was designed to add the benefits of high speed video and multimedia. USB 2.0 device is not compatible with USB 1.0 or 1.1. NRZI encoding means that only variations in the voltage produce a change in state. NRZI is one of the way USB can generate much higher throughput then earlier serial transfer protocols. IEEE 1394 FireWire: Design to deliver speeds up to 400Mbps new 1394b up to 800Mbps. IEEE- 1394 uses daisy-chained topology and allows 63 nodes, with 16 devices. FireWire or ilink transfer information from device to device. USB moves information through the computer. Networks can be peer-to-peer or client/server. All PC’s are equal in peer-to-peer network as opposed to client/server network where some PC act as a server and others clients. Both networks use software that performs the redirector function. The redirector monitors the CPU and determines whether data requests are local or remote. Redirector used INT 21. 3 groups of 24-bit MAC address is assigned my manufacturer and stored in ROM on the card. 1st group is a unique vendor code middle group identifies the particular card and the 3rd group are serial number. Ethernet is a baseband network meaning only one signal can be on the network at a time and that the signal takes up the entire bandwidth. Ethernet is called carrier sense, multiple access, collision detection (CSMA/CD) network. Terminator prevents signals along the wire from reflecting back onto each other from the cable end. Terminator absorbs the signals. Token ring network connects PC’s in a ring called ring topology. A bridge is a way to break down a large network running at full capacity into smaller groups of segment. Bridge work with only the addresses of the network cards on a specific network. Bridge allows for more PCs to be connected to the network without creating traffic bottlenecks. Router directs traffic to different, whole network. Bridge uses the built-in MAC address and router use the TCP/IP address. OSI LAYER o Physical Layer Network media, voltage level, connectors, media details. OSI lower layer o Data Link Layer Responsible for error-free communication between two network devices or nodes. LLC sub-layer on top of MAC sub-layer provides for connectionless and connection- oriented communication. o Network Layer Specifies path and packet switching between networks. Using routing protocol like IP, IPX, Appletalk o Transport Layer Establishes end-to-end connections. Also ensures reliable data flow. Protocol like TCP, UDP. SPX. o Session Layer Establishes, manages, and terminates communication by coordinating service requests and responses between two or more stations. o Presentation Layer Makes sure information is delivered to Application layer in readable and proper format. Data encryption/decryption, data compression/decompression and data representation. ASCII, EBCDIC, MIDI, MPEG, JPEG and GIF o Application Layer Any application that reaches out over the network is some form of communication is considered to be a layer 7 application. The HyperText Transfer Protocol HTTP was invented to transmit those HTML documents over WWW. XML is an extended markup language, designed to handle information formatting. ISDN provides up to 128Kbps of digital transmission over ordinary phone line. DSL connection, the PC must be within three miles of CO. transfer rates 1.5Mbps download and upload 128Kbps. PING uses the Internet Control Message Protocol ICMP to send data packets to another computer. TRACERT is used to time the various hops- the route- a packet takes to reach the destination IP address. Wireless 802.11 a / b / g o 802.11 wireless use spread spectrum transmission. o 802.11a Uses 5GHz OFDM Orthogonal frequency division multiplexing. 54Mbps OFDM divides the available channel into sub-channels and encodes a portion of the signal across each sub-channel in parallel o 802.11b Wi-fi Uses 2.4MHz FHSS freq hopping spread spectrum. 11Mbps the channel is broken into sub-channels, and the transmitter jumps from sub-channel to sub- channel (freq hopping) o 802.11g Uses 2.4MHz DSSS Direct sequence spread spectrum. DSSS smears a signal across a wide band of freq. The receiver listens to the entire band and rebuilds the signal. SSID service set identification used as the name of the network. WEP allows a device to send encrypted data over a wireless link. Typically 64-128 bit encryption. In addition o encryption key, the system can be configured as either open or closed. In an open system, the access point sends out a beacon and only those stations with the correct encryption key can decipher the data. On a closed system the access point doesn’t send a beacon. Each station sends an active probe, requesting a connection from access point. An active probe (closed system) takes longer to establish a link but is more secure. Bluetooth short range 5-10 meters uses 2.4GHz freq, transfer rate 1Mbps, developed by Ericsson Comm. IR uses light freq. Speed range from 0.9 to 4Mbps. Fiber Optics o Single mode 22 kilometer uses 5 micron wide fiber o Multi mode 6 kilometer uses 62 micron fiber o Uses 1. Bayonet (ST) connector looks like BNC connector or 2. Snap-on (SC) connectors looks like rj45 connector. Chapter 11 Basic Networking XT used DB25 serial port AT introduced 9 pin serial connector. DB9. Super I/O chip includes controller for IDE, COM Ports, FDD controller, LPT port also NIC, modem etc. LPT is a 25 pin parallel interface. Maximum length of LPT cable is 25ft. for serial cable is 50ft. Types of Parallel Ports IEEE 1284 o Unidirectional: Data flows out, but can’t come back o Standard bidirectional: Peripherals can send status message back o Standard Parallel Port (SPP) found in laptops and Notebooks o Extended Parallel Port (EPP) also 10 times faster than Standard bi-directional port. o Extended Capabilities Port (ECP) ECP port is about 10 times faster than standard bi- directional port. Allows Compression. Port on back of motherboard is 25pin female Parallel Port. Note that XT motherboard had 25pin male which was serial port and 25pin female Parallel Port. Serial is RS-232C. 9 pin Serial, 15 pin Video, 25 pin Parallel, 36 pin centronics, 50 pin SCSI, 5 pin DIN, 6 pin Mini DIN or PS/2. 10Base5 Thicknet 500 meters, 10Base2 Thinnet 200 meters, Uses Coaxial Cable RG-58 with 50 ohms impedance. RG59 is for video audio transmission with 75 ohms impedance. 10BaseT T stands for twisted pair. Uses CAT-5 four pairs to total of 8 wires. CAT 1 2 & 3 intended for voice-grade analog signal. CAT 5 and CAT6 used for data grade cable used for digital signaling up to 100Mbps Fast Ethernet. Category 5 CAT5 can be either solid core or stranded core. Stranded core wire is made up of many very thin strands of wire and more flexible than solid core wire. Solid core wire is less flexible, but it has less signal loss (attenuation) per meter than flexible core. Solid-core wire used for longer cable run up to 100 meters. STP is primarily used in IBM Token ring networks. CAT3 16MHz CAT4 20MHz CAT5 100MHz CAT5e 350MHz CAT6 and CAT7 550MHz. RJ11 can have 1 2 or 3 pairs of wire where as RJ45 has 4 pairs of wire. END OF HARDWARE EXTRA NOTES Water Cooling Condensor coil radiator. Liquid Cooling CPU cooling Block & Refrigerant Cooling Evaporator. POST Errors o 1xxMotherboard errors, 2xxRAM errors, 3xxKeyboard Errors, 3xxxx NIC o 6xxFloppy error, 11xxCOM1 errors, 17xxHard drive errors. Maximum Length of Standard Parallel Cable is 10ft, some enhanced use 25ft Maximum Length of RS232 Serial Cable is 50ft for RS232C is 100ft Firewire is 14ft 4.5 meters Max IrDA length is 1 meter speed is 115kbps SCSI recommended cable length is 20ft/6meters fast SCSI is 6ft and SCSI segment is 3 ft. 32 bit transfer use 68pin centronics 0=lowest 15 highest priority (forced-perfect termination) Default SCSI host adapter id is 7. LVD use 3.3v Low voltage High Speed. Laser Printer Process: Cleaning, Conditioning, Writing, Developing, Transferring, Fusing. Remember CCWDTF PCMCIA operating system must support two levels “Card Level” & “Socket Level” I/O Address of Video Controller is C0000-C7FFF. Primary IDE controller standard address is 1F0. Available IRQ are 0 2 8 13 are reserved for internal Computer 3-7 9 -12 14-15 BIOS consults ESCD extended System Configuration data went PnP device is connected. SCSI ID 7 has the highest priority on the SCSI bus. The priority of the remaining IDs, in descending order, is 6 to 0, 15 to 8 [7 6 5 4 3 2 1 0 15 14 13 12 11 10 9 8 ]. So SCSI Host Adapter usually assigned ID 7 and Primary HD ID 0. I/O Address Primary HD is 01F0-01FF IRQ 14 Secondary HD is 0170-0177 IRQ 15 COM 1 & 3 is IRQ 4 03F8 03E8 COM 2 & 4 is IRQ 3 02F8 and 02E8 LPT1 I/O address 0378h-037f LPT2 I/O address 0278h-027f, NIC I/O is 360 PIO Stands for Programmed Input / Output. FRU abbreviated for Field Replaceable Units. If a SCSI card is controlling both external and internal devices then the terminator resistor must be disabled on the controller and both the last internal and last external devices must be terminated. Diff between ESD & EMI. ESD is not recoverable EMI is recoverable. Low Level Format, Partition and then Format. MBR is at Cylinder 0, Track 0, Sector 1. Green is earth/ground, Black is live Shorter Prong, White is neutral USB Cable length 5 meters. IDE Controller has 2 channels Primary & Secondary. Each Channels can have 2 HD Master and Slave. Enable 13h int on SCSI controller for Bootable CD-ROM. 2 Type II PCMCIA Laptop can install 1 Type III Card 10.5 mm . Just empty both slots. “Local digital loop back” checks the transmitter and receiver of a modem. RAMBUS can be 168 pin, 184 pin or 242 pin (dual channel) SCSI has (single ended) SE 1.5m length, HVD 25meter or LVD 12meter length cable DMA channels are 0 to 7. ISDN BRI is 2B channels (64kbps)+1control = 128kbps. PRI =23B+1control=3Mbps. Thicknet 10Base5 uses Vampire connector or AUI connector (15pin) 10BaseT 100m 10Base2 185m & 10Base5 500m RG-58 coaxial and Fiber Cable good in EMI environment.