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Optical Link Receiver Presentation

VIEWS: 6 PAGES: 13

									 BTeV Pixel Detector

 Data In and Out project


Optical link receiver chip
                Data In Out
• Is the interface between the Pixel Detector and
  the pair DAQ system/Trigger processor.
• Ships pixel hits generated by the FPIX chips at
  high speed (~16Gb/s/plane).
• Accepts Initialization, Control and timing
  information for the FPIX chips.
• Provides clean clocks for FPIX and Tx chip.
• Optical links will be used for input and output
  links
   Data In Out requirements:
• Must fit in a tiny space at the corners of the
  Pixel planes.
• Radiation hardness: 1 Mrad
• Low Power budget: 1 W/corner
• Low material budget: no ferromagnetics.
• Everything must operate in the vacuum.
• EMI noise resistant.
                        Data In Out block diagram
                                                        BCO + control and initialization
                                                        signals
Fiber Pigtail
                 PIN     Receiver
                diode      chip
106MHz + control data
                                       shift_in#1                   shift_in#1                shift_in#1                          shift_in#2
                                                        PIXEL                       PIXEL                         PIXEL                        PIXEL
                                     shift_in#2
                                                        CHIP                        CHIP                          CHIP                         CHIP
                                                                                                                                    Token #2                 Token #2
                                              Token#1               Token#1                   Token#1




                            53 MHz Marter Clock
                                                                                            Data Bus #1

                                                                                             Token#1


                                                                                                  Data Bus #2




                                                              Token_in #1
                                                              Token_out
                                                              #1
                                                    8           Data bus              Data                        Tx serializer
                                                                #1                                      16
                                                                                   concentrator          ?
                                                                                                                  and VCSEL                VCSEL
                                                                                                                  driver                           Fiber Pigtail
                                                              Token_in #2            chip #1
                                                              Token_out
                                                              #2
                                                    8           Data bus
                                                                #2
                           Data Concentrator Control
                                                                                                  53 MHz Marter
                                                                                                  Clock
    Optical link receiver chip goals:

• Initialize FPIX chips
• On line control FPIX chips
• Generate appropriate timing for FPIX
• Some on line control to the Data
  Concentrator chip
• Supply clean clocks
              Optical link characteristics:
•   VCSEL: Ithmin=5mA, Opt. Power: 1mW (min).
•   PIN: responsivity 0.3 A/W.
•   Optical Receiver: Current to voltage front-end amplifier.
•   Cost: > $150/fiber:
     – VCSEL: $35
     – PIN: $35
     – Rad hard fiber: $3.5/m            total(10m): $35
     – Standard fiber: $0.15/m           total(150m): $22.5
     – Connector/Assembly: MT12 $80/pair, ~$15/fiber.
     – Total cost per extra fiber in the Pixel Detector (~200
       planes): $30K. Moral: minimize the number of fibers.
             Input Data characteristics:
• Three clocks:
   – Readout clock: 53 MHz, external. Needs jitter<100-150ps
   – BCO clock: 7.56 MHz, external.
   – FPIX Initialization clock (ShiftIn): few MHz needed.
• Initialization and Control data speed: few MHz needed.
• Initialization and Control data/clock are not concurrent.
• Conclusions:
   – Data can be serialized
   – 53MHz clock and ShiftIn can share the same channel.
   – Both clocks and data can share the same channel
            Data and clock onto a single fiber (1)

                                                   • Single fiber for
      0 0    0    1 0 0        0   1 1     0   0     clock and data.
                                                   • Guarantied
    132ns        132ns
                                                     transition every
      0 0 0       1      0   0 0   1   1   0   0     clock cycle.
                                                   • DC balanced.
    132ns
                                                   • Self clocking.
                 132ns



•      Figure: (upper) Bi-Phase mark encoding
              (lower) Manchester encoding
                            Data Frame:
          Start   CONTROL    DATA   Start      CONTROL     DATA




Start             1 bit                     • Start: frame
Command           Up to 12 bits               synchronization
Data              1 bit                     • Command: internal
                                              acction on FFs and
                                              logic.
                                            • Data: Init. Data for
                                              Fpix chips.
    Optical Receiver Block Diagram
                                          Serial In
                               Clock
                                                          8-bits Shift Register
                              extractor

                                                 8-bits parallel                                          LVDS
106 MHz biphase signal?                                                                    ?
                                                                                  .   FF
                                                                                  .
                                                                                  .
                                                          Command Decoder         .
                                                                                  .
                                                                                  .
                                                                                  .
                          53MHz ck                                                         ?>10             CMOS
                                                                                      FF




                                                                   DAC                            Charge Inj.




                                                                                                     LVDS
                                                                   PLL

                                                                                                  Diff PECL


                                                               Reset
                                                                                                     LVDS
                                                               BCO clock
           Optical Receiver Command List
•            Command      Value               Command   Value
    1 Data Reset                  13   Set_ScanPath#2
    2 Data Reset Low              14   Set_ScanPath#3
    3 Program Reset               15   Set_ScanPath#4
    4 Program Reset Low           16   Set_ScanPath#5
    5 BCO_ck_en                   17   Set_ScanPath#6
    6 BCO_ck_dis                  18   Set_ScanPath#7
    7 ShiftIn_en#1                19   Trigg/Acc_high
    8 ShiftIn_en#2                20   Trigg/Acc_low
    9 Load/Kill_set               21   Token_eneble
    10 Load/Kill_reset            22   Report_Status
    11 Set_ScanPath#0             23   Receiver reset
    12 Set_ScanPath#1
          Optical Receiver chip specifications:
• Input signals: PiN signal is AC coupled to comparator. Input power
    about 1 mW. PiN responsivity > 0.3A/W.
•   53 MHz clock jitter: 100-150ps
•   Output signals: CMOS and LVDS to the FPIX chip
•   Noise: as a function of BER. For instance: 10^-12 for the channel after
    irradiation => S/N > 15. We probably need S/N > 20 at the receiver.
•   Radiation: 10^13 n/cm² plus 1Mrad maximum estimated.
•   Physical size: must fit in 7 cm². The area is not rectangular but with an
    ugly shape. Unless the mechanical specification of the Pixel Plane
    changes.
•   Temperature: -20C to 30C ?
•   Vacuum:
                        Some questions:
• Will the receiver input need a PLL?
• Can IC tap delays be as accurate as required for the 106 MHz data case
  over time, temperature variations & accumulated radiation effects?
• How is a frame error detected remotely? Is it really necessary to detect
  frame errors. Won’t the system let you know of some error if framing
  is lost.
• Do startup problems arise (e.g., due to capacitor charge up times) if the
  receiver’s input signal is turned off for a brief period? Is it better to
  have the receiver check for a unique 14-bit data pattern (e.g., all ones)
  for proper framing detection?
• How does the slow control system get control data back from Denes’
  ICs if that is the path for read-back of control/downloading
  information?

								
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