# Lec 4_ State and Finite State Machines - Cornell University

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```					 State & Finite State Machines
Hakim Weatherspoon
CS 3410, Spring 2011
Computer Science
Cornell University

See P&H Appendix C.7. C.8, C.10, C.11
Announcements
Make sure you are
Registered for class
Can access CMS
Have a Section you can go to
Have a project partner

Sections are on this week

HW 1 out later today
Due in one week, start early
Work alone
• Class notes, book, Sections, office hours, newsgroup, CSUGLab
2
Announcements
Check online syllabus/schedule
Office Hours
Homework and Programming Assignments
Prelims: Evening of Thursday, March 10 and April 28th

Schedule is subject to change
HW1 Correction:
to implement both addition and subtraction. Similarly, your ALU should use only a single left shifter component to implement all of the shift

operations. For instance,   left right shifting can be accomplished by transforming the inputs and outputs to your left shifter. You
will be penalized if your final ALU circuit uses more than one adder or left shifter. Of course, always strive to make your implementation
clear, but do not duplicate components in an effort to do so.                                                                              3
Goals for Today: Stateful Components
Until now is combinatorial logic
• Output is computed when inputs are present
• System has no internal state
• Nothing computed in the present can depend on what
happened in the past!

Inputs         Combinational         Outputs
N        circuit       M

Need a way to record data
Need a way to build stateful circuits
Need a state-holding device
Finite State Machines                                   4
Unstable Devices
B

C

A

5
Bistable Devices
• Stable and unstable equilibria?

A              B    A Simple Device
Bistable Devices
• Stable and unstable equilibria?

A                   B           A Simple Device

• In stable state, A = B
0           1
1              0
A                   B              A                      B

• How do we change the state?
SR Latch
Set-Reset (SR) Latch                      S   Q
Stores a value Q and its complement Q
R   Q
S R      Q     Q
Q
0 0
0 1                                      R

1 0                    S
1 1                          Q

8
Unclocked D Latch
Data (D) Latch

D   S   Q         D Q Q
R   Q          0
1

9
Unclocked D Latch
Data (D) Latch

D                  S      Q                     D Q Q
R      Q                     0     0        1

1     1        0

Data Latch
• Easier to use than an SR latch
• No possibility of entering an undefined state
When D changes, Q changes
– … immediately (after a delay of 2 Ors and 2 NOTs)
Need to control when the output changes
10
D Latch with Clock
Level Sensitive D Latch
Clock high:
D    S   Q      set/reset (according to D)
Clock low:
clk   R   Q      keep state (ignore D)

clk
D
Q

11
Clocks
Clock helps coordinate state changes
• Usually generated by an oscillating crystal
• Fixed period; frequency = 1/period

1
0

12
Edge-triggering

• Can design circuits to change on the rising or falling
edge

• Trigger on rising edge = positive edge-triggered

• Trigger on falling edge = negative edge-triggered

• Inputs must be stable just before the triggering edge
input
clock
Edge-Triggered D Flip-Flop
D Flip-Flop
D    D   Q   F D    Q   Q   Edge-Triggered
•
• Data is captured
clk   L   Q     cL   Q   Q   when clock is high
c           • Outputs change only
on falling edges

clk

D
F
Q
14
Clock Disciplines
Level sensitive
• State changes when clock is high (or low)
Edge triggered
• State changes at clock edge

positive edge-triggered

negative edge-triggered

15
Registers
D0      Register
• D flip-flops in parallel

D1      • shared clock
• extra clocked inputs:
write_enable, reset, …
D2

D3
4-bit
4     reg 4
clk
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Metastability and Asynchronous Inputs

1-bit
reg

Clk

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Metastability and Asynchronous Inputs
Q: What happens if input changes near clock edge?
A: Google “Buridan’s Principle” by Leslie Lamport

1-bit
reg
0
1
Clk

18
An Example
Reset
Run
WE R

32-bit      +1
reg

Clk

19
Clock Methodology
Clock Methodology
• Negative edge, synchronous

clk         tcombinational    tsetup thold

compute        save         compute       save compute
– Signals must be stable near falling clock edge

•     Positive edge synchronous
•     Asynchronous, multiple clocks, . . .

20
Finite State Machines
Finite State Machines
An electronic machine which has
• external inputs
• externally visible outputs
• internal state

Output and next state depend on
• inputs
• current state

22
Abstract Model of FSM

Machine is
M = ( S, I, O,  )
S: Finite set of states
I:     Finite set of inputs
O: Finite set of outputs
: State transition function
Next state depends on present input and
present state

23
Voting Machine
3
D

LED dec
mux
mux
32 32              32
+1

reg reg reg          ... reg                    32
WE        WE    WE       WE

decoder (3-to-8)
detect

enc

V
3
24
Automata Model
Finite State Machine
Current
Output
Registers
State    Comb.
Logic
Input             Next State

•   inputs from external world
•   outputs to external world
•   internal state
•   combinational logic

25
FSM Example
down/on
input/output     up/off                             down/on
A                B
state   start
state

Legend                      up/off       up/off
up/off
C                D
down/off
Input: up or down                down/off
Output: on or off
States: A, B, C, or D

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FSM Example Details
1/1
i0i1i2…/o0o1o2…     0/0                       1/1
00            01
S1S0    S1S0

Legend                      0/0      0/0
0/0
10            11
1/0
Input: 0=up or 1=down             1/0
Output: 1=on or 1=off
States: 00=A, 01=B, 10=C, or 11=D

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Mealy Machine
General Case: Mealy Machine
Current
Registers
State    Comb.
Output
Logic
Input             Next State

Outputs and next state depend on both
current state and input
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Moore Machine
Special Case: Moore Machine
Current   Comb.

Registers
State     Logic   Output
Comb.
Input     Logic   Next State

Outputs depend only on current state

29
Moore Machine Example
down
input                up                      down
A             B
state     start             off           on
out       out

Legend                          up      up
up
C             D
off           on
down
Input: up or down                   down
Output: on or off
States: A, B, C, or D

30
Digital Door Lock
Digital Door Lock
Inputs:
• clock
Outputs:
• “unlock” signal
• display how many keys pressed so far

31
Door Lock: Inputs
Assumptions:
• signals are synchronized to clock

K A B Meaning
K              0 0 0 Ø (no key)
A              1 1 0 ‘A’ pressed
B              1 0 1 ‘B’ pressed

32
Door Lock: Outputs
Assumptions:
• High pulse on U unlocks door

4 LED 8
D3D2D1D0     dec
U

33
Door Lock: Simplified State Diagram
Ø                Ø
G1     “A”       G2      “B”     G3
”1”              ”2”            ”3”, U

“B”             else              else      any

Idle
”0”
Ø     else                                     any
B1    else B2          else     B3
”1”          ”2”                ”3”
Ø            Ø
34
Door Lock: Simplified State Diagram
Ø                Ø
G1     “A”       G2     “B”    G3
”1”              ”2”          ”3”, U

“B”             else       else           any

Idle
”0”
Ø                          else
else
B1    else B2
”1”          ”2”
Ø            Ø
35
Door Lock: Simplified State Diagram
Ø                Ø
G1     “A”       G2     “B”       G3
”1”              ”2”             ”3”, U

“B”             else       else              any
Cur.
Output
State
Idle                                       Idle         “0”
”0”                                         G1          “1”
Ø                          else                 G2          “2”
else
G3         “3”, U
B1    else B2
”1”          ”2”           B1          “1”
B2          “2”
Ø            Ø
36
Door Lock: Simplified State Diagram
Ø                Ø  Cur. State   Input    Next State
G1     “A”     G2 Idle “B”     Ø G3     Idle
”1”            ”2”Idle         ”3”,
“B” U      G1
Idle       “A”        B1
“B”             else     else                any G1
G1         Ø
G1        “A”        G2
Idle                                 G1        “B”        B2
”0”                                  G2         Ø         B2

Ø                          else          G2        “B”        G3
else                               G2        “A”       Idle
B1    else   B2 G3            any       Idle
”1”          ”2” B1            Ø         B1
B1         K         B2
Ø           Ø B2         Ø         B2
B2         K        Idle
37
State Table Encoding
Cur. State
S2 S1 S0       D3    Output
D2 D1 D0   U   Cur.S1 S0
S2 State        A
K Input B   Next 1 S’
S’2 S’State0
0
0 Idle 0       0       0
0 “0” 0    0    0 Idle 0
0       0   0
Ø   0        0
0 Idle 0
0 G1 10        0       0
0 “1” 1    0    0 Idle 0
0           0
1 “B” 1          0
0 G1 1
0 G2 01        0       1
0 “2” 0    0    0 Idle 0
0           1
1 “A” 0          0
1 B1 0
0 G3 11        0       1
0“3”, U1   1    0 G1 1
0       0   0
Ø   0        0
0 G1 1
1 B1 00        0       0
0 “1” 1    0    0 G1 1
0           1
1 “A” 0          1
0 G2 0
1 B2 10        0       1
0 “2” 0    0    0 G1 1
0           0
1 “B” 1          0
1 B2 1
1
0 G2 0     0   0
Ø   0        1
0 B2 0
State       4 S2 S1 8 S0             1
0 G2 0         0
1 “B” 1          1
0 G3 1
K 1A 0B
D3D2D D          Meaning
dec
0 Idle 0
0U        Ø 0 key) 0
(no 0                 1
0 G2 0     1 “A” 0
1            0
0 Idle 0
1
0 G3 1         x
x any x          0
0 Idle 0
1 G1 0       ‘A’0pressed 1
0
1
1R
0
1 B1 0     0   0
Ø   0        0
1 B1 0
1 G2 1          0pressed 0
0         ‘B’       P 1            0
1 B1 0     1   x
K   x        0
1 B2 1
G3           0 1
Q           0
1 B2 1     0   Ø
0   0        0
1 B2 1
B1          1      0       0       0
1 B2 1     1   x
K   x        0
0 Idle 0
B2          1      0       1                                      38
Door Lock: Implementation
4

dec
D3-0
3bit        S2-0
Reg                  U
clk
S2-0
A          S’2-0
B
C
Strategy:
(1) Draw a state diagram (e.g. Moore Machine)
(2) Write output and next-state tables
(3) Encode states, inputs, and outputs as bits
(4) Determine logic equations for next state and outputs 39
Summary
We can now build interesting devices with sensors
• Using combinational logic

We can also store data values
•   Stateful circuit elements (D Flip Flops, Registers, …)
•   Clock to synchronize state changes
•   But be wary of asynchronous (un-clocked) inputs
•   State Machines or Ad-Hoc Circuits

40

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