Microcomputer Block Diagram

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					 Microcomputer Block Diagram



             A dd re ss Bu s
CPU

              Da ta Bus


             Co n tro l Bu s




                                     In t e rf a ce Circ uit r y

       RAM                     ROM

                                     Perip h er a l D e vice s



                                                                   F1-1




                        TM-1
      CPU Functional Units


                                       CPU


In st r uc t io n Re g ist e r ( IR)          Pro gr am Co u nt er ( PC)



                                                     Re g ist e r 0
    Inst r u ct io n De co d e
    an d C on t r o l U nit
                                                     Re g ist e r 1




     A r it h m et ic an d
     Lo g ic Un it ( A LU )
                                                  Reg ist er n - 1



                                                                           F1-2




                                       TM-2
                   Opcode Fetch


    CPU
                                A d dr e ss Bu s




      N

 Pr o g ram
 Co u n t e r
                                               D a t a Bu s




  Op c od e                                          RA M

Inst ru ct io n
Re g ist e r                                                   N+2

                                                               N+1
                   Co nt ro l
                     Bus                           Op co d e   N
          Clo ck                                               N-1

          Re ad




                                                                     F1-3




                                     TM-3
                             Memory Maps


                       1 Byte

          F FFF    7 6 5 4 3 2 1 0   6 5 ,5 3 5          FF FF
                                                                   4 K ROM
                                                         F0 0 0
                                                         EFFF




                                                                  4 4 K Em pt y
H exa d ec im al                         De cim a l
A d dr esse s                            A dd re sse s


                         .
                                                         4000
                         .                               3 FFF

                         .
           0004                      4
                                                                   1 6 K RA M
           0003                      3
           0002                      2
           0001                      1
           0000                      0                   0000



                                                                          F1-6/7




                                                  TM-4
                           16-Bit Addresses


        Bit 1 5 =
                                                                                  B it 0 =
 m os t -sig n if ican t b it
                                                                         lea st -sig n if ica nt bit




       15   14    13   12   11      10   9   8   7   6       5   4   3   2    1     0




(a )



              9                      C                   F                3
        1    0     0   1        1   1    0   0   1   1       1   1   0   0    1    1




(b )

                                                                                                       F1-8




                                                 TM-5
          The Development Cycle


           Specify    Design                                Preliminary
                                Edit           Translat e
          software   software                                 t est ing




                                                                     Int egrate
Concept                                                                  and      Product
                                                                       verify




           Specify    Design             Build              Preliminary
          hardware   hardware          prot otype             t est ing



                                                                                  1-11




                                TM-6
                              Steps in
                       the Development Cycle


                                  List ing                                  L ist in g
                                     f ile                                     f ile
                                  ( .L ST)                                  ( .M A P)




           Sou rc e                                     Ob je ct                          A b so lut e
                                                                            L in ke r/                                                                 So f t ware
Edit o r      f ile            A sse m b le r              f ile                           o b je ct      Sim ula t o r
                                                                            lo ca t o r                                                                sim u lat io n
           (. SRC)                                      (. OBJ)                               f ile



                                                (For a b solu t e f iles)

                                                                                                                                                       Ha rdw are
                                                                                                           Em u lat o r
                                                                                                                                                       em u lat io n




                                                                                                                             He x     Do wn lo ad /
            Le g e nd :                                                                                    OBJHEX
                                                                                                                              f ile    t e rm in al       RA M
                                                                                                         c o nv er sio n
                                                                                                                           (. HEX)     e m ula t e
            Ut ilit y p ro g ram o r
            d ev elo p m e nt t o o l



            Use r f ile
                                                                                                            EPROM
                                                                                                                                                         EPROM
                                                                                                         Pro g ram m er
            Ex ec ut io n e nv iro nm e n t




                                                                                                           Fact o ry
                                                                                                             m ask                                        ROM
                                                                                                           p ro ce ss




                                                                                                                                                1-13




                                                                              TM-7
                      Motorola S-records

             S00900006D796E616D656F
             S11320003C3C000A327C201661000020534666F4F2
             S11320101E3C00E44E4E53636F7474204D61634B59
             S10C2020656E7A6965200D0A0061
             S113202A1E3C00F81019670000064E4E60F64E7505
             S9030000FC

(a)




      S1 1 3 2 0 0 0 3 C3 C0 0 0 A 3 2 7 C2 0 1 6 6 1 0 0 0 0 2 0 5 3 4 6 6 6 F4 F2



                                  Che ck sum
                                  Da t a By t es
                                  Lo ad A d d r ess
                                  Byt e Co u n t
                                  Re co r d T y pe




(b)


                                                                                      1-14




                                           TM-8
 68000 Programmer's Model


31           16   15   8 7     0

                                       D0
                                       D1
                                       D2
                                       D3     D at a
                                       D4     Re g is t e rs
                                       D5
                                       D6
                                       D7


31           16 15                 0

                                       A0
                                       A1
                                       A2     A dd re ss
                                       A3
                                              Reg ist ers
                                       A4
                                       A5
                                       A6
31           16 15                 0

                                       A7     U ser St ack Po int e r ( USP)
                                       A7     Su p erv iso r St ac k Po in t e r (SSP)

31   24 23                         0

                                       PC Pro g ra m Co un t er

                  15   8 7         0

                                       SR St a t u s Re g ist e r
                        123
                             CCR

                                                                                         F2-1




                                            TM-9
          68000 Status Register

                                            U ser By t e
     Syst e m Byt e             ( Co nd it io n Co d e Re gist er )

15   13        10     9    8                  4    3   2   1   0

T    S         I2     I1   I0                 X    N   Z   V   C

               123

                                                                      Carry
                                                                      Ove rf lo w
                                                                      Ze ro
                                                                      Ne g at ive
                                                                      Sig n Ex t e nd
                                                                      Int er rup t M ask
                                                                      Sup e rviso r St a t e
                                                                      Trac e Mo d e


                                                                                           F2-4




                                         TM-10
Condition Code Computation


    1 1 1
    00011001            C = Sm D m + Rm D m + Sm Rm
                          = 0 0 + 0 0 + 0 0
+   01110000              = 0

    10001001    Z = 0   V = Sm Dm Rm + Sm D m Rm
                         = 0 0 0 + 1 1 1
                N = 1    = 1

                        X = C = 0
    Rm = 1
    Dm = 0
    Sm = 0



                                              F2-5




               TM-11
68000 Memory Map

  -- Byte View --


                 1 By t e
                 ( 8 b it s)


    F FFFF F




   0 000 04
   0 000 03
   0 000 02
   0 000 01
   00 000 0

                               F2-7




               TM-12
              68000 Memory Map

                       -- Word View --


                      1 W ord ( 1 6 b it s)



FFF FFE


            By t e FFF FFE           By t e FFF FFF




                                                          N ot e :
                                                          Ev e n b y t e s co r re spo n d
                                                          t o u p pe r b yt es o n t h e
                                                          ex t e rn al d at a b us. Od d
                                                          b yt es c o r r esp o n d t o lo w e r
                                                          b yt es o n t h e e xt er n al
                                                          d at a b us.
           By t e 4                By t e 5
                 By t e 2                 Byt e 3

                        By t e 0                By te 1

0 000 04
0 000 02
00 000 0

                                                                                                   F2-8




                                              TM-13
                    68000 Memory Map

                    -- Longword View --


                                                   1 L o ng w or d ( 3 2 b it s )



                               W or d a dd re ss: n + 4


                            B yt e n + 4               et c.



                    n + 8
                    n + 4
L o ng w o rd s
                       n
ca n b e at a ny
e ve n a dd re ss

                            B yt e n               B yt e n + 1       B y te n + 2       B y te n + 3
                            1            2          3                 1         2          3
                                       Wo rd ad d ress: n                  W o rd ad dr ess: n + 2




                                                                                                F2-9




                                  TM-14
                      68000 Addressing Modes
                                                         Assembler                  Effective Address
                     Mode                                 Syntax                       Generation
Data Register Direct                                         Dn                            EA = Dn
Address Register Direct                                      An                            EA = An
Absolute Short                                          xxx.W or <xxx                 EA = (next word)
Absolute Long                                           xxx.L or >xxx             EA = (next two words)
Register Indirect                                           (An)                          EA = (An)
Postincrement Register Indirect                             (An)+                EA = (An), An ` An + N
Predecrement Register Indirect                              -(An)                 An ` An - N, EA = (An)
Register Indirect with Offset                             d16(An)                     EA = (An) + d16
Register Indirect with Index & Offset                     d8(An,Xn)                EA = (An) + (Xn) + d8
PC Relative with Offset                                   d16(PC)                     EA = (PC) + d16
PC Relative with Index and Offset                        d8(PC,Xn)                EA = (PC) + (Xn) + d8
Immediate                                                  #data                   DATA = next word(s)
Implied Register                                    CCR, SR, USP,            EA = CCR, SR, USP, SSP, PC
                                                      SSP, PC
 Notes:
 EA = effective address                                     PC = program counter
 An = address register                                      ( ) = contents of
 Dn = data register                                         d8 = 8-bit offset (displacement)
 Xn = address or data register used as index register       d16 = 16-bit offset (displacement)
 CCR = condition code register                              N = 1 for byte, 2 for word, 4 for longword. (If An is the
 SR = status register                                         stack pointer and the operand size is byte, N = 2 to
 USP = user stack pointer                                     keep the stack pointer on a word boundary.)
 SSP = supervisor stack pointer                             ` = is replaced by

                                                                                                           T2-1




                                                        TM-15
        Data Register Direct


Instruction: MOVE.B D0,D3

         Register Contents
Before:....D0.....10204FFF
...........D3.....1034F88A
                             On ly b it s 0 -7
                                af f ec t e d
After:.....D0.....10204FFF
...........D3.....1034F8FF

                                                 F2-10




                    TM-16
     Address Register Direct


Instruction:   MOVEA.L A3,A0

          Register Contents          Mo ve t o
                               a d dr e ss r e g ist e r
Before:     A0.....00200000
            A3.....0004F88A
                                         3 2 bit s are
After:      A0.....0004F88A                 m ov e d
            A3.....0004F88A

                                                           F2-11




                     TM-17
                Absolute Short


                                                   So urc e a dd re ssin g
                                                   m o d e is im m e d ia t e
Instruction:   MOVE.L #$1E,$800

           **** MEMORY ****
                                           De st in at io n a dd re ssin g
          Address Contents
                                           m o d e is ab so lu t e sho rt
Before:    000800     12
           000801     34
           000802     56
           000803     78

After:    000800     00           3 2 -b it o p e ran d siz e
          000801     00           m o v es d at a t o f o u r
          000802     00            c on se cu t iv e b y t e
                                          lo ca t io n s
          000803     1E

                                                                                F2-13




                          TM-18
                Absolute Long


Instruction: MOVE.B #$1E,$8F000

           **** MEMORY ****
                                   D est ina t io n ad d ressin g
          Address Contents
                                   m od e is a b so lut e lo n g
Before:    08F000     FF

After:    08F000     1E           Op era n d siz e
                                     is b yt e

                                                                F2-14




                          TM-19
                 Register Indirect


Instruction:   MOVE.L D0,(A0)                               A0 co nt ain s t h e
                                                            a d dr ess o f t h e
                                                               d e st in at ion
           **** MEMORY ****
          Address Contents     Registers
Before:    001000    55        A0 00001000
           001001    02        D0 1043834F
           001002    3F
           001003    00                                                A0 do e s no t
                                                                         ch an g e
After:    001000     10        A0 00001000
          001001     43        D0 1043834F
          001002     83
          001003     4F         A lo n g w o r d is w r it t e n t o
                                    ad d r e ss $ 0 0 1 0 0 0



                                                                                        F2-17




                              TM-20
           Postincrement Address
              Register Indirect


Instruction:   MOVE.W (A5)+,D0

           **** MEMORY ****
          Address Contents      Registers
Before:    001000     45        A5 00001000
           001001     67        D0 0000FFFF
                                              A dd re ss re gist e r
           001002     89                      in cr em e n t e d b y
           001003     AB                      nu m b e r o f b y t e s
                                                  m ov e d, 2
After:    001000     45         A5 00001002
          001001     67         D0 00004567
          001002     89
          001003     AB


                                                              F2-18




                              TM-21
          Predecrement Address
             Register Indirect


Instruction:   MOVE.W D0,-(A7)

         **** MEMORY ****
        Address Contents      Registers
Before: 001000     10         A7 00001002
         001001    12         D0 00000143
                                            A dd re ss re gist e r
         001002    83                       d e cre m en t ed b y
         001003    47                       nu m b e r o f b y t e s
                                                 m ov e d, 2
After:   001000     01        A7 00001000
         001001     43        D0 00000143
         001002     83
         001003     47

                                                               F2-19




                            TM-22
                  Register Indirect
                    With Offset



Instruction: MOVE.W 6(A0),D0        Ef f e ct ive a d dr ess is
                                     6 p lu s va lu e in A 0

         **** MEMORY ****
        Address Contents     Registers
Before: 001026      07       A0 00001020
         001027     BF       D0 00000000             A d dre ss r e g is t e r
                                                     do e s no t ch an g e
After:   001026     07       A0 00001020
         001027     BF       D0 000007BF




                                                                          F2-20




                            TM-23
               Register Indirect
             With Index and Offset


                                            A d dr ess r e g ist e r


                                                         Ind e x r eg ist er , 3 2 b it s
Instruction: MOVEA $10(A0,D0.L),A1

           **** MEMORY ****
          Address Contents               Registers
Before:    00101C     EF                 A0 0000100A
           00101D     10                 A1 00000000                               W o r d v alu e is
                                         D0 00000002                              sig n-e xt en d ed
                                                                              b e ca use d est ina t io n
After:    00101C         EF              A0 0000100A                         is a n a dd r e ss r e gist e r

          00101D         10              A1 FFFFEF10
                                         D0 00000002

              No t e:
              EA = $ 1 0 + $ 1 0 0 A + $ 2 = $ 1 0 1 C




                                                                                                       F2-22




                                        TM-24
                    PC-Relative
                    With Offset


Instruction:   MOVE.W $1020(PC),D5

         **** MEMORY ****
        Address Contents      Registers
Before: 001020      AB        PC 00001000     In st r uc t io n is t w o
         001021     CD        D5 12345678   w o rd s lo ng , s o PC is
                                            in cr em e n t e d b y f o ur

After:   001020     AB        PC 00001004
         001021     CD        D5 1234ABCD


                                                                  F2-23




                            TM-25
                 PC-Relative
            With Index and Offset


Instruction:   MOVE.W $1020(PC,D0.W),D5
                                                  On ly lo w - o rd er
           **** MEMORY ****                    1 6 b it s o f D 0 use d
          Address Contents        Registers           a s ind e x
Before:    001026    FE          PC 00001000
           001027    DC          D0 ABCD0006
                                 D5 12345678

After:    001026     FE          PC 00001004
          001027     DC          D0 ABCD0006
                                 D5 1234FEDC



                                                                F2-26




                              TM-26
                    Immediate


                                       Im m e dia t e d at a
                                             f ollo w
Instruction:     MOVE.L #$1FFFF,D0

          Register Contents      Base :
Before:     D0     12345678      $ = he xa d ecim al
                                 @ = oc tal
                                 % = b in a ry
After:      D0       0001FFFF    & ( o r n o t h in g ) = d ec im al
                                 ' A B' = A SCII ch ara ct er s




                                                                 F2-28




                         TM-27
                            68000 Signals


                Vc c (2 )
                                         A d dr ess Bu s        A1 -A 2 3
                GND (2 )
                               68000
                                            D at a Bu s         D0 -D1 5
                    CL K


                                                 AS
                                                 R/ W      A syn ch ro n o us
                     FC0                         UDS       Bu s
Pro ce ssor                                                Co n t ro l
                     FC1                         L DS
St a t u s
                     FC2                         D TA CK


MC 6 8 0 0             E                         BR        Bu s
Perip h era l      V MA                          BG        A rb it ra t io n
Co n t ro l         VPA                          BGAC K    Co n t ro l


                   B ERR                         IPL0
Sy st e m                                                   In t e rrup t
                  RESET                          IPL1
Co n t r ol                                                 Co n t ro l
                  HA L T                         IPL2


                                                                     F2-33




                                 TM-28
                        Upper Data Strobe and
                         Lower Data Strobe


         Int er n a l                 Bu s
          Sig n als                 Sig n als




          A2 3                        A2 3


            A1                        A1

            A0                                            WORD / BYT E   A0   U DS   L DS
                                       UD S
                                 ( ev en b yt e)               1         X     0      0

                                                               0         0     0      1

                                      LD S                     0         1     1      0
   WORD / BYT E
                                 ( o dd b yt e )


( a)                                               (b )

                                                                                   F2-34




                                 TM-29
                Decoding with
                -UDS and -LDS


68 0 00

   A 1 -A2 3                                           A d d r e ss B us


   D 8 -D 1 5                                    D a t a B us ( u pp e r b y t e)

     D 0 -D7                                     D a t a B us ( l ow er b y t e )



                 A d dre ss
                                       Up p er                                       Lo wer
                 De co d ing            RA M                                          RAM

                                   CS                                               CS
       UD S



       L DS


                                                                                         F2-36




                               TM-30
              Generation of -DTACK


                                        A d dre ss Bu s


6 80 0 0
                         A dd re ss     RA M                 Ad d re s s       RA M
                         De co d ing                        D e co d ing


                                       CS                                   CS
                      74 07                               740 7
            +5 V

               10 K
                                                                  Fro m o t h e r RA Ms ,
  DT A CK
                                                                  ROM s, I/ O De v ic es , et c.



                                                                                      F2-36




                                       TM-31
      Function Code Outputs


 Function Code

FC2   FC1   FC0         Address Space Type

 0     0     0          (Undefined, reserved)

 0     0     1                User Data

 0     1     0               User Program

 0     1     1          (Undefined, reserved)

 1     0     0          (Undefined, reserved)

 1     0     1              Supervisor Data

 1     1     0           Supervisor Program
 1     1     1    CPU Space (Interrupt Acknowledge)

                                                      T2-3




                    TM-32
                 Read Cycle Timing

                      DT AC K m u st b e                                 D at a lat ch e d in t o
                 asse rt ed b ef o r e t h e e n d                       CPU at be g in nin g
                  o f S4 , ot h erw ise w ait                                    o f S7
                    st at es ar e in sert ed


            S0      S1        S2         S3          S4   S5   S6   S7

     CLK

FC0 -FC2


A1 -A2 3

      AS

     UDS


    L DS


    R/ W

 DT A CK

D8 - D1 5


 D0 - D7

                                                                                          F2-39




                                           TM-33
             Write Cycle Timing


            S0   S1   S2      S3   S4   S5   S6   S7

    CL K

FC0 -FC2


A1 -A2 3


      AS

    UDS


    L DS

    R/ W

 DT A CK


D8 - D1 5


  D0 - D7
                                                       F2-40




                           TM-34
Data Movement Instructions


 Instruction                  Operation

EXG            Exchange registers

LEA            Load effective address

LINK           Link and allocate stack

MOVE           Move source to destination

MOVEA          Move source to address register

MOVEM          Move multiple registers

MOVEP          Move to peripheral

MOVEQ          Move short data to destination

PEA            Push effective address

UNLK           Unlink stack
                                                 T3-3




                      TM-35
 Integer Arithmetic Instructions
  Instruction                         Operation
ADD             Add source to destination
ADDA            Add source to address register
ADDI            Add immediate data to destination
ADDQ            Add short data to destination
ADDX            Add with extend bit to destination
CLR             Clear operand
CMP             Compare source to destination
CMPA            Compare source to address register
CMPM            Compare memory
DIVS            Signed divide
DIVU            Unsigned divide
EXT             Sign extend
EXTB            Sign extend byte
MULS            Signed multiply
MULU            Unsigned multiply
NEG             Negate
NEGX            Negate with extend
SUB             Subtract source from destination
SUBA            Subtract source from address register
SUBI            Subtract immediate from destination
SUBQ            Subtract short from destination
SUBX            Subtract with extend bit from destination
                                                            T3-4




                              TM-36
          CMP Example


Instruction:   CMP.B #'z',D7               A SCII co d e f o r
                                              'z ' is $ 7 A
        Register Contents
                                            D 7 also co n t a in s
Before:   D7     FFFFFF7A
                                            ASCII co d e f or ' z'
          SR         001F

After:    D7       FFFFFF7A                 D7 d o e s n o t
                                              ch an g e
          SR           0014

Notes:     01111010
         - 01111010
           00000000
           12 3
                      Z= 1
                      N = 0
                      V = 0 ( sig n b it d oe s n ot ch an g e)
                      C = 0 ( b o rro w no t re q u ir ed )
                      X = 1 (n o ch an g e)

                                                                     F3-5




                   TM-37
         DIVS Example



Instruction:     DIVS #-3,D7      Div is or , - 3


        Register Contents
                                  D ivid en d , 1 4
Before:   D7     0000000E
          SR         001F

After:      D7       0002FFFC     Qu o t ie n t , -4
            SR           0018
                                  Re m ain d er , 2


Notes: 14 / -3 = -4 with a remainder of 2
                                                       F3-8




                   TM-38
                Boolean Instructions


      Instruction                       Operation

AND                 AND source to destination

ANDI                AND immediate data to destination

EOR                 Exclusive OR source to destination

EORI                Exclusive OR immediate data to destination

NOT                 Complement destination

OR                  OR source to destination

ORI                 OR immediate data to destination

Scc                 Test condition codes and set operand

TST                 Test operand and set condition codes

                                                                 T3-5




                                TM-39
                      EOR Example

Instruction: EOR.L D6,(A4)+

         **** MEMORY ****
        Address Contents                   Registers
Before: 003100     AB                     A4 00003100
                                                                So ur ce o p e ran d
         003101    CD                     D6 12345678
         003102    EF                     SR      0000
         003103    10                                            De st ina t io n o p e ran d


After:    003100       B9                 A4 00003104           A 4 in cre m en t ed
          003101       F9                 D0 12345678                by four
          003102       B9                 SR     0008
          003103       68

Notes:     ABCDEF10
         + 12345678
           B9F9B968
           1 2 3
                      Z=    0
                      N =   1
                      V =   C = 0 ( alw a ys)
                      X =   n ot af f e ct e d ( assu m e 0 )

                                                                                       F3-10




                                        TM-40
     Shift and Rotate Instructions
Instruction           Operation                      Bit Movement

   ASL            Arithmetic shift left          C               Op era n d            0


                                                 X




                                                            Op er a nd             C
   ASR           Arithmetic shift right
                                                                                   X




                                                 C             Ope ra nd               0
   LSL             Logical shift left
                                                 X




                                                 0             Op e ran d              C
   LSR             Logical shift right
                                                                                       X




   ROL                Rotate left
                                                     C           Op e ran d




   ROR               Rotate right                            Op er an d            C




  ROXL        Rotate left with extend bit    C              Op e ran d         X




  ROXR        Rotate right with extend bit           X            Op era nd                C




                                                         1 6 b it s   1 6 b it s
  SWAP        Swap words of a longword

                                                                                               T3-6




                              TM-41
                 ASR Example



                                             A rit hm e t ic shif t
Instruction:     ASR.B D3,D2                   righ t : sig n b it
                                            d o es n o t ch an g e !

          Register Contents
                                             Sh if t c o un t in D3
Before:     D3     00000002
            D2     00000068
            SR         001F                 Sh if t d at a in D 2


After:      D3      00000002
            D2      0000001A
            SR          0000

Notes:         01101000

               00110100

               00011010      0
               1 2 3
                                  C =   X = 0
                                  Z=    0
                                  N =   0
                                  V =   0 ( alw ay s)

                                                                       F3-11




                          TM-42
Bit Manipulation Instructions


     Instruction           Operation

     BCHG                  Change bit

     BCLR                   Clear bit

     BSET                    Set bit

     BTST                   Test bit
                                        T3-7




                   TM-43
                 BTST Example



Instruction:     BTST #7,D5     T e st b it 7 o f D 5


          Register Contents
                                 Bit 7 = 0
Before:     D5     FFFFFF7F
            SR         0000

After:      D5       FFFFFF7F
            SR           0004    Z = 1



                                                        F3-12




                        TM-44
Binary-Coded Decimal Instructions

    Instruction              Operation

      ABCD           Add source to destination

      NBCD              Negate destination

      SBCD        Subtract source from destination
                                                     T3-8




                     TM-45
                    ABCD Example


                                                       O p e r an d siz e
                                                        alw a ys b y t e
Instruction: ABCD -(A3),-(A4)

            **** MEMORY ****
           Address Contents              Registers
Before:     00200E     98                A3 0000200F
            00210E     54                A4 0000210F                        X= 1

                                         SR      001F
                                                                            Bot h a d dr ess r e g ist e r s
After:     00200E       98               A3 0000200E                         d e cr e m en t ed b y o n e
           00210E       53               A4 0000210E
                                         SR     0011
              1                                                             ---XNZVC
Notes:      10011000                                                        00010001
            01010100
          +         1   (X = 1 )                                            98 + 54 + 1 = 15 3
                1 1                                                         ( t h e h u nd r e d s d ig it
            11101101                                                         is st o r e d in C & X)
          + 00000110    ( ad d 0 6 )
           11 1
            11110011
          + 01100000    ( ad d 6 0 )

            01010011
            1 2 3
                             Z= 0
                             C = X = 1
                             N = V = u nd e f ine d ( a ssum e 0 )



                                                                                                       F3-13




                                        TM-46
    Program Flow Instructions


   Instruction                          Operation

       Bcc                       Branch conditionally

      BRA                          Branch always

      BSR                       Branch to subroutine

      DBcc                   Test, decrement, and branch

      JMP                          Jump to address

       JSR                       Jump to subroutine

      NOP                              No operation

      RTE+                   Return and deallocate stack

      RTR                 Return and restore condition codes

      RTS                      Return from subroutine

+privileged instruction
                                                               T3-9




                               TM-47
                   BRA Example


Instruction:   BRA $20A0          Br a n ch d e st in at io n


          **** MEMORY ****
          Address Contents        Registers
Before:   002050     60           PC 00002050
          002051     4E
                                                                In st r uc t io n w o r d

After:    002050     60           PC 000020A0
          002051     4E

Notes:    Displacement = X               Bra n ch o f f s et , 8 b it s
          2052 + X = 20A0
                X = 20A0 - 2052
                   = 4E

                                                                                            F3-15




                             TM-48
                              BSR/RTS Example
                                                   BSR $ 4 0 F2
               BEFO RE                                                           A FT ER
RE GIS T ERS:                                                     RE GIS T ERS:
PC          0 0 5 0 16                                            PC          0 0 4 0 F2
A7       0 000 305 0                                              A7       0 000 304 C

MEMO RY:                                                          MEMO RY:




                                        MA IN                                                                MA IN
00 501 A                                PROGRA M                  00 50 1A                                   PROGRA M
0 0 5 0 1 8 F0 DA                                                 0 0 5 0 1 8 F0 DA
                       BSR $ 4 0 F2                                                      BSR $ 4 0 F2
00 501 6 6 1 0 0                                                  00 50 16 6 1 00



0 0 4 0 F A 4 E7 5     RTS                                        0 0 4 0 F A 4 E7 5     RTS
                                        SU BROU TIN E                                                        SU BROU TIN E


0 0 4 0 F2                                                        0 0 4 0 F2


00 3 05 0 1 234              A7                                   00 3 05 0 1 234
00 3 04 E 5 678                         STA CK                    00 3 04 E 5 01A                            STA CK
0 0 3 0 4 C 9 A BC                                                00 3 04 C 0 000               A7



                                                                                                 a dd re ss o f
                                                                                                 ins t ru ct ion
                                                                                               f o llo w in g BSR




                                                        RT S
                BEFORE                                                            A FT ER
  REGIST ERS:                                                       REGIST E RS:
  PC            0 0 4 0 FA                                          PC            0 05 01A                     ret u r n t o
  A7         0 00 0 3 04 C                                          A7         0 00 0 30 5 0                  in st r u ct io n
                                                                                                            f o llo w in g BSR
  MEMORY:                                                           MEMORY:




                                         MA IN                                                                 MA IN
  00 5 01 A                              PROGRA M                   00 5 01 A                                  PROGRA M
  0 0 5 0 1 8 F0 DA                                                 0 0 5 0 1 8 F0 DA
                         BSR $ 4 0 F2                                                      BSR $ 4 0 F2
  00 5 01 6 61 00                                                   00 5 01 6 61 00



  0 0 4 0 FA 4 E7 5      RT S                                       0 0 4 0 FA 4 E7 5      RT S
                                         SU BROU TINE                                                          SU BROU TINE


  0 0 4 0 F2                                                        0 0 4 0 F2


  003 050 1 2 34                                                    003 050 1 23 4                A7
  003 04E 5 0 1A                         ST A CK                    003 04E 5 01 A                             ST A CK
  003 04C 0 0 00              A7                                    003 04C 0 00 0




                                                                                                                                  F3-16




                                                         TM-49
          System Control Instructions


 Instruction                                    Operation

ANDI++           AND immediate to status register/condition code register

CHK              Trap on upper out-of-bounds operand

EORI++           Exclusive OR immediate to status register/condition code
                   register

ILLEGAL          Illegal instruction trap

MOVE++           Move to/from status register/condition code register

ORI++            OR immediate to status register/condition code register

RESET+           Assert RESET line

STOP+            Stop processor

TAS              Test and set operand
TRAP             Trap unconditionally

TRAPV            Trap on overflow

+privileged instruction

++privileged instruction if SR specified
                                                                            T3-10




                                        TM-50
                   TRAP Example


 Instruction: TRAP #5

                 **** MEMORY ****
                 Address Contents         Registers
 Before:          002FFA    12           PC 00002000
                                                                          Sy st e m
                  002FFB    34           A7' 00003000                 St a ck Po int er
                  002FFC    56           SR      001F
                  002FFD    78
                  002FFE    9A
   V ec t o r
                  002FFF    BC
  ad d r e ss
f o r t ra p 5    000094    00       V ec t o r f o r
                  000095    01          t rap 5                  Exc ep t ion p ro ce ssing
                                                                  b e gin s at ad d r ess
                  000096    80
                                                                        $ 0 1 8 0 F0
                  000097    F0

 After:          002FFA     00           PC 000180F0
                 002FFB     1F           A7' 00002FFA                     Sy st e m
                                                                      St a ck Po int er
                 002FFC     00           SR      201F
                                                                      d e cr e m e nt ed
                 002FFD     00                                               by 6
                 002FFE     20
                 002FFF     02                SR sa ve d o n      Su p er viso r St a t e
                 000094     00               syst em st ac k            b it = 1

                 000095     01
                 000096     80
                                              PC sav ed o n
                 000097     F0               sy st e m st a ck


 Notes:          Vector read from address $80 + (5 x 4) = $94
                                                                                           F3-18




                                 TM-51
          68000 Instruction Format

15   14   13   12     11   10     9   8   7    6    5   4     3   2   1     0

                                 Operation Word

           (1st word specifies operation and addressing modes)

                                Immediate Operand

                           (if any, one or two words)

                      Source Effective Address Extension

                           (if any, one or two words)

                    Destination Effective Address Extension

                           (if any, one or two words)

                                                                          F3-19




                                      TM-52
           Effective Address Encoding

            Addressing Mode                     Mode Bits    Register Bits

Data Register Direct                              000       register number

Address Register Direct                           001       register number

Address Register Indirect                         010       register number

Address Register Indirect with                    011       register number
  Postincrement

Address Register Indirect with                    100       register number
  Predecrement
Address Register Indirect with                    101       register number
  Displacement†

Address Register Indirect with Index*             110       register number

Absolute Short†                                   111                000

Absolute Long††                                   111                001

Program Counter with Displacement†                111                010

Program Counter with Index*                       111                011

Immediate or Status Register†††                   111                100

†      One extension word required
††     Two extension words required
†††    For Immediate addressing, one or two extension words required
          depending on the size of the operation
*      One extension word required; see Table C-4 for the encoding

                                                                           T3-11




                                        TM-53
   68000 Condition Code Encoding


   Mnemonic             Condition             Encoding         Test
      T†                  true                  0000            1
      F†                   false                0001             0
      HI                   high                 0010           C •Z
      LS               low or same              0011           C+Z
    CC(HS)              carry clear             0100             C
    CS(LO)               carry set              0101             C
      NE                 not equal              0110             Z
      EQ                  equal                 0111             Z
     VC††             overflow clear            1000             V
     VS††              overflow set             1001             V
      PL                   plus                 1010             N
      MI                  minus                 1011             N
     GE††            greater or equal           1100        N• V + N • V
     LT††                less than              1101        N• V + N •V
     GT††              greater than             1110     N• V •Z +N • V • Z
      LE††             less or equal            1111      Z + N• V + N •V
† Not available for Bcc instruction
†† Twos complement arithmetic
• = Boolean AND
+ = Boolean OR
                                                                           T3-12




                                      TM-54
                Opcode Map

     Bits
15 through 12                 Operation

    0000           Bit Manipulation/MOVEP/Immediate

    0001                      Move Byte

    0010                      Move Long

    0011                      Move Word

    0100                     Miscellaneous

    0101                ADDQ/SUBQ/Scc/DBcc

    0110                       Bcc/BSR

    0111                       MOVEQ

    1000                     OR/DIV/SBCD

    1001                      SUB/SUBX

    1010                     (Unassigned)

    1011                      CMP/EOR

    1100                 AND/MUL/ABCD/EXG

    1101                      ADD/ADDX

    1110                      Shift/Rotate

    1111                     (Unassigned)

                                                      T3-13




                     TM-55
                         Assembler Operation

                                                         PROG.OBJ
                                                                            L eg e nd :

                                                                                          Ut ilit y p ro g ram
       PRO G.SRC                A68 K

                                                                                          Use r f ile
                                                         PROG.L ST


( a)


                          Inp u t
          C o m m an d      f ile         Lis t ing      O b je ct co d e
                                        o ut ut f ile     o ut p ut f ile     A ssem ble r
                                                                                op t ion s



                A 6 8 K PROG.SRC, PRO G.L ST , PROG.OBJ, X S
( b)



                                                                                                 F4-1




                                                 TM-56
                               Assembler Files


                    La b el    Mn e m o nic     Op er an d      C om m en t
                    f ield        f ie ld         f ie ld    f ield (e m p t y )

                               ORG.....$1000
                 PROG          LEA.....$800,A0
                               MOVE.B..#50,D0
                               CLR.W...D7
                                                                                   Sou r ce
                 LOOP          ADD.W...(A0)+,D7                                      f ile
                               SUBQ.B..#1,D0
                               BRA.....*
                               END
( a)



            L ine nu m b e r

               A d d re ss     Co n t e n t s                So u rce f ile

        1   00001000.................ORG.....$1000
        2   00001000.41F80800.PROG...LEA.....$800,A0
        3   00001004.103C0032........MOVE.B..#50,D0
        4   00001008.4247............CLR.W...D7                                               L ist in g
        5   0000100A.DE58.....LOOP...ADD.W...(A0)+,D7                                            f ile
        6   0000100C.5300............SUBQ.B..#1,D0
        7   0000100E.60FE............BRA.....*
        8   00001010.................END

 (b )

                                                                                                       F4-2




                                                 TM-57
                   Listing Examples
 1   00001000                    ORG       $1000
 2   00001000   6006             BRA       *+8             ;"*" location counter
 3   00001002   60FE             BRA       *               ;branch to itself
 4   00001004   6000FFFE   HERE BRA        HERE            ;branch to itself
 5   00001008   181B             MOVE.B    (A3)+,D4        ;indirect addressing
 6   00000064              COUNT EQU       100             ;equate symbol to value
 7   0000100A   3A3C0064         MOVE.W    #COUNT,D5       ;symbol as immed. data
 8   0000100E   3A3C0064         MOVE.W    #100,D5         ;decimal
 9   00001012   3A3C0064         MOVE.W    #$64,D5         ;hexadecimal
10   00001016   3A3C0064         MOVE.W    #144Q,D5        ;octal (A68K format)
11   0000101A   3A3C0064         MOVE.W    #%01100100,D5   ;binary
12   0000101E   3E3CFFFB         MOVE.W    #-5,D7          ;negative number, decimal
13   00001022   3E3CFFFB         MOVE.W    #$FFFB,D7       ;negative number, decimal
14   00001026   3A390000         MOVE      $F000,D5        ;data address
     0000102A   F000
15   0000F000              PORT   EQU      $F000           ;equate symbol as address
16   0000102C   3A390000          MOVE     PORT,D5         ;data address (symbol)
     00001030   F000
17   00001032   4E71       BACK   NOP                      ;code address (NOP =
18   00001034   4E71              NOP                      ;   no operation)
19   00001036   67FA              BEQ      BACK
20   00001038                     END



                                                                      F4-4




                                   TM-58
            Assemble-Time Operators

 Operator†              Function              Precedence        Type
       -              Unary minus                  1           Unary
    .NOT.             Logical NOT                  1           Unary
   .LOW.                Low byte                   1           Unary
   .HIGH.               High byte                  1           Unary
  .LWRD.                Low word                   1           Unary
  .HWRD.               High word                   1           Unary
       *              Multiplication               3           Binary
       /                 Division                  3           Binary
       +                 Addition                  4           Binary
       -               Subtraction                 4           Binary
   .MOD.                 Modulo                    3           Binary
    .SHR.           Logical shift right            3           Binary
    .SHL.            Logical shift left            3           Binary
    .AND.             Logical AND                  5           Binary
     .OR.              Logical OR                  6           Binary
    .XOR.             Logical XOR                  6           Binary
     .EQ.                Equal††                   7           Binary
    .NE.               Not Equal††                 7           Binary
    .GE.           Greater or equal††              7           Binary
    .LE.            Less or equal††                7           Binary
    .GT.             Greater than††                7           Binary
    .LT.              Less than††                  7           Binary
   .UGT.         Unsigned greater than††           7           Binary
    .ULT.         Unsigned less than††             7           Binary
†Operators apply to A68K. Different assemblers may support different
   operators.
††Relational operators return 1s (true) or 0s (false).
                                                                        T4-1




                                   TM-59
            Examples of
       Assemble-Time Operators


 1   00000064              COUNT     EQU    100
 2   00002000                        ORG    $2000
 3   00002000   3A3CFFFF             MOVE   #-1,D5
 4   00002004   3A3C0009             MOVE   #4+50/10,D5
 5   00002008   3A3C0001             MOVE   #25.mod.6,D5
 6   0000200C   3A3C0400             MOVE   #$8000.shr.5,D5
 7   00002010   3A3C0040             MOVE   #$45&$F0,D5
 8   00002014   3A3C0041             MOVE   #.high.'AB',D5
 9   00002018   3A3CFFFF             MOVE   #5.gt.4,D5
10   0000201C   3A3C0032             MOVE   #COUNT/2,D5
11   00002020                        END


                                                        F4-5




                             TM-60
                 Assembler Directives

Directive            Operation                              Syntax

ORG         set program origin                       ORG      value

EQU         equate value to symbol         symbol EQU         value

END         end of source program                    END      label

DC          define data constant           [label]   DC       number[,number][...]

DS          define RAM storage             [label]   DS       count

RSEG        begin relocatable segment                RSEG     name

EXTERN      define external symbol                   EXTERN symbol[,symbol][...]

PUBLIC      define public symbol                     PUBLIC symbol[,symbol][...]


                                                                                T4-2




                                        TM-61
                   Listing Examples

     Address    Contents   ***************   CH4-6.SRC *********************
 1   00001000                     ORG        $1000
 2   00001000   1A3C0064   START MOVE.B      #100,D5
 3   00000064              COUNT EQU         100
 4   00002000                     ORG        $2000
 5   00002000   1A3C0064   HERE   MOVE.B     #COUNT,D5
 6   0000000D              CR     EQU        $0D        define a symbol
 7   00003000                     ORG        $3000      set origin
 8   00003000   0005FFFF   NUM    DC         5,-1       word size default
 9   00003004   05FF       MORE   DC.B       5,-1       byte size constants
10   00003006   4A4F484E   NAME   DC.B       'JOHN'     ASCII string
11   0000300A   0D00              DC.B       CR,0       CR is a symbol
12   00004001                     ORG        $4001
13   00004002   000F       VALUE DC          15         decimal constant
14   00005000                     ORG        $5000
15   00005000   6100              DC.W       'a'
16   00000050              LENGTH EQU        80
17   00006000                     ORG        $6000
18   00006000              BUFFER DS.B       LENGTH
19   00006050              TEMP   DS.B       1
20   00007000                     ORG        $7000
21   00007000   7250              MOVE.L     #LENGTH,D1 use R1 as counter
22   00007002   327C6000          MOVEA      #BUFFER,A1 A1 points to buff
23   00007006   12FC0000   LOOP   MOVE.B     #0,(A1)+   clear location
24   0000700A   5301              SUBQ.B     #1,D1      done?
25   0000700C   66F8              BNE        LOOP       no: clear again
26   00000000                     RSEG       EPROM
27   00000000   1A3C002C   BEGIN MOVE.B      #44,D5
28   00000004                     END



                                                                      F4-8




                                  TM-62
                                    Linker Operation


                                                           P ROG .H EX
       F ILE 1 . OB J                                                                  Le g en d :

           FIL E 2 .O BJ                                                                               Ut i lit y pr o g r a m
                                     X LIN K
               F ILE 3 . OB J
                                                                                                       Us er f ile
                   F ILE 4 . O BJ
                                                           PRO G. MA P


( a)




                                                                         O pt i o ns
       Co m m an d
                                                                          f o llo w            A bso l u t e
                           CPU                                                               o u t p u t f i le
                                                In p ut                                       f o r m at t e d              L ist in g
                                                 f ile s                                    in S- r ec o r d s                 f ile


             XL IN K 6 8 K F IL E1 .OBJ FIL E2 .O BJ FIL E3 .O BJ FIL E4 .OB J / O= PROG.H EX M= PRO G.M A P
( b)




                                                                                                                        F4-10




                                                 TM-63
 User Mode vs. Supervisor Mode

    Feature                   User Mode          Supervisor Mode

          Entered by     Clearing S-bit in SR   Exception processing

               FC2 =                  0                  1

 Active stack pointer            USP                   SSP

  Other stacks using            A0 - A6             USP, A0-A6

          SR access
              Read:          Entire SR               Entire SR
              Write:        CCR bits only            Entire SR

Instructions available   All except                     All
                         AND #data,SR
                         EOR #data,SR
                         MOVE <ea>,SR
                         MOVE USP,An
                         MOVE An,USP
                         OR #data,SR
                         RESET
                         RTE
                         STOP

                                                                 T6-1




                                TM-64
      Changing Between
User Mode and Supervisor Mode


              T ra ns it io n m a y o cc ur o n ly
             d ur in g ex ce pt io n p r o ce ssing



    U ser                                             Su pe rv isor
    M o de                                               Mo d e



                    T ran sit io n m ay o ccu r
                t h r o u gh f o u r in st r uc t io n s:
                              MOV E t o SR
                              A N DI t o SR
                              EOR t o SR
                              RT E

                                                                      F6-1




                              TM-65
                                            Exception Tree


                                                      Exc ep t ion




                        Ext e r n al                                                               Int e r na l




                                                                                                                        Exec ut io n
      In t er r u p t                                In st r uc t io n
                                                                                                                          Er r o r




                                                        T RA P                                                          A - lin e o r
 Use r          A ut o         Bu s                                                  D iv id e-        Pr iv ileg e                     A d dr ess       Ille g al
                                          Re s e t     T RA PV           T r a ce                                         F- line
V e ct o r     V e ct o r      Er r o r                                             b y - ze r o       V io la t io n                     Er r o r   In s t r uc t io n
                                                         CH K                                                           Em ula t io n



                                                                                                                                                F6-2




                                                                          TM-66
Exception Processing Sequence


         St art e xc ep t ion


          Ma ke in t ern al
           c op y of SR


           S = 1, T = 0



                                  y es    Up d at e in t e rru p t
              Int err up t
                   ?                         m a sk lev el

                        no



           Ob t a in v ec t o r
              n um be r



        V ec t o r a dd re ss =
        ve ct or n u m b er x 4



       Pus h PC an d c o pie d
          SR o n t o st ac k



        ( V ec t o r ad d re ss)
              -----> PC



       C on t in u e e xe cu t io n

                                                                     F6-3




                                  TM-67
   Stack Frame for Exceptions

(except bus error and address error)


                     Hig h -Me m o r y


         15                                        0


   n+6                                                 SP ( old )

   n+4        Pro g r am Co u nt e r ( lo w )

   n+2        Pr o g ra m C o un t e r (h ig h )

    n               St at u s Re g ist e r             SP ( n ew )




                      Lo w -Mem or y
                                                                     F6-4




                                  TM-68
       Exception Vector Address


A3 1                  A 10   A9     A8       A7   A6     A5     A4   A3   A2   A1   A0


       all ze r o s          V7     V6       V5   V4     V3     V2   V1   V0   0    0
                             1    4      4    4     2     4      4   4    3
                                             V e ct o r n u m b er


                                                                                F6-5




                                 TM-69
Reset and Exception
Vector Assignments
  Vector           Hexadecimal
  Number             Address                       Assignment
    0                  000                          Reset SSP†
      –                  004                        Reset PC†
      2                  008                         Bus Error
      3                 00C                        Address Error
      4                  010                     Illegal instruction
      5                  014                      Divide-by-zero
      6                  018                     CHK instruction
      7                 01C                     TRAPV instruction
      8                  020                     Privilege violation
      9                  024                           Trace
      10                 028                    Line 1010 emulator
      11                02C                     Line 1111 emulator
      12                 030                         (reserved)
      13                 034                         (reserved)
      14                 038                   Format error (68010)
      15                03C                Uninitialized interrupt vector
    16-23             040-05C                        (reserved)
      24                 060                   Spurious interrupt††
      25                 064               Level 1 interrupt autovector
      26                 068               Level 2 interrupt autovector
      27                06C                Level 3 interrupt autovector
      28                 070               Level 4 interrupt autovector
      29                 074               Level 5 interrupt autovector
      30                 078               Level 6 interrupt autovector
      31                07C                Level 7 interrupt autovector
    32-47             080-0BC             TRAP instruction vectors†††
    48-63             0C0-0FC                        (reserved)
   64-255             100-3FC                 User interrupt vectors
† The reset vector is four words and resides in the supervisor program (SP)
space. All other vectors reside in the supervisor data (SD) space.
†† The spurious interrupt vector is taken when there is a bus error during an
interrupt acknowledge cycle.
††† Trap #n uses vector number 32 + n. See Table 6-5.



                                                                                T6-2




                                  TM-70
Exception Grouping and Priority

Group      Exception                       Processing

  0          Reset               Exception processing begins
          Address Error           within two CPU cycles
            Bus Error

  1             Trace            Exception processing begins
              Interrupt           before the next instruction
        Illegal Instruction
        Privilege Violation

  2      TRAP, TRAPV             Exception processing begins by
             CHK                  normal instruction execution
          Zero Divide

                                                                  T6-3




                              TM-71
       Traps vs. Subroutines
  Features                     Traps          Subroutines

         Initiated from     user mode or      user mode or
                           supervisor mode   supervisor mode

  Routine executes in      supervisor mode    user mode or
                                             supervisor mode
      Registers saved        PC and SR             PC

  Registers saved on        system stack      user stack or
                                              system stack
    Routine ends with           RTE               RTS

Privilege state after is    user mode or      user mode or
                           supervisor mode   supervisor mode

                                                               T6-4




                             TM-72
Vector Assignments for
  TRAP Instructions
  Instruction   Vector    Vector
                Number   Address
 TRAP #0          32     $000080
 TRAP #1          33     $000084
 TRAP #2          34     $000088
 TRAP #3          35     $00008C
 TRAP #4          36     $000090
 TRAP #5          37     $000094
 TRAP #6          38     $000098
 TRAP #7          39     $00009C
 TRAP #8          40     $0000A0
 TRAP #9          41     $0000A4
 TRAP #10         42     $0000A8
 TRAP #11         43     $0000AC
 TRAP #12         44     $0000B0
 TRAP #13         45     $0000B4
 TRAP #14         46     $0000B8
 TRAP #15         47     $0000BC
                                   T6-5




                TM-73
                  Stack Frame for
            Bus Error and Address Error


                               Hig h - Me m o ry


                    15                                       0

            n+1 4                                                     SP (o ld )

            n+1 2        Prog r a m Co u nt er ( lo w )

            n+1 0        Pr o g ram Co u n t e r ( h ig h)

             n+ 8             St at us Re g ist e r

             n+ 6          In st ruc t io n Re g is t e r

             n+ 4         Ac ce s s ad d r es s ( lo w )

             n+ 2         A c c ess a dd re ss (h ig h )

               n                 A cc es s t yp e                     SP ( ne w )




                                Lo w -M em o ry



( a)




       15                                             5      4    3   2    1       0

                    u n de f in ed                          R/ W I/ N FC 2 FC1 FC 0
                                                                      142 4 3

                                                                                       Fu nc t io n C o de
                                                                                       I/ N
                                                                                          0 = in s t r uc t io n
                                                                                          1 = n o t a n in st r u ct io n
                                                                                       R/ W
                                                                                          0 = w r it e c yc le
                                                                                          1 = re ad cy cle
( b)




                                                            TM-74
        F6-6




TM-75
                           Power-on Reset Timing

                                                           ...
        CL K


           +5V
     Vcc
            0V

                                                         > 100 ms

     RESET



      H A LT

                                                      < 4 c lo c ks                          1
B u s Cyc les                                                                                         SS P H SSP L PC H PC L
                                                                                                     14 42 44 3 1 44 24 43                       4 44
                                                                                                                                                1 42
                                                                                                        In it ializ e SSP   In it ializ e P C   E xec ut e 1 st
                                                                                                                                                 in st ru c t io n
                 L eg e nd :

                                                                              A ll c o nt r o l sig n als in ac t ive .
                      1        Int er na l st art -u p t im e                 D at a b us in r ea d m o d e

                               Bus s t at e u n kn ow n                       Bu s c y cle ( m e m o ry r e ad o r m em o r y w r it e )




                                                                                                                                                F6-7




                                                                      TM-76
A Switch as an Input Device and an
    LED as an Output Device


                                             +5 V

                                                                   Sw it c h   L ED
                                                    Re sist o r
                                                                   OPEN        OF F
        Sw it c h                     LED            22 0 Ω
                                                                  CL OSED       ON
                         W ir e



( a)


                                             +5 V

                                                                   Sw it c h   L ED
                                                Re sis t o r
                                                                   OPEN          ?
       Sw it c h                     L ED        22 0 Ω
                                                                  CL OSED        ?
                    Co m p u t e r



( b)

                                                                                 F7-1




                                     TM-77
          Interface to Switches and LEDs
                    (conceptual)

                                                           D at a Bu s


                      Ad d re ss Bus
                                                                                                     L ED # 7
                                                                                                                 +5 V
                                                   D15                             D1 5
                                                                                             D   Q
6 800 0
                                                   D14                             D1 4
                                                                                             D   Q
                                                   D13                             D1 3
                                                                                             D   Q
              A23                                               A2 3
                                                   D12                             D1 2
              A22                                               A2 2                         D   Q
          0   A21
              A20
                                                   D11     0    A2 1
                                                                A2 0
                                                                                   D1 1
                                                                                             D   Q
              A19                                  D10          A1 9               D1 0
                                                                                             D   Q

          0   A18
              A17
              A16
                                                    D9     0    A1 8
                                                                A1 7
                                                                A1 6
                                                                                        D9
                                                                                             D   Q
                                                    D8                                  D8
              A15                                               A1 5                         D   Q
              A14                                               A1 4
          C   A13
              A12
                                                           C    A1 3
                                                                A1 2     WRIT E LED S
                                                                                                      L ED # 0

                        REA D SWIT C HES
              A11                                               A1 1
              A10                                               A1 0
          0    A9
               A8
                                                           0      A9
                                                                  A8
               A7                                                 A7
               A6                                                 A6
          0    A5
               A4
                                                           0      A5
                                                                  A4
               A3                                                 A3
               A2                                                 A2
          0    A1
              UD S
                           +5 V
                                                           0     A1
                                                                U DS
                AS                                                AS
              R/ W                                              R/ W

                     D T A CK


                                Co n t ro l Bu s




                                                                                                     F7-2




                                                   TM-78
      Timing for MOVE.B $00C000,D0

                                                Hig h- w o rd o f        Lo w - w o rd o f    Me m o ry
                            Op co d e              a d dr ess               ad d re ss        lo ca t io n
                             f et ch              ( $0 000 )               ( $ C0 0 0 )      $ 0 0 C0 0 0


                            Mem or y                  M em o ry              Me m o r y       M em or y
                             r e ad                     r e ad                r ea d            r e ad

CPU clo ck :
                    2
                   13
               One clo ck
                                             t im e
                p er io d


     t hre e - st a t e
  b uf f ers e na b led
                                                                                                  D a t a f r o m sw it ch e s
                                                                                                  lat ch ed int o r eg ist er
                               S0       S1       S2      S3      S4     S5    S6    S7
                                                                                                     D 0 , b it s 0 -7 , a t
                                                                                                      t h e st ar t of S7
                     CL K

            F C0 -FC2


               A1 - A 2 3                                     $ 0 0 C0 0 0

                     AS

                     UDS


                    LD S


                   R/ W


                DT A CK


               D 8 -D1 5                                       sw it c h d at a

                D 0 -D7

                                                                                                                         F7-3




                                                                  TM-79
          Example of Partial Decoding


       A 23                                                                              A 23
       A 22                                                                              A 22
0      A 21
       A 20
                                                                                 0       A 21
                                                                                         A 20
       A 19                                                                              A 19

0      A 18
       A 17
       A 16
                                                                                 0       A 18
                                                                                         A 17
                                                                                         A 16
                                           REA D SW IT CH ES                                                             W RIT E L ED S
       A 15                                                                              A 15
       A 14                                                                              A 14
C      A 13
       A 12
                                                                                 C       A 13
                                                                                         A 12
       UDS                                                                               UDS
         AS                                                                                AS
       R/ W                                                                              R/ W

( a)



              A d dr e ss:

              A23                A19                A15               A1 1               A7                 A3           A0
               0    0   0    0    0    0    0   0    1    1   0   0    X     X   X   X    X     X   X   X   X    X   X   0


                    0                  0                      C                  X                  X             X0
                                                                                                                 XX
(b )

                                                                                                                                  F7-5




                                                              TM-80
                         Flowcharts for
                     Program-Conditional I/O


In pu t F lo w c h ar t :                                 O ut p ut Flo w c h a r t :



                                E nt er                                                   En t e r




                            Rea d D e v ic e                                        Re ad D ev ice
                            S t a t u s Flag                                        S t at us F la g




                NO             D e vic e                                  NO             De v ic e
                               Re ad y                                                   Rea d y
                                   ?                                                        ?


                                           YE S                                                    Y ES




                                In p ut                                                  Ou t p u t
                                 D at a                                                   Da t a




                              Clea r Flag                                               Cle ar Fla g




                                   Ex it                                                    Exit



( a)                                                      (b )

                                                                                                          F7-7




                                                  TM-81
                     Keyboard Interface

                                          D a ta Bu s


                                                                                                   D8
       Ke yb o ard

                                                                             D1 5
                KBD                       D          Q
               D A TA                                                        D1 4
                                          D          Q
                                                                             D1 3
                                          D          Q
                                                                             D1 2
                                          D          Q
                                                                             D1 1
                                          D          Q
                                                                             D1 0
                                          D          Q

                                          D          Q                       D9

                                                                             D8
                                          D          Q



                                                                                          F L AG

                          K EYH IT
                                                                                  S
                                                                                      Q
                                                                                  R




                                        REA D K BD D A T A

                                      REA D KBD ST A T U S


( a)


                                                             Da t a ar e st o re d
                                        A k ey is              in lat ch an d
                                        pr ess e d              f la g is se t




                        KBD DA T A                       V alid D at a


                           K EYH IT

( b)

                                                                                                        F7-6



                                              TM-82
    Interface Using a
  Peripheral Interface IC


                       Da t a B us

CPU                  A d dr ess Bu s


                     Co nt ro l Bus



                           Pe r ip h e r al In t er f a ce IC
                         A1           Re ad       W rit e
                         A0
                                     St at us    C o nt ro l
                         R/ W          e t c.      etc .

                                       e t c.      etc .
      A d d r e ss
                         CS           In p u t   Ou t p u t
      D ec o din g




                                Pe ri p h er a l Dev ic e
                                                                F7-9




                      TM-83
                                 Program Execution
                                 Without Interrupts or
                                    With Interrupts

                                     t im e


                                                                          M ain P r o g r am


( a)




       Int er r up t - le v el
                                                  ISR                           ISR                                                        ISR
       exe c u t io n


                                              *         **            *                        **                                      *            **


       Base - lev el
                                 M ain                       Ma in                                           M ain                                       Ma in
       exe c u t io n



                                                                                                *   Int er r up t
                                                                                               **   Ret ur n f r o m int e r r up t in s t r uc t io n
( b)

                                                                                                                                                         F7-11




                                                                     TM-84
      Interrupt Priority Conditions on -
            IPL2, -IPL1, and -IPL0


      Signal

IP2     IP1    IP 0   Interrupt    Condition     Maskable   Priority

1       1       1        0        No interrupt      -          -

1       1       0        1          Interrupt      Yes      Lowest

1       0       1        2          Interrupt      Yes       (etc.)

1       0       0        3          Interrupt      Yes       (etc.)

0       1       1        4          Interrupt      Yes       (etc.)

0       1       0        5          Interrupt      Yes       (etc.)

0       0       1        6          Interrupt      Yes       (etc.)

0       0       0        7          Interrupt      No       Highest

                                                                      T7-3




                                  TM-85
   Autovectors for
Automatic IACK Cycles
                Vector Address
   Interrupt     (Autovector)

      0                   -

      1                $000064

      2                $000068

      3                $00006C

      4                $000070

      5                $000074

      6                $000078

      7                $00007C
                                 T7-4




               TM-86
Vector Addresses for
 User IACK Cycles

Vector Number       Vector Address

      0                 $000000

      1                 $000004

      2                 $000008

     etc.                 etc.

    255                 $0003FC
                                     T7-5




                TM-87
                                    Interrupt Circuitry


                                                                          +5 V
                                                                                                   74 07
                                                                                1 0K
                                                            V PA



                                                   680 00                                       7 4 HC 1 3 8

                                                             A3                                  C         7        IA C K 7
                                                             A2                                  B         6        IA C K 6
N o n - Mas k ab le
                                                             A1                                  A         5        IA C K 5
In t er r u p t ( NM I)
                                                                                                           4        IA C K 4
                                                                                         +5 V
                                                                                                           3        IA C K 3
                                                                                                 E1        2        IA C K 2
                                                                                                 E2        1        IA C K 1
                 +5 V       7 4 H C1 4 8                                                         E3        0

IN T 7                       7     A2      IPL 2
IN T 6                             A1                                     7 4 H C1 3 8
                             6             IPL 1
IN T 5                       5     A0      IPL 0            FC 2           C       7      IA ( In t e rr up t Ac k n o w led g e )
IN T 4                       4                              FC 1           B       6      S P ( Sup e r v is o r P r og r a m )
IN T 3                       3                              FC 0           A       5      S D ( Su p e r v is o r Da t a )
IN T 2                       2                                                     4
IN T 1                       1                                     +5 V            3
                     +5 V    0                                             E1      2      UP ( Us er P ro g ram )
                                                             AS            E2      1      UD ( Us er D at a)
                             E1                                            E3      0


                                                                                                                        F7-12




                                                      TM-88
Bus Connections for DMA Interface


                                           Da t a Bu s
  CPU
                                         A dd re ss Bu s

                                         C o nt ro l Bu s




                         DMA
        Me m o r y                          Dev ic e
                      Co n t r o lle r


                                                            F7-13




                     TM-89
      Device-to-Memory
     Transfer Using DMA


              D at a Bu s


         A dd re ss Bu s

             Co n t r o l Bus




                                   DMA
Me m o r y                                         Dev ic e
                                Co n t ro l le r


                                                              F7-14




                                 TM-90
  68000 Bus Arbitration
     Control Signals



68 000
 CPU                         D MA
                           Co nt ro lle r

         BR           BR

         BG           BG

    BGA CK            BGA CK

                                            F7-15




              TM-91
                  Bus Arbitration


                     6 8 0 0 0 CPU                        DMA Co n t r ol le r

                                                           Re qu e st t he Bus

                                                  1 . A ssert b us r e q ue st
                                                      ( BR = 0 )

                   Gr an t t he Bus

         1 . A sse r t b u s g ran t ( BG = 0 )

                                                  A ckn o w le dg e Bus M ast er sh ip

                                                  1 . A ssert b us g r a nt
                                                      a ck no w le d ge (B GA CK = 0 )

                                                  2 . Ne g at e b u s req u e st
                                                      ( BR = 1 )


           Ter m ina t e Bus A rb it r a t io n

         1 . Ne g at e b u s gr an t ( BG = 1 )
             a nd w a it f o r BGA CK t o be
             n e ga t e d

                                                      Op er a t e as Bu s Mast e r

t im e                                            1 . Pe r f o r m d at a t r an sf e rs
                                                      acc o r d in g t o sam e r u les
                                                      t h e CPU u se s




                                                      Rele ase Bu s M ast ersh ip


                                                  1 . Ne g at e b u s g ran t
                                                      ack no w le d g e ( BGA CK = 1 )

          Resu m e N o rm a l Pr o ce ssing

                                                                                       F7-16




                                         TM-92
     Timing for Bus Arbitration


                                          t im e


   BR


   BG



BGA CK


         1 2 3      1   4   4   2     4      4     3   1 2 3
           CPU                   DM A                    C PU
          cy cles               cy cles                 cy cle s

                                                                   F7-17




                            TM-93
              Block Diagram of the 68KMB


                                                  T e rm ina l/        M isce lla n eo u s
                                              H o st Co m p u t e r    In pu t / Ou t p u t
                  68 000                                                   De vic es
                   CPU

 Sy st e m
  Cloc k                                                  6 8 6 8 1 DUA RT




  Re s e t
                                               Sy st e m Bu ses
  Cir c uit




Int e r rup t              A dd r e ss       Mo nit o r           U ser
                                                                                   RAM s
  Circ u it                D ec od e         EPRO Ms            EPRO Ms
                                                                                   ( 1 6 K)
                            Cir c uit         (1 6 K)            ( 1 6 K)


 Ext e rn al
Int err u p t s



                                                                                              F8-3




                                     TM-94
                              68000 CPU


                                                                 52
                                                          A2 3
                                                          A2 2   51

                                                          A2 1   50
                             14, 49                              48
                      +5 V            V cc                A2 0
                                                          A1 9   47
                             16, 53                              46
                                      G ND                A1 8
                                                          A1 7   45
                                                  68000   A1 6   44
                                                                 43
                                15
                                                   CPU    A1 5
                                                          A1 4   42
                                      C LK
                                                          A1 3   41

                                                          A1 2   40   A d d r es s
               +5 V                                              39      Bu s
                                                          A1 1
                                20                               38
                                      E                   A1 0
                                19                         A9    37
                                      V MA
                                21                         A8    36
                                      V PA
                                                           A7    35

                                13                         A6    34
                                      BR
                                11                               33
                                      BG                   A5
                                12                         A4    32
                                      B G A CK
                                                           A3    31
                                 6                         A2    30
                                      AS
                                 9                               29
                                      R/ W                 A1
Co n t r o l                     7
                                      U DS
  Bu s                           8    L DS
                                10                               54
                                      D T A CK            D1 5
                                                          D1 4   55

                                28                               56
                                      F CO                D1 3
                                27                               57
                                      F C1                D1 2
                                26                        D1 1   58
                                      F C2
                                                          D1 0   59
                                25                         D9    60
                                      IPL 0
                                24                               61
                                      IPL 1                D8           D at a
                                23                               62
                                      IPL 2                D7           Bu s
                                                           D6    63
                                22                               64
                                      B ERR                D5
                                18    RESET                D4    1
                                17                         D3    2
                                      H A LT
                                                           D2    3
                 7 X                                       D1    4
               1 0 KΩ                                            5
                                                           D0



                                                                                     F8-4




                                               TM-95
                      68KMB Clock Circuit


     7 4 HC 1 4
                      0 . 0 1 µF                        47 Ω
       1          2                3   4     5     6
                                                               C LK              to
                                                                               680 00

             1K          1K



10
                      3.68 64               13     12
pF                                                                               to
                        MHz                                    BA U D CL K
                                                                               686 81


                                                                        F8-6




                                           TM-96
                   68KMB Reset Circuit


          +5 V      +5 V



    1N           1 0K
                                     7 4 HC1 4         7 407
   9 14
                            9        8            10
                                          11           3       4
                                                                   RESET
                                                                                     to
  100 Ω                                                        2
                                                                                   68 000
                        +                              1
                            2 2 µF                                 H A LT

RESET




                                                                            F8-7




                                          TM-97
                            68KMB Interrupt Circuit


                              M ON IT OR
                                                  +   2 2 µF




                                                          +5V   7 x         7 4 HC1 4 8
                                                                10K
                                                                        4                 6
                             IN T 7                                          7     A2                                        IPL 2
                                                                        3                   7
                   IN T 6                                                    6     A1                                        IPL 1
                                                                                            9
 Ext er na l       IN T 5
                                                                       2
                                                                             5     A0                                        IPL 0        to
                                                                       1                                                                68 000
In t e r ru pt s   IN T 4                                                    4                              740 7
                                                                       13
                             IN T 3                                          3
                                                                       12                 15               13       12
                             IN T 2                                          2     E0                                        V PA
                                                                       11                 14
                             IN T 1                                          1     GS
                                                                       10
                                                                +5 V         0                             11       10

                                      X1 6                             5
                                                                             E1
                                                                                                            5       6


                                                                                       7 4 H C1 3 8
                                                                                   3                  7
                     A3                                                                 C        7                  IA CK7
                                                                                   2                  9
                     A2                                                                 B        6    10            IA CK6
                                                                                   1
                     A1                                                                 A        5                  IA CK5
                                                                                                      11
                                                                                                 4    12            IA CK4
                                                                            +5V
                                           7 4 H C1 3 8                            6
                                                                                                 3                  IA CK3                to
                                                                                                      13
                                                                                        E1       2                           IA CK 2
     f ro m                            3                   7    IA                 4                  14                                686 81
                    FC 2                     C        7                                 E2       1                  IA CK1
    680 00                             2                   9                       5                  15
                    FC 1                     B        6         SP                      E3       0
                                       1                   10
                    FC 0                     A        5         SD
                                                           11
                                                      4    12
                            +5 V                      3
                                       6                   13
                                             E1       2         UP
                                       4                   14
                     AS                      E2       1         UD
                                       5                   15
                                             E3       0



                                                                                                                                     F8-8




                                                                      TM-98
            68KMB Address Decoding


                         1                        19
          A20                I0              O8                    EPROM 0 U
                         2                        18
          A19                I1              O7                    EPROM 0 L
                         3                        17
          A18                I2              O6                    EPROM 1 U           t o EPRO M,
                         4                        16
          A17                I3     1 6 L8   O5                    EPROM 1 L        RA M , & D UA RT
                         5                        15
          A16                I4              O4                    RA M0 U        c hip se le ct inp u t s
 f ro m                  6                        14
          A15                I5              O3                    RA M0 L
68 000                   7                        13
          A14                I6              O2                    D UA RT
                         8                        12
          UD S               I7              O1
                         9
          LDS                I8                        9           8
                        11
           AS                I9                                        D T A CK    t o 6 800 0
                        20
                 +5 V        Vc c                          7 407
                        10
                             GN D




                                                                                      F8-9




                                        TM-99
              68KMB Memory Map


FFFFFE




               Re f le ct ed                  7 M w o rd s




200000
1FFFFE


               Ex pa ns io n                9 9 2 K w o rd s



010000
                                                                                        8 M w o rd s
00FFFE                                                                               ( 1 6 M b y t e s)
                                              8 K w or d s
                               D UA RT
                                                 ( I/ O)
00C000
                                                                   1 M w o rd s
00BFFE
                                                                  ( 2 M b y t e s)
         RA M0 U               RA M 0 L        8 K w or d s
008000                                     ( syst e m / u ser )

007FFE
         EPROM1 U         EPROM1 L            8 K w or d s
                                                ( u ser )
004000
003FFE
                                             8 K w o rd s
         EPROM0 U         EPROM0 L
                                             ( MON 6 8 K)
000000

                                                                                                  F8-10




                                          TM-100
                         Monitor EPROMs


                                  2                                   19
                           A13         A1 2                     D7                D15
                                  23                                  18
                           A12         A1 1                     D6                D14
                           A11
                                  21   A1 0   2764A             D5
                                                                      17
                                                                                  D13
                           A10    24   A9                       D4    16
                                  25
                                              EPROM                   15
                                                                                  D12
                            A9         A8                       D3                D11
                                  3    A7                             13
                            A8                                  D2                D10
          f r om                  4           ( m o nit or )          12
                            A7         A6                       D1                D9
         68 000             A6
                                  5    A5                       D0
                                                                      11
                                                                                  D8
                                  6
                            A5         A4
                                  7                                        + 5V
                            A4         A3
                                  8                                   28
                            A3         A2                      V cc
                                  9                                   1
                            A2         A1                      Vpp
                                  10   A0                             27
                            A1                                 PGM


                                                                      22                t o / f ro m
                                                                OE
                                                                                          680 00
f ro m A d dr ess                 20                                  14
                       EPROM0 U        CS                      GN D
D ec od e Cir cu it




                                  2                                   19
                           A13         A1 2                     D7                D7
                                  23                                  18
                           A12         A1 1                     D6                D6
                           A11
                                  21   A1 0   2764A             D5
                                                                      17
                                                                                  D5
                                  24                                  16
                           A10         A9     EPROM             D4                D4
                                  25                                  15
                            A9         A8                       D3                D3
                                  3    A7                             13
                            A8                                  D2                D2
                                  4                                   12
          f ro m            A7         A6     ( m o nit or )    D1                D1
                                  5    A5                             11
         680 00             A6                                  D0                D0
                                  6
                            A5         A4
                                  7                                        + 5V
                            A4         A3
                                  8                                   28
                            A3         A2                      V cc
                                  9                                   1
                            A2         A1                      Vpp
                                  10   A0                             27
                            A1                                 PGM


                                                                      22
                                                                OE

f ro m A dd r e ss                20                                  14
                       EPROM0 L        CS                      GN D
De co d e C ir cu it


                                                                                                       F8-12




                                            TM-101
                            User EPROMs

                                  2                                19
                           A13         A12                   D7                D1   5
                                  23                               18
                           A12         A11                   D6                D1   4
                           A11
                                  21   A10    2764A          D5
                                                                   17
                                                                               D1   3
                                  24                               16
                           A10         A9     EPROM          D4                D1   2
                                  25                               15
                            A9         A8                    D3                D1   1
                                  3    A7                          13
                            A8                  (u se r )    D2                D1   0
          f ro m                  4                                12
                            A7         A6                    D1                D9
         6 800 0                  5    A5                          11
                            A6                               D0                D8
                                  6
                            A5         A4
                                  7                                     +5 V
                            A4         A3
                                  8                                28
                            A3         A2                   Vc c
                                  9                                1
                            A2         A1                   Vp p
                                  10   A0                          27
                            A1                              PGM


                                                                   22                   t o/ f ro m
                                                             OE
                                                                                         68 000
f ro m A d d r ess                20                               14
                      EPROM 1 U        CS                   GND
D ec o de Cir cu it




                                  2                                19
                          A13          A12                   D7                D7
                                  23                               18
                          A12          A11                   D6                D6
                          A11
                                  21   A10    2764A          D5
                                                                   17
                                                                               D5
                                  24                               16
                          A10          A9     EPROM          D4                D4
                                  25                               15
                           A9          A8                    D3                D3
                                  3    A7                          13
                           A8                                D2                D2
          f ro m           A7     4    A6       ( use r )    D1    12
                                                                               D1
         680 00                   5    A5                          11
                           A6                                D0                D0
                                  6
                           A5          A4
                                  7                                     +5 V
                           A4          A3
                                  8                                28
                           A3          A2                   Vc c
                                  9                                1
                           A2          A1                   Vp p
                                  10   A0                          27
                           A1                               PGM


                                                                   22
                                                             OE

f ro m A d dr ess                 20
                                       CS                          14
                      EPROM1 L                              GND
D ec od e Cir cu it


                                                                                                      F8-13




                                            TM-102
                      System/User RAM


                                2                         19
                        A13          A12             D7              D1   5
                                23                        18
                        A12          A11             D6              D1   4
                        A11
                                21   A10     6264    D5
                                                          17
                                                                     D1   3
                        A10     24   A9              D4   16
                                25
                                             RA M         15
                                                                     D1   2
                         A9          A8              D3              D1   1
                                3    A7                   13
                         A8                          D2              D1   0
                         A7     4    A6              D1   12
                                                                     D9
           f ro m               5    A5                   11
                         A6                          D0              D8
         6 800 0                6
                         A5          A4
                                7                              +5V
                         A4          A3
                                8                         28
                         A3          A2             Vcc
                                9                         26
                         A2          A1
                                10   A0
                         A1


                                27   W
                                                          22                  t o / f ro m
                        R/ W                         OE
                                                                               68 000
f r o m A d dr ess              20                        14
                      RA M0 U        CS             GND
D ec od e Cir cu it




                                2                         19
                        A1 3         A12             D7              D7
                                23                        18
                        A1 2         A11             D6              D6
                        A1 1
                                21   A10     6264    D5
                                                          17
                                                                     D5
                                24                        16
                        A1 0         A9      RA M    D4              D4
                                25                        15
                         A9          A8              D3              D3
                                3    A7                   13
                         A8                          D2              D2
                                4                         12
                         A7          A6              D1              D1
           f ro m               5    A5                   11
                         A6                          D0              D0
         6 800 0                6
                                     A4
                         A5                                    +5V
                                7
                         A4          A3
                                8                         28
                         A3          A2             Vcc
                                9                         26
                         A2          A1
                                10   A0
                         A1


                                27                        22
                        R/ W         W               OE

f ro m A d dr e ss              20                        14
                      RA M0 L        CS             GND
D ec od e Cir cu it


                                                                                             F8-14




                                           TM-103
                                                   68681 DUART


                                                                                                                                     J3
                                                                                                                                    D B2 5 S
                                        25                                30             11                      2          3
                                D7            D7                  TxD A                           T1 I   T1 O
                                         16
                                D6            D6
                                         24
                                D5            D5                          31             12                                 2
                                         17                                                                      14                               T e r m ina l/
                                D4            D4                  Rx DA                           R1 0    R1 I
                                         23                                                                                 7                  H os t Co m p u t e r
                                D3            D3
                                        18
                                D2
                                        22
                                              D2         68681                                       MA X
                                D1
                                        19
                                              D1
                                                         DUA RT                                      232                             J8
                                D0            D0
            t o / f ro m                                                                                                            D B2 5 S
             68 000                     34                                11             10                      7          3
                             RESET            RESET               TxD B                           T2 I   T2 O
                                        8
                               R/ W           R/ W
                                        9                                                                                                      O p t io n al
                            D T AC K          D T A CK                    10              9                      8          2
                                                                                                  R2 0    R2 I                                   Ser ia l
                                                                  Rx DB
                                        6                                                                                   7                     Por t
                                A4            RS4                                                                     +5V
                                        5
                                A3            RS3                                             1                  16
                                        3
                                A2            RS2                                   +             C1 +   Vcc            +
                                        1
                                A1            RS1                                             3                  2
                                                                                 4 X              C1 -    V+
       t o / f ro m                     21
                              IN T 2
                                        37
                                              IRQ                              1 0 µF         4                  6
In t e r r u pt Cir cu it   IA CK 2           IA CK                                               C2 +     V-
                                                                                     +                                  +
 f r om A d d r e ss                    35                                                5                      15
                            D UA RT           CS                                                  C2 -   G ND
 D e co d e Cir c uit

       f r o m Clo ck        BA UD
                                        32
                                              C LK/ X1                                                                                J1
            Cir cu it         CL K
                                         33                               15                                                    8
                                              X2                   O P7   26                                                    7
                                                                   O P6
                                                                          14                                                    9
                                                                   O P5   27                                                    3
                                                                   O P4
                                                                          13                                                17
                                                                   O P3   28                                                    4
                                        40                         O P2   12                                                11
                                 + 5V         V cc                 O P1
                                                                          29                                                    5
                                                                   O P0                                                                         Mis c ellan e ou s
                                         20
                                              G ND                                                                                              Inp u t / Ou t pu t
                                                                          38                                                14
                                                                    IP5                                                                            D ev ic e s
                                                                          39                                                15
                                                                    IP4                                                     16
                                                                          2
                                                                    IP3   36                                                12
                                                                    IP2                                                     13
                                                                          4
                                                                    IP1
                                                                          7                                                     6
                                                                    IP0
                                                                                                                            20
                                                                                                                      +5V
                                                                                                                            10




                                                                                                                                        F8-15




                                                                  TM-104
Expansion to 6800 Peripherals


                                           J2
                                    1
                        D7
                                    2
                        D6
                                    3
                        D5
                                    4
                        D4
                                    5
                        D3          6
                        D2
                                    7
                        D1
                                    8
                        D0

                                    11
     t o / f ro m     A 16
       680 00
                                    14
                        A3
                                    15
                        A2                              Exp an sion t o
                                    16               6 8 0 0 Pe rip he r a ls
                        A1

                                    13
                     RESET
                                    18
                       V PA
                                    17
                          E
                                    19
                       R/ W

     t o / f ro m                   12
                      IN T3
    In t e r ru pt                  9
                         SD
       Circu it
                                    20
                              +5V
                                    10




                                         2 0 - pin
                                         h ea de r

                                                                                F8-16




                               TM-105
          68681 Interface to
         LEDs and Switches

                    (I/O Board #1)


686 81
                                                                     8 ×    +5 V
DU ART                    J1              7 4 LS2 4 4               220 Ω
               15     8              17                 3
     OP7
               26     7              15                 5
     OP6
               14     9              13                 7
     OP5
               27     3              11                 9
     OP4
               13     17             8                  12
     OP3
               28     4               6                 14
     OP2
               12     11             4                  16
     OP1
               29     5              2                  18
     OP0



                      20
                                                1, 19
                               +5V
                      10


                                                             +5 V

               38     14
         IP5
               39     15
         IP4
               2      16
         IP3
               36     12
         IP2
               4      13
         IP1
               7      6
         IP0
                                                    6 ×
                                                  1 0 kΩ


                                                                                   F9-3



                               TM-106
  Interface to Switches and
        7-Segment LED

                    (I/O Board #2)

686 81
DU ART               J1                                                            +5 V
                                     7 4 LS2 4 4
               15    8          17                 3            7 ×
     OP7                                                       22 0 Ω                      14, 3
               26    7          15                 5                     1
     OP6                                                                     a
               14    9          13                 7                    13             a
     OP5                                                                     b
               27    3          11                 9                    10
     OP4                                                                     c     f               b
               13   17          8                  12                    8             g
     OP3                                                                     d
               28    4           6                 14                    7
     OP2                                                                     e     e               c
               12   11          4                  16                    2             d
     OP1                                                                     f
               29    5          2                  18                   11
     OP0                                                                     g

                                                                                  MA N 7 2 A
                                           1, 19
                    20                                                           7 -s eg m e nt
                          +5V
                                                                                   co m m o n
                    10
                                                                                 an od e LED
                                                        +5 V


               2    16
         IP3
               36   12
         IP2
               4    13
         IP1
               7     6
         IP0
                                               4 ×
                                             1 0 kΩ

                                                                                                       F9-4




                                 TM-107
                4-Digit 7-Segment Display

                                                   (I/O Board #3)

                                                          +5 V

6 86 8 1            J1                                18
                                                          V cc
           28   4                     5                                            8 ×                                    4 × MA N 4 7 4 0 A
    O P2                                      DA TA
                                                                                  47 Ω
           12   11               13                                          4           14
    O P1                                      CL OCK                     a                    a
                                                                                              a
           29   5                12                                          3           13
    O P0                                      ENA BL E                                                   a                a                    a                        a
                                                                         b                    b
                                                                                              b
                                                                             2           8
                20                                                       c                    c
                                                                                              c
                               +5 V                  MC1 4 4 9 9                                     f          b     f          b       f               b          f           b
                                                                             1           7                  g               g                    g                         g
                10                                                       d                    d
                                                                                              d
                                                                             17          6
                                                                         e                    e
                                                                                              e      e          c     e          c       e               c          e           c
                                                                             16          1                  d               d                    d                         d
                                      6                                  f                    ff
                                              O SC
                                                                             15          2                      dp              dp                      dp                     dp
                    0 .0 1 5                                             g                    g
                       µF                 9
                                                                             14          4
                                              GN D                h (d p )                    dp

                                                                                                   4 ,1 2            4,12               4 ,1 2                    4 ,1 2
                                               D4     D3     D2     D1
                                               7      8    10     11                                                                                    4 ×
                                                                                                                                                     2 N3 9 0 4




                                                                                                                                                       F9-6




                                                                             TM-108
                   MC14499 Timing


                                           t im e

ENA BL E ( OP0 )


 CL OCK ( OP1 )


                   d1   d2    d3      d4            d1 9   d20
  D AT A ( OP2 )


                                                                 F9-7




                             TM-109
     MC14499 Digit and Bit Sequence


                                                              t im e


Bit N o .   1     2    3     4   5   6   7    8     9   10   11   12   13 14   15   16   17 18   19   20




            1 4 2 4 3 1 42 4 3 1 4 2 4 3 1 4 2 4 3 1 4 2 4 3
                De cim a l           Dig it             D ig it           D igit            Dig it
                 Poin t s             1                    2                3                 4


                                                                                                      F9-8




                                                  TM-110
8-Digit 7-Segment Display

      (I/O Board #4)




         D IGIT         SEG        D IGIT         SEG


          MC1 4 4 9 9               MC1 4 4 9 9

    DA TA                 h   D A TA                h
    CL OCK                    C LO CK
    EN ABL E                  EN AB LE                  et c.




                                                                F9-9




                    TM-111
                     68681 Input Expansion
                        Using 74LS165s

                                                                                                     Ex t e r n al Inp u t s

                J1

                                  L SB                                                                                                                                             MSB
6 868 1        20
D UA RT               + 5V
               10                6               4       3       14       13       12       11                       6         5       4       3       14       13       12       11
                                         5
                                     H       G       F       E        D        C        B        A                       H         G       F       E        D        C        B        A

          7    6             9   D AT A                                                         DA T A 1 0     9    D AT A                                                         DA T A   10
    IP0                                                  7 4 L S1 6 5                                                                          7 4 L S1 6 5
                                 O UT                                                               IN              O UT                                                               IN

                                         G ND        Vcc                  L O AD            CL K                             G ND          Vc c                 L O AD            CL K
                                 8, 1 5          16          7             1                2                        8, 1 5            16          7             1            2                  etc .
                                                     + 5V        nc                                                                        +5V         nc

          12   11
   O P1
          29   5
   O P0




                                                                                                                                                                                   F9-10




                                                                 TM-112
6821 Interface to the 68000

               (I/O Boards #5 & #6)


          J2
                                                                         6 821
          1                                                 26                          39
                                                                          PIA    CA 2
  D7                                                             D7
          2                                                 27                          40
  D6                                                             D6              CA 1
          3                                                 28
  D5                                                             D5
          4                                                 29                          9
  D4                                                             D4              PA 7
          5                                                 30                          8
  D3                                                             D3              PA 6
          6                                                 31                          7
  D2                                                             D2              PA 5
          7                                                 32                          6
  D1                                                             D1              PA 4
          8                                                 33                          5
  D0                                                             D0              PA 3
                                                                                        4
                                                                                 PA 2

         9                                                  23                          3
                                                                                 PA 1
   SD                                                            CS2
                                                            24                          2
         11                                                                      PA 0
 A16                                                             CS1
                                                            22
                                       1       2     +5 V        CS0




                      7 4 HC 0 0                                                        17
                                           3                                     PB 7
                                   4
                                                                                        16
         18      6                                                               PB 6
 VPA                               5                                                    15
                                                            34                   PB 5
         13
RESET                                                            RESET                  14
                                                            21                   PB 4
         19
 R/ W                                                            R/ W                   13
                                                                                 PB 3
         17                                                 25
    E                                                            E                      12
                                                                                 PB 2
         12                                                 38
 INT 3                                                           IRQA                   11
                                                                                 PB 1
         14                                                 37
   A3           nc                                                                      10
                                                                 IRQB            PB 0
         15                                                 35
   A2                                                            RS1
         16                                                 36                          19
   A1                                                            RS0             CB2
         20                                                                             18
                +5V                                         20                   CB1
                                                     +5 V        V cc
         10
                                                             1
                                                                 GN D




                                                                                             F9-11




                                                   TM-113
Keypad Interface to the 6821

            (I/O Board #5)


   68 21
                  2
    PIA    PA 0
                  3
           PA 1
                  4
           PA 2
                  5
           PA 3

                             J        H         G        F


                                 0          1        2        3

                  6     N
           PA 4

                                 4          5        6        7

                  7     M
           PA 5

                                 8          9        A        B
                  8      L
           PA 6

                                 C          D        E        F
                  9     K
           PA 7

                                     Gra yh ill PN 8 8 BA 2

                                                                  F9-12




                      TM-114
    Output to a MC1408L8 DAC

                   (I/O Board #6, 1 of 4)


68 21                               M C1 4 0 8 L 8
                                                                          +5V
               9              5                                    1 kΩ
        PA 7                      D7                                              1 50 Ω
                                                             14
               8              6                   V r ef +
        PA 6                      D6
               7              7                                                   10 0 Ω
        PA 5                      D5
                                                                   1 kΩ
               6              8                              15
        PA 4                      D4              V r ef -
               5              9
        PA 3                      D3
               4             10                              1
        PA 2                      D2                              nc          4 .7 k Ω
               3             11
        PA 1                      D1
               2             12                                            + 1 2 V -1 2 V
        PA 0                      D0
                                                                              7
                                                             4                     4
                                                                          2
                             13                        IO                                   6
                     +5 V         V CC
                                                                                                       VO
                                                                          3
                             16
                                  COMP                                             8        L M3 0 1
                                                                              1
                              2
                    1 5 pF        GND
                                          V EE
                                          3                                   3 3 pF

                                         -1 2 V

                                                                                                       F9-13




                                           TM-115
     Low-Pass Filter and Audio Output

                           (I/O Board #6, 2 of 4)


                            0 .0 4 4 µ F
                                                          VO
                                                      ( f ilt er ed )
                                     2 .4 k Ω
                                                                                                                  A ux ilia r y
                                                                                                                    Jack
                                 +12V -12V                                     + 1 2 V -1 2 V

                                      7                                            7

                                 2         4
                                                                               2
                                                                                       4
                                                                                                                                  2 5 µF
     1 .2 k Ω    1 .2 k Ω
                                                6                                               6

VO
                                 3                                             3                                                  +
                                           8       L M3 0 1                            8          LM 3 0 1
                                                                        5 kΩ                                                                  Sp ea k e r
            0 .0 2 2 µ F              1         ( lo w - pa ss                     1
                                                                                                ( vo lt ag e
                                                    f ilt e r )                                 f o llo w e r )

                                       33 pF                                       3 3 pF



                                                                                                                                           F9-15




                                                               TM-116
            Interface to ADC0804
          Analog-to-Digital Converter

               (I/O Board #6, 3 of 4)


                              AD C0 8 0 4
682 1                                             20
                                        V cc                                          +5V

          19        3
   C B2                  WR                       6
                                                                                             10 k Ω
                                     Vin ( + )                                             t r im p o t
          18        5                                  Di f f e re nt ial In p ut s
   C B1                  IN TR        V in( - )                                       ( t r an sd uc er)
                                                  7
                    1
                         CS
                    2
                         RD
                                                  9
                                        Vr ef                nc
          17        11                            19
    PB7                  D7          C LK R
          16        12
    PB6                  D6
          15        13                                             1 5 kΩ
    PB5                  D5
          14        14                            4
    PB4                  D4          CL K IN
          13        15
    PB3                  D3
          12        16                                          1 5 0 pF
    PB2                  D2
          11        17                            10
    PB1                  D1          D GN D
          10        18                            8
    PB0                  D0          A GN D




                                                                                            F9-16




                                 TM-117
     Timing for ADC0804 Conversions


         Clea r    St a r t o f                      En d o f      C le ar   St ar t Ne xt
         INT R    Co n ve rsio n                   Co nv er sion   IN TR     Co nv er sio n




 WR

                                   ≈ 1 0 0 µs

IN T R




                                                                                 F9-17




                                                TM-118
      Microphone Input to the ADC0804

                                    (I/O Board #6, 4 of 4)
                      1 kΩ                      100 k Ω                             VA                                                                     VB
                       1%                         1%                                                           1 kΩ                   1 0 kΩ

                                                                                                          +
                                             + 1 2 V -1 2 V
                                                                                                1 0 µF                            + 1 2 V -1 2 V

                                                 7                    47 Ω                                                             7                    47 Ω
                      1 kΩ                  2         4                                                                           2           4
                                                              6                                                                                        6
Mic rop h o ne
                       1%                                                                                     2 2 kΩ
                                            3                                                                                     3
   200 Ω                                                      LM 3 0 1                              +5V                                                LM 3 0 1
                                                      8                                                                                       8
                                                              ( p r e -am p )                                                                          (a m p )
                      1 0 0 kΩ
                                                1                                                                                     1
                                                                                                                 2 2 kΩ
                         1%
                                                 33 pF                                                                                 33 pF

                                                                                                              +5 V


                                                                                                1N914
       1 .2 k Ω


                  0 .0 4 4 µF
                                                                                L F3 9 8
                                                                                                                                                   A DC0 8 0 4
                                                                        ( sa m p le an d h o ld )
                           2 .4 k Ω
                                                                            +12V            -1 2 V
       1 .2 k Ω
                       + 1 2 V -1 2 V                                                                   18 k Ω     5 . 6 kΩ                                              20
                                                                                                                                                                  V cc        +5 V
                                                              V                     1
                            7                                     C                         4
                       2        4
                                                                                                    8
                                        6                                       3
                                                                                                          5
                                                                                                                              V
                       3                                                                                                          D
                                        L M3 0 1
       0 .0 2 2 µ F             8                                                               6
                           1            ( lo w -p a ss f ilt e r )                      7
                                                                                                        0 .0 0 1 µ F
                                                                                                                                          6
                                                                                                                                                                         1
                                                                                                                                              V in (+ )             CS
                                                                                                                                          7                              2
                            33 pF                                                                                                             V in (- )             RD



                                                    6 821
                                                                       19                                                             3
                                                              CB2                                                                             WR
                                                                       18                                                             5                                  9
                                                              CB1                                                                             IN T R          V re f          nc
                                                                                                                                                                         19
                                                                       17
                                                                                                                                                            CL K R
                                                                                                                                      11
                                                              PB7                                                                                 D7
                                                                       16                                                             12                                           15 k Ω
                                                              PB6                                                                                 D6
                                                                       15                                                             13                                 4
                                                              PB5                                                                                 D5       CL K IN
                                                                       14                                                             14
                                                              PB4                                                                                 D4
                                                                       13                                                             15                                       1 50 pF
                                                              PB3                                                                                 D3
                                                                       12                                                             16                                 10
                                                              PB2                                                                                 D2       D GND
                                                                       11                                                             17                                 8
                                                              PB1                                                                                 D1       A GND
                                                                       10                                                             18
                                                              PB0                                                                                 D0




                                                                                    TM-119
         F9-19




TM-120
              Sample-and-Hold Waveforms


                                                           1 0 0 µ s m in im un
                  Sign a l a t V C


                              Sig n al at V D




V o lt a ge




                                                  T im e



                                                                                  F9-20




                                                TM-121
                      68000-Family Features

                      48-pin   52-pin
                      68008    68008    68000    68010   68020   68030     68040

    Data Bus (bits)     8        8        16      16      32      32         32

Address Bus (bits)     20       22        24      24      32      32         32

Data Cache (bytes)      –        –        –       –       –      256        4096

 Instruction Cache      –        –        –       –      256     256        4096
            (bytes)

  On-Chip Memory       No       No       No       No      No     Yes        Yes
     Management

 On-Chip Floating-     No       No       No       No      No      No        Yes
        Point Unit


                                                                         T10-1




                                        TM-122
          Comparison of Five Recent
             Microprocessors                                †




                                                                        Alpha
                     68040     80486         PowerPC       Pentium      21064

        Company Motorola        Intel       IBM/Motorola    Intel        DEC

       Introduced    1989       6/91              4/93      3/93         2/92

     Architecture    CISC      CISC               RISC      CISC        RISC

      Width (bits)    32         32                32           32        64

        Registers    16/8       8/8              32/32          8/8     32/32
     (general/FP)

  Multiprocessing     No         No               Yes           Yes      Yes
         Support?

Device Size (mm)     10.8 x     not              11 x 11    17.2 x    15.3 x 12.7
                      11.7    available                      17.2

      Transistors     1.2       1.2                2.8          3.1      1.68
        (millions)

     Clock (MHz)      25         50                80           66       200

   SPECint 92††       21        27.9               85       67.4         130

    SPECfp 92††       15        13.1              105       63.6         184

     Peak Power        6         5                 9.1          16        30
         (Watts)

 Price ($US/1000     $233      $432               $557      $898         $505
           units)

† Source: IEEE Spectrum, December 1993, p. 21
†† Integer and floating-point performance benchmarks

                                                                           T10-10




                                        TM-123