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# CS1104 Computer Organisation

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```									   CS1104: Computer Organisation

http://www.comp.nus.edu.sg/~cs1104

Lecture 4: Logic Gates and Circuits
Lecture 4:
Logic Gates and Circuits
 Logic Gates
   The Inverter
   The AND Gate
   The OR Gate
   The NAND Gate
   The NOR Gate
   The XOR Gate
   The XNOR Gate
 Drawing Logic Circuit
 Analysing Logic Circuit
 Propagation Delay

CS1104-4               Lecture 4: Introduction to Logic   2
Gates
Lecture 4:
Logic Gates and Circuits
 Universal Gates: NAND and NOR
 NAND Gate
 NOR Gate

   Implementation using NAND Gates
   Implementation using NOR Gates
   Implementation of SOP Expressions
   Implementation of POS Expressions
   Positive and Negative Logic
   Integrated Circuit Logic Families

CS1104-4                 Lecture 4: Introduction to Logic   3
Gates
Logic Gates
 Gate Symbols             Symbol set 1                    Symbol set 2
(ANSI/IEEE Standard 91-1984)
a                               a
AND                        a.b                    &        a.b
b                               b

a                               a
OR                        a+b                  1         a+b
b                               b

NOT     a                  a'           a        1         a'

a                               a
(a.b)'                &         (a.b)'
NAND      b                               b

a                               a
NOR                         (a+b)'               1         (a+b)'
b                               b

a                               a
ab                  =1         ab
EXCLUSIVE OR b                               b

CS1104-4                          Logic Gates                                       4
Logic Gates: The Inverter
 The Inverter
A A'
A               A'       A                  A'   0   1
1   0
 Application of the inverter: complement.
Binary number
1   1   0        1   0       0      0   1

0   0   1        0   1       1      1   0
1’s Complement

CS1104-4                 Logic Gates: The Inverter                    5
Logic Gates: The AND Gate (1/2)
 The AND Gate
A                          A       &
A.B                    A.B
B                          B

A    B      A.B
0    0       0
0    1       0
1    0       0
1    1       1

CS1104-4          Logic Gates: The AND Gate             6
Logic Gates: The AND Gate (2/2)
 Application of the AND Gate
1 sec

A               A
Counter
Enable
Enable
1 sec
Register,
Reset to zero                      decode
between                            and
frequency
Enable pulses
display

CS1104-4               Logic Gates: The AND Gate                         7
Logic Gates: The OR Gate
 The OR Gate
A                      A         1
A+B                        A+B
B                      B

A    B      A+B
0    0       0
0    1       1
1    0       1
1    1       1

CS1104-4           Logic Gates: The OR Gate              8
Logic Gates: The NAND Gate
 The NAND Gate
A
(A.B)'      A
(A.B)'
A      &
(A.B)'
B                         B                           B

A   B   (A.B)'
0   0     1
0   1     1

1   0     1
1   1     0                      NAND                Negative-OR

CS1104-4                    Logic Gates: The NAND Gate                             9
Logic Gates: The NOR Gate
 The NOR Gate
A
(A+B)'      A
(A+B)'
A       1
(A+B)'
B                        B                           B

A   B   (A+B)'
0   0     1
0   1     0

1   0     0
1   1     0                       NOR                Negative-AND

CS1104-4                    Logic Gates: The NOR Gate                            10
Logic Gates: The XOR Gate
 The XOR Gate
A                           A          =1
AB                         AB
B                           B

A    B     AB
0    0      0
0    1      1
1    0      1
1    1      0

CS1104-4              Logic Gates: The XOR Gate              11
Logic Gates: The XNOR Gate
 The XNOR Gate
A                         A         =1
(A  B)'                   (A  B)'
B                         B

A   B (A  B) '
0   0    1
0   1    0
1   0    0
1   1    1

CS1104-4          Logic Gates: The XNOR Gate                   12
Drawing Logic Circuit (1/2)
 When a Boolean expression is provided, we can
easily draw the logic circuit.
 Examples:
(i) F1 = x.y.z' (note the use of a 3-input AND gate)

x
y                               F1

z               z'

CS1104-4                 Drawing Logic Circuit              13
Drawing Logic Circuit (2/2)
(ii) F2 = x + y'.z (if we assume that variables and their
complements are available)
x
F2
y'
z                  y'.z

(iii) F3 = x.y' + x'.z
x                   x.y'
y'
F3
x'
z                   x'.z

CS1104-4                   Drawing Logic Circuit                    14
Quick Review Questions (1)
Textbook page 77.
Questions 4-1, 4-2.

CS1104-4            Quick Review Questions (1)   15
Analysing Logic Circuit
 When a logic circuit is provided, we can analyse the
circuit to obtain the logic expression.
 Example: What is the Boolean expression of F4?

A'           A'.B'
B'                           A'.B'+C      (A'.B'+C)'
F4
C

F4 = (A'.B'+C)' = (A+B).C'

CS1104-4                   Analysing Logic Circuit                     16
Propagation Delay (1/3)
 Every logic gate experiences some delay (though
very small) in propagating signals forward.
 This delay is called Gate (Propagation) Delay.
 Formally, it is the average transition time taken for
the output signal of the gate to change in response to
changes in the input signals.
 Three different propagation delay times associated
with a logic gate:
 tPHL: output changing from the High level to Low level
 tPLH: output changing from the Low level to High level
 tPD=(tPLH + tPHL)/2   (average propagation delay)

CS1104-4                      Propagation Delay                 17
Propagation Delay (2/3)

Input                      Output

H
Input
L

H
Output
L

tPHL      tPLH

CS1104-4                    Propagation Delay       18
Propagation Delay (3/3)
A                  B               C

 Ideally, no                              In reality, output signals
delay:                                     normally lag behind
input signals:
1                                      1
Signal for A                            Signal for A
0                                      0

1                                      1
0       Signal for B                   0        Signal for B

1                                      1
Signal for C                             Signal for C
0                                      0
time                                   time
CS1104-4                          Propagation Delay                         19
Calculation of Circuit Delays (1/3)
 Amount of propagation delay per gate depends on:
 (i) gate type (AND, OR, NOT, etc)
 (ii) transistor technology used (TTL,ECL,CMOS etc),
 (iii) miniaturisation (SSI, MSI, LSI, VLSI)

 To simplify matters, one can assume
 (i) an average delay time per gate, or
 (ii) an average delay time per gate-type.

 Propagation delay of logic circuit
= longest time it takes for the input signal(s) to propagate to the
output(s).
= earliest time for output signal(s) to stabilise, given that input
signals are stable at time 0.

CS1104-4                   Calculation of Circuit Delays                    20
Calculation of Circuit Delays (2/3)
 In general, given a logic gate with delay, t.
t1
t2               Logic
:    :          Gate
tn                                   max (t1, t2, ..., tn ) + t

If inputs are stable at times t1,t2,..,tn, respectively; then the
earliest time in which the output will be stable is:
max(t1, t2, .., tn) + t

 To calculate the delays of all outputs of a
combinational circuit, repeat above rule for all gates.

CS1104-4                    Calculation of Circuit Delays                      21
Calculation of Circuit Delays (3/3)
 As a simple example, consider the full adder circuit
where all inputs are available at time 0. (Assume
each gate has delay t.)

X 0               max(0,0)+t = t
max(t,0)+t = 2t
Y 0                                                              S

t                        2t          max(t,2t)+t = 3t
C
0
Z

where outputs S and C, experience delays
of 2t and 3t, respectively.

CS1104-4                      Calculation of Circuit Delays                            22
Quick Review Questions (2)
Textbook page 77.
Questions 4-3 to 4-5.

CS1104-4            Quick Review Questions (2)   23
Universal Gates: NAND and NOR
 AND/OR/NOT gates are sufficient for building any
Boolean functions.
   We call the set {AND, OR, NOT} a complete set of
logic.
 However, other gates are also used because:
(i) usefulness
(ii) economical on transistors
(iii) self-sufficient

NAND/NOR: economical, self-sufficient
XOR: useful (e.g. parity bit generation)

CS1104-4               Universal Gates: NAND and NOR   24
NAND Gate (1/2)
 NAND gate is self-sufficient (can build any logic
circuit with it).
   Therefore, {NAND} is also a complete set of logic.
 Can be used to implement AND/OR/NOT.
 Implementing an inverter using NAND gate:
x                   x'

(x.x)' = x'   (T1: idempotency)

CS1104-4                      NAND Gate                  25
NAND Gate (2/2)
 Implementing AND using NAND gates:
(x.y)'
x
x.y
y
((x.y)'(x.y)')' = ((x.y)')' idempotency
= (xy)     involution

 Implementing OR using NAND gates:
x'
x
((x.x)'(y.y)')' = (x'.y')' idempotency
x+y                      = x''+y'' DeMorgan
= x+y      involution
y
y'

CS1104-4              NAND Gate                                        26
NOR Gate (1/2)
   NOR gate is also self-sufficient.
   Therefore, {NOR} is also a complete set of logic
   Can be used to implement AND/OR/NOT.
   Implementing an inverter using NOR gate:

x                    x'

(x+x)' = x'   (T1: idempotency)

CS1104-4                       NOR Gate                27
NOR Gate (2/2)
 Implementing AND using NOR gates:
x'
x
x.y
((x+x)'+(y+y)')'=(x'+y')'   idempotency
y
y'                          = x''.y''   DeMorgan
= x.y       involution
 Implementing OR using NOR gates:
(x+y)'
x
x+y
y
((x+y)'+(x+y)')' = ((x+y)')' idempotency
= (x+y)     involution

CS1104-4               NOR Gate                                       28
Implementation using NAND gates (1/2)
 Possible to implement any Boolean expression using
NAND gates.
Procedure:
(i) Obtain sum-of-products Boolean expression:
e.g. F3 = x.y'+x'.z
(ii) Use DeMorgan theorem to obtain expression
using 2-level NAND gates
e.g. F3 = x.y'+x'.z
= (x.y'+x'.z)' '       involution
= ((x.y')' . (x'.z)')' DeMorgan

CS1104-4             Implementation using NAND           29
gates
Implementation using NAND gates (2/2)

x                   (x.y')'
y'
F3
x'
z                   (x'.z)'

F3 = ((x.y')'.(x'.z)') ' = x.y' + x'.z

CS1104-4            Implementation using NAND            30
gates
Implementation using NOR gates (1/2)
 Possible to implement any Boolean expression using
NOR gates.
Procedure:
(i) Obtain product-of-sums Boolean expression:
e.g. F6 = (x+y').(x'+z)
(ii) Use DeMorgan theorem to obtain expression
using 2-level NOR gates.
e.g. F6 = (x+y').(x'+z)
= ((x+y').(x'+z))' ' involution
= ((x+y')'+(x'+z)')' DeMorgan

CS1104-4             Implementation using NOR gates     31
Implementation using NOR gates (2/2)

x                    (x+y')'
y'
F6
x'
z                    (x'+z)'

F6 = ((x+y')'+(x'+z)')' = (x+y').(x'+z)

CS1104-4           Implementation using NOR gates        32
Implementation of SOP Expressions
(1/2)
 Sum-of-Products expressions can be implemented
using:
 2-level AND-OR logic circuits
 2-level NAND logic circuits

 AND-OR logic circuit
A
B                                F = A.B + C.D + E
C
F
D

E

CS1104-4                   Implementation of SOP                       33
Expressions
Implementation of SOP Expressions
(2/2)
 NAND-NAND circuit (by                     A
B
circuit transformation)
C
D
b) change OR-with-                       E
inverted-inputs to NAND
& bubbles at inputs to
their complements                     A
B
C
F
D

E'

CS1104-4                 Implementation of SOP   34
Expressions
Implementation of POS Expressions
(1/2)
 Product-of-Sums expressions can be implemented
using:
 2-level OR-AND logic circuits
 2-level NOR logic circuits

 OR-AND logic circuit
A
B                                   G = (A+B).(C+D).E
C
G
D

E

CS1104-4                    Implementation of POS                       35
Expressions
Implementation of POS Expressions
(2/2)
 NOR-NOR circuit (by                     A
circuit transformation):              B
C
G
b) changed AND-with-
E
inverted-inputs to NOR
& bubbles at inputs to
their complements                   A
B
C
G
D

E'

CS1104-4                 Implementation of POS   36
Expressions
Quick Review Questions (3)
Textbook page 77.
Questions 4-6 to 4-8.

CS1104-4            Quick Review Questions (3)   37
Positive & Negative Logic (1/3)
 In logic gates, usually:
 H (high voltage, 5V) = 1
 L (low voltage, 0V) = 0

 This convention is known as positive logic.
 However, the reverse convention, negative logic
possible:
 H (high voltage) = 0
 L (low voltage) = 1

 Depending on convention, same gate may denote
different Boolean function.

CS1104-4                  Positive & Negative Logic   38
Positive & Negative Logic (2/3)
 A signal that is set to logic 1 is said to be asserted, or
active, or true.
 A signal that is set to logic 0 is said to be deasserted,
or negated, or false.
 Active-high signal names are usually written in
uncomplemented form.
 Active-low signal names are usually written in
complemented form.

CS1104-4                Positive & Negative Logic              39
Positive & Negative Logic (3/3)
Positive logic:

Active High:
Enable                                0: Disabled
1: Enabled

Negative logic:
Active Low:
Enable                                0: Enabled
1: Disabled

CS1104-4                      Positive & Negative Logic                  40
Integrated Circuit Logic Families
(1/2)
 Some digital integrated circuit families: TTL, CMOS, ECL.
 TTL: Transistor-Transistor Logic.
 Uses bipolar junction transistors
 Consists of a series of logic circuits: standard TTL, low-power
TTL, Schottky TTL, low-power Schottky TTL, advanced Schottky
TTL, etc.
TTL Series       Prefix Designation Example of Device

Standard TTL     54 or 74                  7400 (quad NAND gates)

Low-power TTL    54L or 74L                74L00 (quad NAND gates)

Schottky TTL     54S or 74S                74S00 (quad NAND gates)

Low-power        54LS or 74LS              74LS00 (quad NAND gates)
Schottky TTL

CS1104-4                Integrated Circuit Logic Families                41
Integrated Circuit Logic Families
(2/2)
 CMOS: Complementary Metal-Oxide Semiconductor.
 Uses field-effect transistors

 ECL: Emitter Coupled Logic.
 Uses bipolar circuit technology.
 Has fastest switching speed but high power consumption.

 Performance characteristics
 Propagation delay time.
 Power dissipation.
 Fan-out: Fan-out of a gate is the maximum number of inputs
that the gate can drive.
 Speed-power product (SPP): product of the propagation
delay time and the power dissipation.

CS1104-4                 Integrated Circuit Logic Families           42
Summary
Logic Gates     Drawing Logic            Analysing
Circuit              Logic Circuit

AND,           NAND   Given a Boolean        Given a circuit, find
OR,                   expression, draw the   the function.
NOT         NOR       circuit.

Implementation          Positive and
Implementation of a     of SOP and POS         Negative Logic
Boolean expression      Expressions
using these
Universal gates.         Concept of Minterm
and Maxterm
CS1104-4                      Summary                                    43
End of file

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