Docstoc

OS

Document Sample
OS Powered By Docstoc
					                                  CMP320
                             Operating Systems
                              Lecture 01, 02

Introduction to Computer & Operating Systems
                                         Fall 2012
                                         Arif Butt
 Note: Some slides and/or pictures are adapted from Lecture slides / Books of
 •    Dr Mansoor Sarwar.
 •    Dr Kubiatowicz.
 •    Dr P. Bhat.
 •    Dr Hank Levy.
 •    Dr Indranil Gupta.
 •    Text Book - OS Concepts by Silberschatz, Galvin, and Gagne.
 •    Ref Books
        •  Operating Systems Design and Implementation by Tanenbaum.
        •  Operating Systems by William Stalling.
        •  Operating Systems by Colin Ritchie.
                  Today’s	
  Agenda	
  
•  Basic Course information and Class Protocols
•  Course Outline
•  Computer System Overview
  –  Processor Registers
  –  Instruction Execution
  –  Memory Hierarchy & Cache Memory
  –  Interrupts
  –  I/O Communication Mechanism
  –  I/O, Memory and CPU Protection

•  Operating System Overview
  –  A Brief History / Evolution of OSs
  1/10/2012	
                CMP320	
  	
  	
  PUCIT	
  	
  	
  Arif	
  Bu3	
     2	
  
                      Course	
  Informa3on	
  
•  Required Textbook: Opera8ng	
  System	
  Concepts,	
  	
  
       	
  	
  8th	
  Edi8on	
  Silbershatz,	
  Galvin,	
  Gagne	
  
•  Lectures Website: http://online.pucit.edu.pk
•  Grades Website:                      http://online.pucit.edu.pk
•  Resources Website: \\printsrv\Teacher Data\Arif Butt\OS

•    Prerequisites : Nill
•    Corequisites : CMP223, CMP210
•    Office: Senior Faculty Room # 2
•    Students Counseling hours:
       –     Mon:   1400 hrs – 1500 hrs
       –     Tue:   0845 hrs – 0945 hrs
       –     Wed:    1400 hrs – 1500 hrs
       –     Thu:   0845 hrs – 0945 hrs
•  24 hour turnaround for email: arif@pucit.edu.pk

     5/1/2012	
                     CMP320	
  	
  	
  PUCIT	
  	
  	
  Arif	
  Bu3	
     3	
  
                 Course	
  Informa3on	
  
•  Teaching Assistants BSCS Morning:
   –  Tahir Fazal:      bcsf09a49@pucit.edu.pk
   –  Samina / Sheeza: bcsf09a@pucit.edu.pk
   –  Lab C1 Timings: 8:15 to 12:45

•  Teaching Assistants BSCS Afternoon:
   –  Mohsin Saleem: bcsf09a010@pucit.edu.pk
   –  Usman Arshad: bcsf09a050@pucit.edu.pk
   –  Lab C1 Timings: 2:30 to 5:30

•  Teaching Assistants BSSE Morning:
   –  Amjad Afzal: bcsf09m001@pucit.edu.pk
   –  Asma Sardar: bcsf09m039@pucit.edu.pk
   –  Lab C2 Timings: 8:15 to 12:45
  5/1/2012	
               CMP320	
  	
  	
  PUCIT	
  	
  	
  Arif	
  Bu3	
     4	
  
                   Lecture Format
•  Please come to class (in time).
•  I will mark the attendance in the first five minutes. Students
   with more than eight absents will not be allowed to sit in the
   class and their names will be struck off the register. (Be
   watch full)
•  To Help you understand important and hard OS concepts
   please read the relevant textbook sections before lecture
•  Exam, quiz, PA and HW questions could be from anywhere in
   the lecture slides, textbook sections covered, reading
   material provided. Your best strategy is to play it safe –
   read all material referred to in lecture
•  Make sure you also
    –  Periodically check lecture notes web page
    –  Utilize the student counseling hours


                                                                                5	
  
   5/1/2012	
              CMP320	
  	
  	
  PUCIT	
  	
  	
  Arif	
  Bu3	
  
                     Lab Format
•  Please come to Labs (in time).
•  5% of your grade is from LAB participation (ATTENDANCE).
   Students having full attendance will get full 5% marks.
•  To Help you understand important and hard OS concepts
   please read the relevant Chapters of UNIX The Textbook by
   Dr Mansoor Sarwar
•  Quizzes might be taken in class or in Lab, so don’t miss and
   don’t come late in the Labs
•  Contents covered in the Lab will come in the Quizzes as well
   as in the Mid and Final exams.




                                                                              6	
  
   5/1/2012	
            CMP320	
  	
  	
  PUCIT	
  	
  	
  Arif	
  Bu3	
  
                 Who	
  cares	
  to	
  get	
  an	
  A?	
  
•  Final exam: 40%

•  Mid-exam: 35%

•  Sessionals: 25%
   –  Surprise Quizzes: 12%

   –  Assignments (PA/LW/HW): 8%

   –  Lab Participation: 5%


  5/1/2012	
                   CMP320	
  	
  	
  PUCIT	
  	
  	
  Arif	
  Bu3	
     7	
  
                Surprise Quizzes
•  There will be surprise quizzes, given at the start
   of a lecture, during any lecture. The total
   number of quizzes could be anywhere between 4
   and 40.
•  NO LATE or MAKEUP SURPRISE QUIZZES,
   under any circumstances whatsoever
•  Surprise quizzes are completely individual
   efforts.
•  Your best strategy is to play it safe – attend
   every lecture and do the reading/programming
   assignments
 5/1/2012	
          CMP320	
  	
  	
  PUCIT	
  	
  	
  Arif	
  Bu3	
     8	
  
          Cheating Policy
•         Academic integrity

•         Both the cheater and the student who aided the
          cheater will be held responsible for the cheating

•         The instructor may take actions such as:

     –      require repetition of the subject work,

     –      assign 'zero' or may be ‘negative’ marks for the
            subject work,

     –      for serious offenses, assign an F grade for the
            course
                               CMP320	
  	
  	
  PUCIT	
  	
  	
  Arif	
  Bu3	
     9	
  
     Late Policy for HWs and PAs
•  Grade book system details can be checked on :
  http://online.pucit.edu.pk
•  Late policy for Assignment, Quizzes, and other
  deliverables
   –  No late Assignment submissions!
   –  No late quizzes or exams!
•  Sticking to dates is your responsibility!
   –  Check announcements on lecture notes regularly
•  Your best strategy is to play it safe – submit everything
  on time
                         CMP320	
  	
  	
  PUCIT	
  	
  	
  Arif	
  Bu3	
     10	
  
       Playing it Safe in CMP320
If you follow these 4 simple rules during the CMP320
   class, you'll make sure that you do well in the
   course:
1.  Attend every lecture + Lab
2.  Read the course material (textbook sections
   assigned + slides + Reading assignments)
3.  Submit everything (PAs, HWs, quizzes, exams) on
   time - don't be late
4.  Don't cheat

                       CMP320	
  	
  	
  PUCIT	
  	
  	
  Arif	
  Bu3	
     11	
  
Programming Assignments
                        &
 Linux Shell Commands


         CMP320	
  	
  	
  PUCIT	
  	
  	
  Arif	
  Bu3	
     12	
  
No Pains
No Gains




       CMP320	
  	
  	
  PUCIT	
  	
  	
  Arif	
  Bu3	
     13	
  
Outline



 CMP320	
  	
  	
  PUCIT	
  	
  	
  Arif	
  Bu3	
     14	
  
              Computer System

•  Hardware(Processor, Main Memory, I/O Modules, System Bus)

•  Operating System

•  Application Programs

•  Users


                        CMP320	
  	
  	
  PUCIT	
  	
  	
  Arif	
  Bu3	
     15	
  
Layered View of Computer System




            CMP320	
  	
  	
  PUCIT	
  	
  	
  Arif	
  Bu3	
     16	
  
 Purpose of a Computer System
Computer systems consist
of software and hardware
that are combined to
provide a tool to solve
specific problems in an
efficient manner. Used to
execute programs.


              CMP320	
  	
  	
  PUCIT	
  	
  	
  Arif	
  Bu3	
     17	
  
 Computer System Organization
•  Computer-system operation
  –  One or more CPUs, device controllers connect
     through common bus providing access to shared
     memory
  –  Concurrent execution of CPUs and devices
     competing for memory cycles




                    CMP320	
  	
  	
  PUCIT	
  	
  	
  Arif	
  Bu3	
     18	
  
Some Computer Architecture Topics
        Input/Output	
  and	
  Storage	
  

                                              Disks,	
  WORM,	
  Tape	
                                                                       RAID	
  

                                                                                                                   Emerging	
  Technologies	
  
                                               DRAM	
                                                              Interleaving	
  
                                                                                                                   Bus	
  protocols	
  

                                                                                                              Coherence,	
  
 Memory	
                                 L2	
  Cache	
                                                       Bandwidth,	
  
 Hierarchy	
                                                                                                  Latency	
  




                                                                                                                                                         Other	
  Processors	
  
                                                                                                                                 Network	
  
                                                                                                                               Communica8on	
  
                                       L1	
  Cache	
                                        Addressing,	
  
           VLSI	
                                                                           Protec8on,	
  
                      Instruc8on	
  Set	
  Architecture	
  
                                                                                            Excep8on	
  Handling	
  

                      Pipelining,	
  Hazard	
  Resolu8on,	
                                                   Pipelining	
  and	
  Instruc8on	
  	
  
                      Superscalar,	
  Reordering,	
  	
                                                       Level	
  Parallelism	
  
                      Predic8on,	
  Specula8on,	
  
                      Vector,	
  Dynamic	
  Compila8on	
  

                                                         CMP320	
  	
  	
  PUCIT	
  	
  	
  Arif	
  Bu3	
                                                    19	
  
  Computer System Hardware

Integer   Control   Keyboard                          Mouse
  Unit     Unit
                                                                                        CD
 Floating Point
      Unit
     Cache

  Processor
                        System Bus
                                                                                        HD
      Mem
      Bus



   RAM/ROM           Printer                                                  Monitor
                         CMP320	
  	
  	
  PUCIT	
  	
  	
  Arif	
  Bu3	
                    20	
  
Computer System Hardware




         CMP320	
  	
  	
  PUCIT	
  	
  	
  Arif	
  Bu3	
     21	
  
          Processor Registers
•  Faster and smaller than main memory
•  User-visible registers
  –  Enable programmer to minimize main memory
     references by optimizing register use
•  Control and status registers
  –  Used by processor to control operating of the
     processor
  –  Used by privileged OS routines to control the
     execution of programs


                     CMP320	
  	
  	
  PUCIT	
  	
  	
  Arif	
  Bu3	
     22	
  
           Processor Registers (…)
•  User Visible Registers
   –  May be referenced by machine / assembly language
   –  Types of registers typically available are data, address, and condition code
      registers
•  Data Registers
   –  Often general purpose, But some restrictions may apply
•  Address Registers
   –  Examples are: Index Register, Segment pointer, Stack pointer
•  Control and Status Registers
   –  Program counter (PC), contains the address of next instruction to be fetched
   –  Instruction register (IR), contains the instruction most recently fetched
   –  Program status word (PSW), contains status information
•  Condition Codes
   –  Usually part of the control registers, also called flags (zero, parity, overflow)
   –  Bits set by processor hardware as a result of operations
   –  Read only, intended for feedback regarding the results of instruction
      execution
                                   CMP320	
  	
  	
  PUCIT	
  	
  	
  Arif	
  Bu3	
     23	
  
         Instruction Execution
                                                                 Addr 232-1
                  R0
                  …                                                          …
                 R31
                          Fetch                                            Data1
                  F0
                  …        Exec                                            Data0
                 F30                                                      Inst237
                  PC                                                      Inst236
                                                                             …
                                                                           Inst5
•  Execution sequence:
    –  Fetch Instruction at PC                                             Inst4
    –  Keep it in IR and Decode                                            Inst3    PC
    –  Execute (possibly using                                             Inst2    PC
       registers)                                                          Inst1    PC
    –  Write results to registers/mem Inst0                                         PC
    –  PC = Next Instruction(PC)                                          Addr 0
    –  Repeat          CMP320	
  	
  	
  PUCIT	
  	
  	
  Arif	
  Bu3	
              24	
  
Instruction Execution (…)




         CMP320	
  	
  	
  PUCIT	
  	
  	
  Arif	
  Bu3	
     25	
  
The program fragment shown adds the contents of the
memory word at address 940 to the contents of the memory
word at address 941 and stores the result in the later
location.
   5/1/2012	
            CMP320	
  	
  	
  PUCIT	
  	
  	
  Arif	
  Bu3	
   26	
  
         Memory Hierarchy
•  Major constraints in memory
  – Amount
  – Speed
  – Expense
•  Faster access time, greater cost per bit
•  Greater capacity, smaller cost per bit
•  Greater capacity, slower access speed


                 CMP320	
  	
  	
  PUCIT	
  	
  	
  Arif	
  Bu3	
     27	
  
       Memory Hierarchy (…)
•  Going down the hierarchy
  –  Decreasing cost per bit
  –  Increasing capacity
  –  Increasing access time
  –  Decreasing frequency of
     access to the memory by
     the processor




                    CMP320	
  	
  	
  PUCIT	
  	
  	
  Arif	
  Bu3	
     28	
  
               Cache Memory
•  Invisible to the OS
  –  Interacts with other memory management hardware
•  Processor must access memory at least once
   per instruction cycle
  –  Processor speed faster than memory access speed
•  Exploit the principle of locality (Temporal and
   Spatial)
  –  Temporal Locality. If data is referenced at time t,
     then it might get referenced at time t+1
  –  Spatial Locality. Data which is required soon is
     often close to the current data
                      CMP320	
  	
  	
  PUCIT	
  	
  	
  Arif	
  Bu3	
     29	
  
         Cache and Main Memory




•  Caches Contains copy of a portion of main memory
•  Processor first checks cache
    –  If not found, block of memory read into cache
•  Because of locality of reference, likely future memory references are
   in that block


                              CMP320	
  	
  	
  PUCIT	
  	
  	
  Arif	
  Bu3	
     30	
  
Cache/Main-Memory Structure




          CMP320	
  	
  	
  PUCIT	
  	
  	
  Arif	
  Bu3	
     31	
  
                Cache Design Issues
•  Cache size. Small caches have significant impact on performance
•  Block size. The unit of data exchanged between cache and main
   memory. Larger block size means more hits. But too large reduces
   chance of reuse
•  Mapping function. Determines which cache location the block will
   occupy. Has two constraints:
     –  When one block read in, another may need replaced
     –  Complexity of mapping function increases circuitry costs for searching
•   Replacement algorithm. Chooses which block to replace when a new
   block is to be loaded into the cache. Ideally replacing a block that isn’t
   likely to be needed again is impossible to guarantee. Effective strategy
   is to replace a block that has been used less than others, e.g., LRU
•  Write policy. Dictates when the memory write operation takes place
     –  Write Through. Can occur every time the block is updated (maximize
        write operations)
     –  Write Back. Can occur when the block is replaced (leave main
        memory and cache in an inconsistent state)
                                   CMP320	
  	
  	
  PUCIT	
  	
  	
  Arif	
  Bu3	
     32	
  
                    Interrupt
•  Virtually all computers provide a
  mechanism by which other modules (I/O,
  memory) may interrupt the normal
  sequencing of the processor.
                                                                           Answer
•  Provided to improve processor utilization
                                                                             The
                                                                            Phone
•  Most I/O devices are slower than the                                        .
                                                                              .

  processor and Processor must pause to                                       .
                                                                              .
                                                                              .
  wait for device                                                             .

                                                                           Resume
                      CMP320	
  	
  	
  PUCIT	
  	
  	
  Arif	
  Bu3	
        33	
  
Common Classes of Interrupts




           CMP320	
  	
  	
  PUCIT	
  	
  	
  Arif	
  Bu3	
     34	
  
Transfer of Control via Interrupts




             CMP320	
  	
  	
  PUCIT	
  	
  	
  Arif	
  Bu3	
     35	
  
      Sub Routine Call vs Interrupt
     Sub routine Call                                                            Interrupt
                             •  Occur due to an internal event
•  Occur due to execution of
                                (setting of flag) or an
   an instruction.
                                external event (key press).
•  Address of subroutine is  •  Address of ISR is determined
  determined by the address                                 by h/w (vectored / non
  part of an instruction.                                   vectored interrupt).
                                                  •  Other than contents of PC,
•  Stores only the contents of
                                                            store the state of processor
  PC (return address).
                                                            as well (all processor
                                                            registers).

                            CMP320	
  	
  	
  PUCIT	
  	
  	
  Arif	
  Bu3	
                 36	
  
Exec of Sub Routine Call & Interrupt
          Sub routine Call                                           Interrupt
•  When a subroutine is              •  An event that interrupts
   called, two things happen:           normal program execution.
      •  Address of next instr          When an interrupt occurs
         (contents of PC) are stored    following events occur:
         in a temporary location.                               •  CPU detects which device has
      •  Control is transferred to the                                   raised a request.
         beginning of sub routine.                              •  CPU stops what it was doing.
•    When a return is                                           •  CPU save the state of the
     encountered, the saved                                              program.
     return address is placed in                                •  Control move to a location where
     PC and the control transfer                                         a routine specific to that
     back to the next instr of                                           interrupt is lying.
                                                                •  Execute that routine.
     the calling program.
                                                                •  Restore state.
                                                                •  Resume execution of main
                                                                         program.
                            CMP320	
  	
  	
  PUCIT	
  	
  	
  Arif	
  Bu3	
                        37	
  
                        Interrupt Handling
1.  Processor assigns a signal, known as Interrupt Request Line, to each
    device that can issue an interrupt.
2.  Processor also assigns an Interrupt Acknowledge line that the
    processor uses to signal the device that it has received and begun to
    process the interrupt request.
3.  To interrupt the processor, a device sends a signal on its IRQ line and
    continue doing it until the processor acknowledges the interrupt on its
    interrupt acknowledge line.
4.  CPU chooses the branch address of the service routine (IH) in two
    ways:
      •    Vectored Interrupt. Source of interrupt supplies the branch information
           to the CPU (Intel processor uses this technique).
      •    Non Vectored Interrupt. Branch address is assigned to a fixed location
           in memory.
5.    CPU then performs a context switch.
6.    CPU executes the ISR.
7.    CPU again performs the context switch.
8.    CPU returns to some user program. 	
  	
  Arif	
  Bu3	
  
                                CMP320	
  	
  	
  PUCIT	
                     38	
  
Simple Interrupt Processing




          CMP320	
  	
  	
  PUCIT	
  	
  	
  Arif	
  Bu3	
     39	
  
Changes in Memory and Registers for
             Interrupt




5/1/2012	
     CMP320	
  	
  	
  PUCIT	
  	
  	
  Arif	
  Bu3	
     40	
  
                 Multiple Interrupts
•  Suppose an interrupt occurs while another
   interrupt is being processed.
  –  E.g. During printing, data being received via
     communications line.
•  Two approaches:
  –  Disable interrupts during interrupt processing
  –  Use a priority scheme.




  5/1/2012	
           CMP320	
  	
  	
  PUCIT	
  	
  	
  Arif	
  Bu3	
     41	
  
Sequential Interrupt Processing




5/1/2012	
     CMP320	
  	
  	
  PUCIT	
  	
  	
  Arif	
  Bu3	
     42	
  
      Nested Interrupt Processing




5/1/2012	
      CMP320	
  	
  	
  PUCIT	
  	
  	
  Arif	
  Bu3	
     43	
  
Example of Nested Interrupt




  Printer	
  with	
  priority	
  2,	
  	
  	
  	
  	
  	
  	
  	
  interrupts	
  at	
  	
  t=10	
  
  Disk	
  with	
  priority	
  4,	
  	
  	
  	
  	
  	
  	
  	
  	
  	
  	
  	
  	
  interrupts	
  at	
  t	
  =	
  20	
  
  Comm	
  line	
  with	
  priority	
  5,	
  interrupts	
  at	
  t	
  =	
  15	
  
                                                               CMP320	
  	
  	
  PUCIT	
  	
  	
  Arif	
  Bu3	
            44	
  
    Interrupts, Traps and Signals
•  Interrupt. An event generated by an I/O device to get
   the attention of CPU and control goes to the OS. State
   of the CPU is saved, ISR is executed and then state of
   CPU is restored.
•  Trap. An event generated by CPU and control goes to the
   OS. Normally when an instruction is executed that may
   cause a division by zero or protection error. State of
   CPU is not saved and TSR is executed.                                             Answer
•  Signal. An event given to a process not to CPU. Since a                             The
   process is a soft entry so signal is called soft interrupt.                        Phone
                                                                                         .
   In case of a signal the process can take one of there                                .
   possible actions:                                                                    .
                                                                                        .
    •  A default action defined by OS.                                                  .
    •  A programmer specified action for signal handling.                               .

    •  Ignore signal.                                                                Resume
                                CMP320	
  	
  	
  PUCIT	
  	
  	
  Arif	
  Bu3	
        45	
  
             I/O Techniques
•  When the processor encounters an
   instruction relating to I/O, it executes that
   instruction by issuing a command to the
   appropriate I/O module
•  Three techniques are possible for I/O
   operations:
  –  Programmed I/O
  –  Interrupt-driven I/O
  –  Direct memory access (DMA)

                      CMP320	
  	
  	
  PUCIT	
  	
  	
  Arif	
  Bu3	
     46	
  
                Programmed I/O
•  The I/O module performs the requested action and then sets
   the appropriate bits in the I/O status register but takes no
   further action to alert the processor
•  As there are no interrupts, the processor must determine
   when the instruction is complete
•  Instruction Set
   –  Control: Used to activate and instruct device, e.g. a
      magnetic-tape unit may be instructed to rewind or to move
      forward one record
   –  Status: Used to test various status conditions associated
      with an I/O module and its peripherals
   –  Transfer: Used to read and/or write data between
      processor registers and external devices
                         CMP320	
  	
  	
  PUCIT	
  	
  	
  Arif	
  Bu3	
     47	
  
        Programmed
        I/O Example
•  Data are read in one word at a
   time.
•  For each word that is read in,
   the processor must remain in a
   status-checking loop until it
   determines that the word is
   available in the I/O module’s
   data register.
•  This flowchart highlights the
   main disadvantage of this
   technique:
  •  It is a time-consuming process
     that keeps the processor busy
     needlessly.
                      CMP320	
  	
  	
  PUCIT	
  	
  	
  Arif	
  Bu3	
     48	
  
Interrupt-Driven I/O
•  Processor issues an I/O command to a
   module and then go on to do some other
   useful work.
•  The I/O module will then interrupt the
   processor to request service when it is
   ready to exchange data with the
   processor
•  Interrupt-driven I/O is more efficient
   than programmed I/O because it
   eliminates needless waiting.
•     However, interrupt-driven I/O still
     consumes a lot of processor time,
     because every word of data that goes
     from memory to I/O module or from I/O
     module to memory must pass through the
     processor.
     5/1/2012	
                 CMP320	
  	
  	
  PUCIT	
  	
  	
  Arif	
  Bu3	
     49	
  
         Direct Memory Access
WHY DMA ?
•  In Programmed I/O the CPU is involved in a constant loop &
   constant status checking. CPU cannot do any thing else.
   However the I/O transfer speed is quite fast
•  In Interrupt driven I/O some other functions are being
   done by the CPU & I/O interpretation takes place only when
   an interrupt is initiated. However in the entire duration of
   data transfer active participation of CPU is involved
•  This brings us to a third transfer mode and that is Direct
   Memory Access
•  DMA provides a direct path between I/O and the Memory
   sub system. It isolate the CPU form the active transfer of
   data to & fro from the I/O subsystem to the memory
   subsystem and vice versa
•  Lets discuss an example for better understanding
                         CMP320	
  	
  	
  PUCIT	
  	
  	
  Arif	
  Bu3	
     50	
  
           Direct Memory Access
Consider the following instruction
       LOAD [2] , [9]
Above is an Illegal instruction, as it is not possible to transfer data
from one memory location to another memory location without
involving CPU.
       LOAD R1 , [9]
       STORE [2] , R1
Same implies to transfer between memory & an I/O device:
       OUT dataport , [6]
Above is also an illegal instr, as it is not possible to transfer data
from a memory location to an I/O device without involving the CPU.
       LOAD R1 , [6]
       OUT dataport , R1
So, we see that the problem lies with the CPU, in both cases the CPU
unnecessarily act as a middle man.
                             CMP320	
  	
  	
  PUCIT	
  	
  	
  Arif	
  Bu3	
     51	
  
            Direct Memory Access
•  DMA is a mechanism by which data could directly be
   transferred from
    •  An I/O device to Memory subsystem
    •  Memory subsystem to an I/O device
    •  An I/O device to another I/O device
•  Advantages
    •  Better throughput & CPU time spent on transfer of
       data is reduced (CPU is involved only at the beginning
       or at the end of data transfer)
    •  Unnecessary interaction of CPU with I/O devices would
       not be there
•  Disadvantage
    •  Requirement of additional hardware- The DMA
       controller       CMP320	
  	
  	
  PUCIT	
  	
  	
  Arif	
  Bu3	
     52	
  
                          Direct Memory Access
     CPU	
  bus	
  signals	
  for	
  DMA	
  transfer	
  
                                                            ABUS	
                    Address	
  bus	
                 High-­‐impedence	
  
          	
  

      DMA	
  
          	
  
                   Bus	
  request	
  
                   Bus	
  granted	
  
                                         BR	
  

                                         BG	
  
                                                  CPU	
  
                                                            DBUS	
  
                                                              RD	
  
                                                              WR	
  
                                                                                      Data	
  bus	
  
                                                                                      Read	
  
                                                                                      Write	
  
                                                                                                                 }        (disabled)	
  
                                                                                                                          when	
  BG	
  is	
  
                                                                                                                           enabled	
  
•      During DMA transfer, the CPU is placed in an idle state having no
       control of the memory buses using following signals:
        •  Bus Request. BR i/p is used by the DMA controller to request the
           CPU to relinquish control of buses. When this input is active, the
           CPU terminates the execution of the current instruction and
           places the addr bus, the data bus and the read / write lines into a
           high impedance state
        •  Bus Grant. BG o/p is used by the CPU to inform the DMA
           controller that it can now take control of the buses to conduct
           memory transfers without CPU intervention.
•      When DMA controller completes the transfer, it disables the BR line.
       The CPU disables the BG line and takes control of the buses
                                                                  CMP320	
  	
  	
  PUCIT	
  	
  	
  Arif	
  Bu3	
                               53	
  
               PROTECTION
In Time Sharing System there are multiple
processes using various resources of the
computer. Sounds great, but like no free
lunch, it has disadvantage as well, i.e. the issue
of protection
§  Keep user programs from crashing the OS
§  Keep user programs from crashing each other
§  Keep parts of OS from crashing other parts
Protection is implemented by keeping two
modes
                     CMP320	
  	
  	
  PUCIT	
  	
  	
  Arif	
  Bu3	
     54	
  
                          Dual Mode Operation
•  To protect the OS and all other programs and
   their data from any malfunctioning program,
   protection is needed for any shared resource. It
   is done by keeping two modes:
    •  User Mode. Execution done on behalf of a
       user program
    •  Monitor/Kernel/System/Supervisor Mode.
       Execution done on behalf of OS
•  Mode bit added to computer h/w to indicate the
   current mode: Monitor (0), User (1) Interrupt/fault"
When	
  an	
  interrupt	
  or	
  fault	
  occurs	
  h/w	
  switches	
  to	
  monitor	
  
mode.	
  
	
                                                                                                            monitor!                    user"
Privileged	
  instruc3ons	
  can	
  only	
  be	
  executed	
  in	
  monitor	
                                            set user mode"
mode.	
  
                                                         CMP320	
  	
  	
  PUCIT	
  	
  	
  Arif	
  Bu3	
                                  55	
  
How to protect Processes from one another?
Need three important things:
•    Protection of I/O devices
     •    Every process should not have access to every device
•    Protection of memory
     •    A process should not access another process address
          space
•    Preemptive switching from task to task
     •    Use of timer
     •    Must not be able to disable timer from user code



                            CMP320	
  	
  	
  PUCIT	
  	
  	
  Arif	
  Bu3	
     56	
  
                  I/O PROTECTION
•    All I/O instructions are privileged instruction, no user
     process can execute an I/O instruction directly. If he/she
     is permitted he/she can always overwrite/delete some
     ones else data
•    I/O is done using system call. A way that an OS allows a
     user process to invoke an operation such as an I/O
     operation e.g. opening and reading a file
•    Following lines of Assy code displays xter ‘A’ on monitor screen
     MOV DL, ‘A’ ;Place xter to be displayed in DL
     MOV AH, 02 ;Place appropriate svc no / system call no in AH
     INT 21h          ;Call the interrupt
•    Following lines of Assy code input a xter and place it in AL register
     MOV AH, 01
     INT 21h
                                CMP320	
  	
  	
  PUCIT	
  	
  	
  Arif	
  Bu3	
     57	
  
           Memory Protection
•  Process Address Space. Region in the main
   memory that a process can legally access is known
   as its address space. A process must not be
   allowed to go outside its address space
•  Implementation. CPU uses two registers to
   determine the range of logical addresses a
   program may access
   •  Base Register holds the smallest/starting
      address of the Address Space assigned to a
      process
   •  Limit Register contains the size of the address
      space allocated to the process
                     CMP320	
  	
  	
  PUCIT	
  	
  	
  Arif	
  Bu3	
     58	
  
Memory Protection                                            (cont…)




        CMP320	
  	
  	
  PUCIT	
  	
  	
  Arif	
  Bu3	
               59	
  
Memory Protection                                            (cont…)




        CMP320	
  	
  	
  PUCIT	
  	
  	
  Arif	
  Bu3	
               60	
  
                         CPU Protection
•    In multiprogramming or time sharing OS, multiple
     processes are running at a time and we want to make sure
     that the CPU must not stay with a process for an infinite
     amount of time
•    Implementation.
     •    Timer interrupts computer after a specified period to ensure OS
          maintains control
     •    Timer (counter register) is loaded with a predetermined value and
          decremented every clock tick
     •    When the timer reaches the value 0, an interrupt occurs and an
          ISR is executed to switch CPU to another process
     •    How Timer is loaded? This is also a privileged instr, because no
          one other than the admin should be allowed to assign a time slice
          to various processes
                                 CMP320	
  	
  	
  PUCIT	
  	
  	
  Arif	
  Bu3	
     61	
  
Operating System
    Overview


      CMP320	
  	
  	
  PUCIT	
  	
  	
  Arif	
  Bu3	
     62	
  
Name some OSs




    CMP320	
  	
  	
  PUCIT	
  	
  	
  Arif	
  Bu3	
     63	
  
                Name some OSs
•  Linux (Ubuntu, Fedora,                                •  Android (IceCream
  OpenSuse, Red Hat,…)                                             Sandwich)from Google
•  Unix                                                  •  BlackBerry from RIM
•  Mac OS X Mountain Lion                                •  iOS from Apple
•  MS Windows 7                                          •  Symbian from Nokia
•  MS Windows 8                                          •  Windows phone from MS
                                                         •  ….




                            CMP320	
  	
  	
  PUCIT	
  	
  	
  Arif	
  Bu3	
              64	
  
               What Is an OS?
“Code” that:
•  Sits between programs & hardware
•  Sits between different programs
•  Sits betweens different users
But what does it do?
  Provides an orderly and controlled allocation of the
  processor(s), memory(ies) and I/O devices among the
  various programs competing for them

Loose analogy:
   –  Government: creates and enforces laws that govern
      resources (money, land, houses, vehicles, oil, etc.)
      but allows citizens to have freedom with using the
      resources (as long as the citizen obeys laws)
                        CMP320	
  	
  	
  PUCIT	
  	
  	
  Arif	
  Bu3	
     65	
  
             What Is an OS? (…)
  Resources                                           Services
  •  Allocation                                       •  Abstraction
  •  Protection                                       •  Simplification
  •  Reclamation                                      •  Convenience
  •  Virtualization                                   •  Standardization

Resource management includes multiplexing (sharing)
resources in two ways:
•  Time Multiplexed (CPU sharing, Printer sharing).
•  Space Multiplexed (Memory, Hard Disk).

                           CMP320	
  	
  	
  PUCIT	
  	
  	
  Arif	
  Bu3	
     66	
  
         What Is an OS? (…)
                                                                           Government

                               Finite resources                          Limited budget,
Resources                      Competing demands                              Land,
                                                                               Oil,
•  Allocation                  Examples:                                       Gas,

•  Protection                  •  CPU
•  Reclamation                 •  Memory
                               •  Disk
•  Virtualization
                               •  Network




                    CMP320	
  	
  	
  PUCIT	
  	
  	
  Arif	
  Bu3	
              67	
  
         What Is an OS? (…)
                                                                          Government

                                                                         Law and order
Resources            You can’t hurt me
•  Allocation        I can’t hurt you
•  Protection
                     Implies some degree of
•  Reclamation         safety & security
•  Virtualization




                    CMP320	
  	
  	
  PUCIT	
  	
  	
  Arif	
  Bu3	
             68	
  
          What Is an OS?(…)
                                                                         Government

                                                                         Income Tax
Resources                       The OS gives
•  Allocation                   The OS takes away

•  Protection
                                Voluntary at run time
•  Reclamation                  Implied at termination
•  Virtualization               Involuntary
                                Cooperative




                    CMP320	
  	
  	
  PUCIT	
  	
  	
  Arif	
  Bu3	
           69	
  
           What Is an OS? (…)
                                                                          Government
                    Illusion of infinite,                                Social security
Resources              private resources
•  Allocation
•  Protection       Memory versus disk
                    Timeshared CPU
•  Reclamation
•  Virtualization   More extreme cases
                     possible (& exist)




                    CMP320	
  	
  	
  PUCIT	
  	
  	
  Arif	
  Bu3	
              70	
  
                    What is an OS? (…)
Objective of an OS is to Tame the h/w so that people can program and can get something useful out of it.


Top Down View: A program that acts as an intermediary between a
user of a computer and the computer hardware. Present the user with the
equivalent of an extended machine or virtual machine that is easier to
program than the underlying hardware. (HOW?)

Bottom Up View: A program that allocates and de-allocates computer
system resources (CPUs, memories, timers, disks, mice, network
interfaces, printers, …) in an efficient, fair and secure manner. (HOW?)

“An OS is a program running at all times on the computer (usually
called the kernel), that controls the execution of application programs
and acts as an interface between the user of a computer and the
computer hardware.”
“Primary goal of OS is convenience of user and secondary goal is
efficient operation of the computer system.”
                                          CMP320	
  	
  	
  PUCIT	
  	
  	
  Arif	
  Bu3	
        71	
  
 History of Operating Systems
•  First generation 1945 – 1955
  –  vacuum tubes, plug boards (no OS, signup
     sheets or punch cards)
•  Second generation 1955 – 1965
  –  transistors, batch systems
•  Third generation 1965 – 1980
  –  ICs and multiprogramming
•  Fourth generation 1980 – 1995
  –  personal computers, networks and
     distributed systems
–  Fifth generation 1995 – present
  –  Mobile systems
                      CMP320	
  	
  	
  PUCIT	
  	
  	
  Arif	
  Bu3	
     72	
  
        First Generation (1945 – 1955)
•  In these early days, a single group of people designed, built,
   programmed, operated and maintained each machine
•  All programming was done in absolute machine language, often by wiring
   up plug boards to control the machine’s basic functions
•  Programming languages were unknown (even assembly language was
  unknown)
•  Operating Systems were unheard of
•  The programmer used to sign up for a block of time on the signup sheet
  on the wall, then come down to the machine room, insert his plug board
  into the computer and spend the next few hours hoping that none of
  the 20,000 or so vacuum tubes would burn out during the run
•  By early 1950s, with the advent of punch cards, it was now possible to
  write programs on cards and read them in instead of using plug boards

                               CMP320	
  	
  	
  PUCIT	
  	
  	
  Arif	
  Bu3	
     73	
  
         ENIAC: (1945—1955)




•  “The machine designed by Drs. Eckert and Mauchly was a
   monstrosity. When it was finished, the ENIAC filled an
   entire room, weighed thirty tons, and consumed two
   hundred kilowatts of power.”
•  http://ei.cs.vt.edu/~history/ENIAC.Richey.HTML
                       CMP320	
  	
  	
  PUCIT	
  	
  	
  Arif	
  Bu3	
     74	
  
        Second Generation (1955 – 1965)
•  The introduction of transistor in mid 1950s changed the
   picture radically
•  Now there was a clear separation between designers,
   builders, operators, programmers and maintenance
   personnel
•  The machines called mainframes, were locked away in
   specially air conditioned computer rooms, with specially
   trained professional operators to run them
•  To run a job: (Serial Processing)
   •    Programmer would first write program on paper (FORTRAN, BASIC, COBOL)
   •    Punch it on cards
   •    Bring the card deck to the input room and hand it over to operator
   •    Go drink coffee
   •    Operator run the job on the machine and before running might need to load FORTRAN compiler
        as well. After running job he then go over to the printer, tear off the output and carry it over to
        the output room, to hand it over to the programmer

•  Limitations. Setup time, Job Scheduling
                                          CMP320	
  	
  	
  PUCIT	
  	
  	
  Arif	
  Bu3	
          75	
  
              Second Generation (cont…)
Batch Processing and Batch OS
•  Reduce setup time by batching similar jobs
•  Automatic job sequencing – automatically transfers control
   from one job to another
•  In simple Batch system a user prepares his/her job (on
   card or tape) offline and submits it to the computer center
   A computer operator batches the jobs together
   sequentially
•  Limitations
   1.    CPU sits idle when there is a job transition
         Ø  Overcome by Resident Monitor
   2.    Speed differential
         Ø  Overcome by two approaches to improve system performance by overlapping IO
             and processing (Buffering and Spooling)
   3.    Non interactive environment
   4.    Offline debugging
                                    CMP320	
  	
  	
  PUCIT	
  	
  	
  Arif	
  Bu3	
     76	
  
                Second Generation (cont…)
Batch Processing and Batch OS




An Early Batch System.                           1401: Character-oriented commercial
                                                 computers used for tape sorting and
a.  Programmers bring cards to 1401              printing
b.  1401 reads batch of jobs onto tape           7094: Word-oriented large scale scientific
                                                 computers used for numerical calculations
c.  Operator carries input tape to 7094          in science and engineering.

d.  7094 does computing
e.  Operator carries output tape to 1401 for printing offline (i.e. not
    connected to the main computer)
f.  1401 prints output        CMP320	
  	
  	
  PUCIT	
  	
  	
  Arif	
  Bu3	
         77	
  
          Second Generation (cont…)
Structure of a typical FMS (Fortran Monitor System) Job.




                                                                            These primitive control cards
                                                                            were the forerunners of
                                                                            modern job control languages
                                                                            and command interpreters.
                       CMP320	
  	
  	
  PUCIT	
  	
  	
  Arif	
  Bu3	
                             78	
  
                  Second Generation (cont…)
Batch Processing and Batch OS
•  Process Scheduling, Memory Management, File Management
   and I/O Management in Batch Processing are quite simple
   Ø  Process Scheduling: Jobs are typically processed in the order of
         submission
   Ø  Memory Management: Memory is typically divided into two areas
         one for the Resident Monitor and other is User Program Area, when
         one program is over the new program is loaded into the same area
   Ø  File Management: Access to files is also serial and there is hardly a
         need of protection and File Access Control Mechanism
   Ø  I/O Management: Since there is only one program executing at a
       time, so there is no competition for I/O devices, therefore
         allocation and de-allocation of I/O devices is trivial
   5/1/2012	
                     CMP320	
  	
  	
  PUCIT	
  	
  	
  Arif	
  Bu3	
     79	
  
                  Second Generation (cont…)
•  Resident Monitor
Ø  One of the problem in simple Batch Processing is                               Int	
  Processing	
  
    “The CPU sits idle when there is a job
    transition”. This problem is over come by a small                              Device	
  Drivers	
  

    program called Resident Monitor
                                                                                  Job	
  Sequencing	
  
Ø  Monitor reads jobs one at a time from the I/P
    device (card reader / Magnetic tape). Current job                             JCL	
  Interpreter	
  
    is placed in the user program area and control is
    passed to this job. When job completes control
                                                                                         User	
  
    transfers back to the monitor, which then loads                                    Program	
  
    next job                                                                             Area	
  

Ø  Job Control Language (JCL) is a special type of
    programming language used to provide instructions
    to monitor
   5/1/2012	
                CMP320	
  	
  	
  PUCIT	
  	
  	
  Arif	
  Bu3	
                       80	
  
                   Buffering VS Spooling
                                                                        •  Simultaneous Peripheral
•  Buffering is a method of
  overlapping I/O and                                                             Operations Online allows
  processing of a single job                                                      CPU to overlap the input of
    Ø  Input                                                                     one job with the computation
                                                                                  and output of other jobs
 CPU	
             Buffers	
      Input	
  Device	
                      •  It essentially use the disk as
                                                                           a large buffer for reading and
       Ø Out put                                                          for storing output files
  CPU	
             Buffers	
      Output	
  Device	
                    •  Advantages
•  Since the CPU is faster than                                                       •           Speedy computation at the cost
   the I/O device, the speed of                                                                   of some disk space and few
                                                                                                  tables kept by OS
   execution is controlled by the
                                                                                      •           Keeps both CPU and I/O devices
   I/O device and not by the
                                                                                                  working at much higher rates
   speed of CPU
    5/1/2012	
                               CMP320	
  	
  	
  PUCIT	
  	
  	
  Arif	
  Bu3	
                               81	
  
       Third Generation (1965 – 1980)
•  IBM came up with System/360; the first major computer
   line to use (small-scale) Integrated Circuits. It was
   designed to handle both scientific (i.e., numerical) and
   commercial computing. The OS/360 was the OS that was
   designed to handle the giant
•  Later IBM came up with 370, 4300, 3080, 3090, and Z-
   series
•  Several key techniques absent in second generation
  operating systems were introduced in OS/360:
   Ø  Multiprogramming. On the 7094, when the current job paused to wait
       for an I/O operation to complete, the CPU simply sat idle until the I/O
         finished. Solution was multiprogramming
   Ø  SPOOLING: With spooling, the 1401s were no longer needed
   5/1/2012	
                    CMP320	
  	
  	
  PUCIT	
  	
  	
  Arif	
  Bu3	
     82	
  
                  Third Generation                                                (cont…)
Multiprogramming / Multiprogrammed OS
•  Buffering improve system performance by
  overlapping the I/O and computation of a
  single job. Spooling improve system
  performance by overlapping the I/O of one
  job with computation and output of another
  job
•  A single user cannot keep CPU and I/O devices
  busy at all times. Multiprogramming offers a
  more efficient approach to increase system
  performance
•  Several jobs are kept in main memory at the
  same time and the CPU is multiplexed among
  them
   5/1/2012	
                CMP320	
  	
  	
  PUCIT	
  	
  	
  Arif	
  Bu3	
               83	
  
Multiprogramming/Multiprogrammed OS                                                                                                                                        (cont…)
 Sequential Execution                                                                                                                                                      CPU	
  Burst	
  
         t1	
              t2	
              t3	
              t4	
              t5	
                t6	
                   t7	
               t8	
     t9	
     t10	
     I/O	
  Burst	
  




Execution in a multiprogramming Environment
                  t1	
              t2	
              t3	
              t4	
              t5	
                     t6	
  
P1	
  
P2	
  


•  Compared to OS which supports only sequential execution,
   multiprogramming systems requires following features:
              •  SPOOLING
              •  Memory management
              •  CPU Scheduling
             5/1/2012	
                                                                            CMP320	
  	
  	
  PUCIT	
  	
  	
  Arif	
  Bu3	
                              84	
  
                  Third Generation                                                   (cont…)
Time Sharing OS
•  With third generation systems, the time between submitting a job and
   getting back the output was often hours, so a single misplaced comma
   could cause a compilation to fail, and the programmer to waste half a
   day
•  This gave introduction to time sharing, in which each user has an online
   terminal
•  It is a form of multi-programmed OS which operates in a interactive
   mode with a quick response time
•  In Timesharing System, each user is given a time slice/quantum. The
   user program/process executes for a short time before it either
   finishes or needs to perform I/O. the resources are then taken away
   from the user and given to some one else. This is hardly noticeable and
   the user thinks as if he is using all the resources by himself
   –  Response time should be < 1 second
   –  If several jobs ready to run at the same time [ CPU scheduling
   –  If processes don’t fit in memory, swapping moves them in and out to run
   5/1/2012	
                   CMP320	
  	
  	
  PUCIT	
  	
  	
  Arif	
  Bu3	
               85	
  
Batch Multiprogramming VS Time Sharing

Batch Multiprogramming Time Sharing
•  Event Driven                                          •  Time Driven

•  Objective is to maximize                              •  Objective is to minimize
  processor use                                                    response time

•  Source of instructions to OS                          •  Source of instructions to OS
  is the JCL instructions                                          are commands entered at the
  provided with job                                                terminal




  5/1/2012	
                  CMP320	
  	
  	
  PUCIT	
  	
  	
  Arif	
  Bu3	
             86	
  
                   Third Generation                                                       (cont…)

MULTICS
MULTiplexed Informaton and Computing Service)

•  First large Time Sharing
   System
•  The 6180 at MIT , skin
   doors open, circa 1976




                                                    http://www.multicians.org/multics-stories.html
    5/1/2012	
                       CMP320	
  	
  	
  PUCIT	
  	
  	
  Arif	
  Bu3	
               87	
  
                  Third Generation                                                  (cont…)
Mini Computers
•  Another major development during the third generation was the growth
  of minicomputers, starting with the Digital Equipment Company (DEC)
  PDP-1 in 1961

•  The PDP-1 had only 4K of 18 bit words, but at $120,000 per machine
  (less than 5 percent of the price of a 7094), it sold like hotcakes.

•  It followed by a series of other PDPs culminating in the PDP-11




   5/1/2012	
                  CMP320	
  	
  	
  PUCIT	
  	
  	
  Arif	
  Bu3	
               88	
  
                 Early Disk History




        1973:                                                                   1979:
        1. 7 Mbit/sq. in                                                        7. 7 Mbit/sq. in
        140 MBytes                                                              2,300 MBytes

               Contrast: Seagate 1TB,
               164 GB/SQ in, 3½ in disk,
               4 platters
5/1/2012	
                 CMP320	
  	
  	
  PUCIT	
  	
  	
  Arif	
  Bu3	
                        89	
  
The ARPANet (1968-1970’s)
    SRI	
  
    SDS	
  940	
                                             Utah	
  
                                                             PDP	
  10	
  
                                 IMPs	
                                                      •  Paul	
  Baran	
  
UCSB	
                                                                                           –  RAND	
  Corp,	
  early	
  1960s	
  
IBM	
  360	
  
                                                                                                 –  Communica8ons	
  networks	
  
         UCLA	
                                                                                     that	
  would	
  survive	
  a	
  major	
  
         Sigma	
  7	
                                                                               enemy	
  a3ack	
  
                                                                                             •  ARPANet:	
  Research	
  vehicle	
  for	
  
                                                                                                “Resource	
  Sharing	
  Computer	
  
                                                                                                Networks”	
  
                                                                                                 –  2	
  September	
  1969:	
  UCLA	
  first	
  
                                                                                                    node	
  on	
  the	
  ARPANet	
  
                                                                                                 –  December	
  1969:	
  4	
  nodes	
  
                                                                                                    connected	
  by	
  56	
  kbps	
  phone	
  
BBN	
  team	
  that	
  implemented	
                                                                lines	
  
the	
  interface	
  message	
  processor	
                                                       –  1971:	
  First	
  Email	
  
h3p://www.cnn.com/2004/TECH/internet/08/29/internet.birthday.ap/                                 –  1970’s:	
  <100	
  computers	
  
index.html	
  	
  
       5/1/2012	
                                   CMP320	
  	
  	
  PUCIT	
  	
  	
  Arif	
  Bu3	
                                      90	
  
                 Fourth Generation (1980 – 1995)
•  With the development of LSI circuits, the age of the
   microprocessor-based personal computer dawned.
   (initially called microcomputers)
•  Intel came out with the 8080 (first general purpose 8-
   bit microprocessor, in 1974)
•  Motorola also produced an 8bit microprocessor, the
   6800
•  In early 1980s Intel came out with 8088 and 8086 with
   MS-DOS and quickly dominate the IBM PC market
•  An interesting development began taking place during
   the mid-1980s is the growth of networks of personal
   computers running Network Operating Systems and
   Distributed Operating Systems
  5/1/2012	
              CMP320	
  	
  	
  PUCIT	
  	
  	
  Arif	
  Bu3	
     91	
  
         Network Operating Systems
•  In NOS, the users are aware of the existence of multiple
   computers and can log in to remote machines and copy files
   from one machine to another
•  Each machine runs its own local OS and has its own local
   user(s)
•  A NOS is a collection of s/w and associated protocols that
   allow a set of autonomous computers which are inter-
   connected by a computer NW to be used together in a
   convenient and cost effective manner
•  Remote Login. Each user normally works on his/her own system; using a
   different system requires some kind of remote login, instead of having
   the OS dynamically allocate processes to CPU
                            telnet pucit.edu.pk
•  Remote File Transfer. Users are aware of where their files are kept
   and must move file from one system to another with explicit file
   transfer commands instead of having file placement managed by OS
                              ftp pucit.edu.pk
   5/1/2012	
                 CMP320	
  	
  	
  PUCIT	
  	
  	
  Arif	
  Bu3	
     92	
  
                 Distributed OS
•  A Distributed System is a collection of independent
  computers that appears to its users as a single
  coherent system

•  The users should not be aware of where their
  programs are being run or where their files are
  located; that should all be handled automatically
  and efficiently by the Operating System
   “A distributed system is one where I can’t do work
   because some machine (in some other part of the
   world) I have never heard of isn’t working”
  5/1/2012	
           CMP320	
  	
  	
  PUCIT	
  	
  	
  Arif	
  Bu3	
     Lamport   93	
  
                   NOS vs DOS
•  File System. In NOS, control over file placement
   must be done manually by the user, where as in a
   DOS it is done automatically by the system itself
•  Protection. In NOS, there are various machines,
   each with its own user to UID, but in DOS there is
   a single system wide mapping that is valid every
   where
•  Program Execution. In the most distributed case
   the system chooses a CPU by looking at the
   processing load of the machine, location of file to
   be used etc. In the least distributed case, the
   system always run the process on one specific
   machine. (usually the machine on which the user is logged in)
   5/1/2012	
             CMP320	
  	
  	
  PUCIT	
  	
  	
  Arif	
  Bu3	
     94	
  
                  Real Time Systems
•  In Real Time systems, the correctness of the system
   depends not only on the logical result of computation but
   also on the time at which the results are produced
•  Examples are Process Control Plants, Robotics, Air Traffic
   Control, Telecommunications, Missile Control System
•  Hard Real Time System. Output should be produced within
   the given time constraints, otherwise, the result is life
   threatening; e.g. Plane landing systems, process control in
   nuclear power plants, missile control system. Secondary
   storage is limited or absent, data stored in short term
   memory or ROM. No virtual memory
•  Soft Real Time System. Output should be produced within
   the given time constraints, but if it is not, the result is not
   life threatening; e.g. applications of multimedia and virtual
   reality
   5/1/2012	
             CMP320	
  	
  	
  PUCIT	
  	
  	
  Arif	
  Bu3	
     95	
  
                 Fifth Generation (1995 – )
•  Ubiquitous Mobile Devices
    –  Laptops, PDAs, phones
    –  Small, portable, and inexpensive
        •  Recently twice as many smart phones as PDAs
        •  Many computers/person!
    –  Limited capabilities (memory, CPU, power, etc…)
•  Wireless/Wide Area Networking
    –  Leveraging the infrastructure
    –  Huge distributed pool of resources extend devices
    –  Traditional computers split into pieces. Wireless
       keyboards/mice, CPU distributed, storage remote
•  Client Server, Peer-to-peer, and Web Based Computing
  5/1/2012	
            CMP320	
  	
  	
  PUCIT	
  	
  	
  Arif	
  Bu3	
     96	
  
                 Computing Environment
•  Traditional computer
   –  Blurring over time
   –  Office environment
       •  PCs connected to a network, terminals
          attached to mainframe or minicomputers
          providing batch and timesharing
       •  Now portals allowing networked and remote
          systems access to same resources
   –  Home networks
       •  Used to be single system, then modems
       •  Now firewalled, networked
  5/1/2012	
            CMP320	
  	
  	
  PUCIT	
  	
  	
  Arif	
  Bu3	
     97	
  
                 Computing Environment (…)
  Client-Server Computing

     Dumb          terminals supplanted by smart PCs
     Many   systems now servers, responding to requests
        generated by clients
           Compute-server        provides an interface to client to
                 request services (i.e. database)
           File-server      provides interface for clients to store
                 and retrieve files




  5/1/2012	
                       CMP320	
  	
  	
  PUCIT	
  	
  	
  Arif	
  Bu3	
     98	
  
         Computing Environment (…)
•  Peer to Peer Computing
•  Another model of distributed system
•  P2P does not distinguish clients and servers
   –  Instead all nodes are considered peers
   –  May each act as client, server or both
   –  Node must join P2P network
      •  Registers its service with central lookup service
         on network, or
      •  Broadcast request for service and respond to
         requests for service via discovery protocol
   –  Examples include Napster	
  	
  A,rif	
  KaZaA, and Gnutella
   5/1/2012	
           CMP320	
  	
  	
  PUCIT	
   Bu3	
            99	
  
                 Computing Environment (…)
Web Based Computing
•  Web has become ubiquitous
•  PCs most prevalent devices
•  More devices becoming networked to allow web
   access
•  New category of devices to manage web
   traffic among similar servers: load balancers
•  Use of operating systems like Windows 95,
   client-side, have evolved into Linux and
   Windows 7, which can be clients and servers

  5/1/2012	
              CMP320	
  	
  	
  PUCIT	
  	
  	
  Arif	
  Bu3	
     100	
  
                  Computing Environment (…)
Multiprocessor Systems
•  Also called parallel systems or tightly coupled systems
•  Multiple CPUs in a single entity, comm using system bus
•  Advantages
    •  Increased throughput
    •  Increased reliability (Graceful degradation, fault tolerance)
    •  Saves money by not duplicating power supplies, housings,
       and peripherals
•  Disadvantage
    •  More complex in both hardware and software than uni-
       processor systems
•  Types
    •  Symmetric multiprocessors All processors are peers and
       I/O can be processed on any CPU
    •  Asymmetric multiprocessors Master slave scenario.
       Master distributes tasks among the slaves, and I/O is
       usually done by master only
   5/1/2012	
              CMP320	
  	
  	
  PUCIT	
  	
  	
  Arif	
  Bu3	
     101	
  
           Computing Environment (…)
Clustered Systems
•  Constructed by combining multiple computers into a
   single system to perform a computational task
   distributed across the cluster
•  They share storage and are linked via LAN
•  Clustered systems communicate using messages, while
   processors in a multiprocessor system could
   communicate using shared memory
•  Used to provide high available service. Can be:
     •  Asymmetric Cluster One machine is in hot standby
         mode, doing nothing, while other is running. Hot
         standby mode machine monitors the server. If
         server fails hot stand by host become active server
     •  Symmetric / Parallel Cluster Two or more hosts
         are running an application and monitoring each other.
         More efficient as it utilizes all of the available
         hardware
   5/1/2012	
  
                            CMP320	
  	
  	
  PUCIT	
  	
  	
  Arif	
  Bu3	
   102	
  
                       Embedded OS
•  Pervasive Computing
    •  Cheap processors embedded every where
    •  How many are on your body now? In your car?
    •  Cell phones, PDAs, iPads, iPod…
•  Typically very constrained h/w resources
    •  Slow processors
    •  Small amount of memory
    •  No disk or tiny disk
    •  Typically only one dedicated application.
    •  Limited power
•  But technology changes fast
    •  Embedded CPUs are getting faster
    •  Storage is growing rapidlyBu3	
  
    5/1/2012	
           CMP320	
  	
  	
  PUCIT	
  	
  	
  Arif	
   103	
  
               SUMMARY


5/1/2012	
       CMP320	
  	
  	
  PUCIT	
  	
  	
  Arif	
  Bu3	
     104	
  
We’re done for now, but Todo’s for
you after this lecture…

•  Go through the slides and Book Sections: 1.1-1.12
•  Go through Unix The Text Book Chapters 0 - 3
•  Get a Secure Shell account in the Lab. Log in using your SSH
   account in lab and run basic shell commands from the tutorial.
•  Copy following from \\printsrv\Teacher Data\Arif Butt\OS
   •  ITC Lecture Slides (Basic Linux Commands)
   •  Basic Linux Tutorial
   •  Unix The Text Book (By Dr Mansoor Sarwar) Chapters 0 - 3
   •  Virtual Box 4.1.4
•  If you are using MS Windows at your home PC, please dual boot
   it with some Linux distribution or install Linux in virtual
   environment using Virtual Box

If you have problems visit me in student counseling hours. . . .
                               CMP320	
  	
  	
  PUCIT	
  	
  	
  Arif	
  Bu3	
     105	
  

				
DOCUMENT INFO
Shared By:
Categories:
Tags:
Stats:
views:0
posted:3/3/2013
language:English
pages:105