FPGA Control of Induction Motors _SD1019_ - ECE Department Wiki by pptfiles


									Generating VHDL Code from XILINX
Files Generated after VHDL Code is
Creating new Project and checking
Only after there were no syntax we are
   able to assign Pins( PlanAhead-
Assigning Pins
FPGA board connected
BIT string file generated.
         NOTE on B-String File.
• Bit-string file is the very important file.
• It shows that our project was done as what is
  supposed to do until now.
• After downloading the .bit and .ucf file we are
  basically done with the project.
• Which shows our code was successfully
  downloaded and ran on FPGA developing
ISE Impact ( downloading code into
Code downloaded!
(And our Project Work)
            Manual J-K FlipFlop
• Finally, in order to know our project was going in
  the right direction we build manual JK flipflop.
• We connected the manual design to our motor .
• We gave the signal to jk flipflop by external signal
  generator and the six output were transmitted to
  our inverter ( that we made) and the final output
  was given to our motor.
• And it ran the motor.
      Part          Quantity   Retail Cost   Expected Cost   Total Cost                 Notes

                       1          $400            $0            $0        We will use one that is already
 FPGA Board                                                               available from Dr. Ababei. For
   (XILINX                                                                universities the discount cost is
  developing                                                                        about $250.

Induction Motor        1       $200-$300      $200-$300      $200-$300     Dr. Yuvarajan will let us know
                                                                               which one to buy later.

   IRAM136             1        $50-$60        $50-$60        $50-$60        Dr. Yuvarajan’s estimated
    Inverter                                                                         amount.

Xilinx Software        1       $0-$3000           $0            $0        Free 4 weeks trial trial version is
(Altera is free).                                                             available. Plan to rotate

    Matlab/            1         $6000            $0            $0            Installed on power lab
   Simulink                                                                computers. Student version is
   Software                                                                         about $500.

                                              Total Max.       $360
1. In order to understand the design process, we
   had to go through the different journals, papers
2. All the member of the group learned about the
   Simulink and the design for the motor control.
   We used this to make the prototype of our
   whole design process.
3. Inorder to make sure that our design process is
   correct, each of the team member used
   different process to control the motor like PWM,
   Sine PWM, and JK flip-flop.
3. Now after the initial design model for the motor
   control was completed, we downloaded the Xilinx
   ISE suite to add the Simulink Xilinx blocks in our
   personal laptops.
4. So, we started to make the blocks to control the
5. Inorder to output the six pulses with three pulses
   with 120 phase difference with each other and
   other three pulses with the inverted original
   signal, we used 3 J-K flip flop.
6. For controlling the Torque of the Motor, we
  used the frequency controller in the simulink
  model. The frequency divider, can be turned
  on and off with just turning on the specific
7. Now after the final model was completed, we
  checked the outputs from these J-K flip flops
  and these were correct.
8. Now we used the Xilinx System Generator to
  generate the VHDL code.
9. The VHDL code was accompanied by other
  files we needed for the download of code in
  the FPGA.
10. Now we opened the ISE Project Navigator
  download the VHDL code in the Xilinx FPGA.
11. We used Plan Ahead software which is a
  built in software inside the ISE Project
  Navigator to assign the input and output pins
  of the FPGA.
12. We used another software IMPACT inside
  the ISE suite to finally download the bit string
  file generated in the process of downloading
  the code.
13. The code was successfully downloaded in
  the FPGA.
14. The outputs we were anticipating were
  different from what we got in the process.
15. Some of the outputs we got were able to
  turn on the LED’S of the FPGA but they were
  not able to drive the motor.
16. The exact reason for this was unknown.
17. However the analog J-K flip flop we used in
  the process was able to run the motor.
18. For the Hardware, we had to design the
  Inverter to drive the motor. The six IGBT’s
  were used to convert the digital signal into the
  sinusoidal. These sinusoidal signals different in
  phase were supplied to the motor to run the
                    1. Matlab
1. The NDSU Matlab version is only limed to the student
2. There are no power electronics and other block we
   need to build the complete prototype for the design
   circuit to see how the design model works.
3. The CEA tech has no solution for this and requires us
   to get the full version only when department is ready
   to pay.
4. The Simulink we learned in the control class was basic
   and doesnot cover this portion of the topic.
       Solution to this Problem
• We had to get the full version from outside to
  download in our personal laptops.
• Each of us worked individually to get this in
  our laptops.
• We had to learn the Simulink individually and
  know about how these block works with the
  limited resources.
    Control pulses to the inverter
• There are various methods to control the
  method. Some are:
(a) Pulse Width Modulation Control
(b) Sine PWM
(c) J-K flip-flop
(d) Space Vector PWM control
The problem was to decide which method to
    decide to control the motor. (continue.)
• We could not use the Sine PWM because the
  digital system doesnot work with this kind of
• Simple PWM also could not be used because
  these signal are not converted into the VHDL
  code when try to generate through the System
• So the only method we could use were Jk flip-
  flop and Space Vector PWM.
            Xilinx and ISE design
• The problem with this was the cost of the software.
• The ISE suite required for this project costs around
  $3000 and we had to find the trial version of this
  software from the Xilinx website.
• The other problem with this was to know which
  version of the Xilinx ISE suite to download. The ISE
  suite works with specific version of Matlab.
• While downloading the software, there are many
  forms to fill and the IP requirements with the License
• The download of the software alone takes about 4
• The other problem with the software is that it can
  be downloaded only in the Window XP.
• So, we have to make the virtual computer inside
  our Window Vista and download the Window XP
  in that virtual computer.
• We again had to get the Matlab installed in the
  virtual computer.
• Moreover the Matlab and Xilinx are big software
  and requires huge amount of storage memory.
  So, we had to delete many files from our laptops
  before downloading the softwares.
     Xilinx blocksets in Simulink
• Xilinx has its own set of blocks.
• In order to make the control blocks with the
  Xilinx blocksets, we had to learn how these
  Xilinx blocks work.
• The Space Vector PWM is a complicated
  process which requires the deep knowledge to
  figure it out.
                 J-K flip flop
• Each J-K flip flop has to be built using the
  Xilinx blocks.
• Had to go through different models through
  the Dr. Srinivasan and online to figure it out.
              Xilinx ISE Suite
• The Xilinx software is a huge software and no
  one in the ECE department has the knowledge
  to use it.
• Had to go through different examples from
  Xilinx to learn how to download the code to
  the Xilinx FPGA.
• The various examples had their own way of
  doing things. So, need to find out what works
  and what does not.
• The ISE suite is made up of other many software inside
• We had to go through the manual and other Xilinx
  websites to learn how to use the other software too.
• The pin assignment was other big problem we
• The PlanAhead software is used to assign the pins in
  the FPGA and had to go through 100 pages just to
  know how to use this software and assign pins.
• The FPGA has in total of 72 pins and we had to go
  through another huge amount of pages in manual to
  learn about the pins.
• ISE suite has its tool to check whether the
  VHDL code generated from the System
  Generator in Simulink has some problems or
• The VHDL code we generated shows some
  warnings and has no specific way to solve the
• The VHDL code itself is 8 pages code and none
  of us know how the whole code works.
• The VHDL code was big and the output from
  the Simulink model shows that the output we
  get is correct.
• But the problem arises when we check the
  code validity in the ISE suite.
• We were able to download the code to the
  FPGA through the different window called
  IMPACT which is inside the ISE suite and
  needed to download the code to the FPGA.
• We were able to get some of the outputs from
  the FPGA but the outputs were not what they
  were supposed to be as seen in the Simulink.
• We tried to work through the trial and error
  method but still could not get it.
 Xilinx ISE suite trial version expire
• The other problem we encountered was that the trial
  version of our ISE suite expired and we could not use it
  for our design purpose.
• So, we asked help from the CEA tech to download the
  trial version in our design computer.
• The problem with this was that the CEA tech supporter
  could not download it completely as the software
  requires the license check off and the internet from our
  campus has no fixed IP address.
• We had to spend days with them just to figure out how
  to do it.
• We again decided to download it in our personal
  laptops but we could only download the trial
  version with the same IP address only once.
• So, we had to go to the friends apartment to get
  it downloaded in the laptops.
• The other problem with this was that the entire
  earlier Xilinx file and the Matlab has to be deleted
  before downloading the Xilinx ISE suite again.
• We even found the complete VHDL code
  required to run the motor but even the whole
  code and the other files required to run the
  motor did not work.
• The code and the files were made for the
  earlier version of the Xilinx.

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