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A Highly-Integrated_ Low-Power_ Ultra-Wideband Transceiver for Low

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					A Highly-Integrated, Low-Power, Ultra-Wideband Transceiver for Low-Rate, Indoor Wireless Systems

Ian O’Donnell University of California, Berkeley
November 21, 2000

Indoor Wireless Low-Rate Applications

Bluetooth/ Intercom

Smart Toys/ Inventory Control

Machine Control/ Monitoring

Smart Home/ Smart Office

Common Radio Characteristics
• Short Range Transmissions
Cell Size ~5 meters

• Low, Scalable Bit-Rate
100 bps – 100kbps

• Low Power
Power Target < 1mW (TX + RX @ 100kbps)

• Flexible Communications
Broadcast and Peer to Peer

• Small, Simple, Low-Cost

Existing Solutions
Transceiver Power vs. Throughput

Ericsson Bluetooth Porret, Melly, Enz, Vittoz1
20kbps RX: 1mW TX: 21mW Up to 1Mbps RX: 150mW TX: 100mW

RFM TR3000
115kps RX: 15mW TX: 36mW

TX+RX Power (mW)

Target
Throughput (bps) 1. IEEE ISCAS, May 2000

100kps RX+TX = 1mW

Towards a Digital Radio
Conventional Integrated, Narrowband Transceiver:
ANALOG: LNA MIXER A/D F SYNTH D/A PA MIXER D/A A/D I Q DIGITAL:

A “Mostly Digital” Radio:
ANALOG: LNA A/D I DIGITAL: PA D/A

Signaling Approach
Sinusoidal, Narrowband

Time

Frequency

Impulse, Ultra-Wideband

Time

Frequency

Existing Ultra-Wideband
UWB Commonly Used for: Radar Extremely High Data-Rate Communications Usually Bulky, Power-Hungry, Expensive
• Can Require Very Accurate Clocking • High-Voltage/High-Power Pulse Generation • Low Levels of Integration

Recent Interest in UWB Technology:
• Low-Power Locationing (I.e. RF Tags) • Short-Distance, Broadband Communication (I.e. the “last mile”)

Research Proposal
Problem:
How to Design and Implement an UWB Transceiver for a HighlyIntegrated, Low-Power, Indoor, Network Radio Application?

Solution:
Establish a Framework to Evaluate Trade-offs Between System Performance and Implementation Issues by: • Investigating Nature of UWB Communications • Modeling and Exploring System Architecture Options • Identifying Low Power Design Techniques for CMOS Circuits

Presentation Outline
System Level Simulation for Link Budget Analysis Modeling the Channel Modeling Interference

Example Simulation vs. Measurement
Proposed Implementation Architecture Power Budget Preliminary Circuit Examination

Pulse-Based Communication
Consider the Pulse to be Periodic Pulse Train
Tpulse rep rate

Tsamp
Time

Tpulse

Use Discrete Fourier Transform to Model One Period
Sampling Rate Chosen for > 90% Energy

System Simulation Framework
Model Pulse Transmission Through Transceiver
Quantize

Signal Path

Gen Pulse

Channel Model

Gain

Low Pass

Noise Figure

Quantize

Noise/Interference Path

Interference Gen

Gain

Low Pass

• Allow System Parameter Exploration • Able to Use Measured and Ideal Values • Performs Link Budget Analysis

UWB Antennas
Critical Design Parameters:
• No Dispersion of Pulse • Wideband Impedance Match to Driver/Receiver • Omni-directional Radiation Pattern • Easily Integrated, 1GHz BW or Higher

Good Candidates:
• Large Current Radiator (But is not 2-Dimensional) • Spiral Antenna • Loaded Dipole

Lump Into Channel Model

Channel Measurements: 800MHz Stub
Stub Antenna:
+ Small Size + Omni-directional - Narrowband - Bad Phase

Spectrum Usage
Interferers:
TV: 174-216MHz, 470-806MHz
ISM: 902-928MHz, 2.4-2.4835GHz, 5.725-5.850GHz

Cell phone:824-849MHz, 870-893MHz
Pager: 929-930MHz PCS: 1.85-1.99GHz Microwave Oven: 2.45GHz

In-band Interference
Everyone is an in-band interferer… why aren’t we swamped?

Energy in Pulse is Concentrated in Time
Amplitude

If Equate Energies, Find Ratio of Amplitudes is:
Apulse 1/2  A sin DutyCycle
Time

For a duty cycle of 1%, this implies a pulse amplitude 7x an equivalent power sinusoid. Ex: -77dBm per MHz over 1GHz is a 40mV pulse (50W) !

Interference Mitigation
Additional Mitigation:
• Can Use Spreading Signal for Processing Gain • Position Pulse Nulls at Known Interference (I.e. Cell Phones) • Filter Out Low Frequency TV Channels, FM Radio • Some Noise Sources are Duty Cycled (I.e. TDMA Phones, Microwave Ovens)

Interferer (Jammer) Impact:
• Limits Gain Through Front-End (No Saturation) • Requires More Bits on A/D to Resolve Signal • Decreases Intrinsic SNR • Increases Need for Spreading (Decreases Data Rate)

Example: 800MHz Stub Simulation
800MHz Stub Antenna:
0.4V Edge /1.5ns 1m Propagation 60% of Energy in first 5ns SNR60% = 4.5dB W/ Spread of 32, 4-bit A/D, Gain=45dB, NF=10dB

SNR = 10dB BER ~ 1e-5

Time Domain Measurements
800MHz Stub Antenna:
Same Conditions: 1.5ns Edge 0.4V Swing 1m Distance See Roughly Same Amplitude and Pulse Length

Pulse Reception
Energy of Pulse is Contained in Small Time Window
Tsamp
Time

Twindow

Only Need Limited Amount of Fast Sampling
Use Parallel Sampling Blocks
Have Rest of Time in Cycle to Process Samples

Do Digital Correlation
Minimum of Analog Blocks Run at Speed

Proposed System Architecture
Based on Digital Sampling/Acquisition Oscilloscopes
MAC LNA VGA S/H A/D

S/H

A/D

Data Recovery

Synch Detect

S/H

A/D

CLK GEN

CONTROL

PULSE

Power Budget
Block Low Noise Amp Variable Gain Amp Sample/Hold Duty Cycle Twin/Trep Twin/Trep 100% Power (Always On) 600mW 1.8mW 1mW Power (Per Period) 60mW 180mW 1mW

A/D Converter
Oscillator Sampling Clock Gen TX: Pulse Generation Digital Logic

100%
100% 100% 2ns/Trep 100%

100mW
100mW 400mW 10mW 60mW

100mW
100mW 400mW 100mW 60mW = 1001mW

Total Power Per Period:

Pulse Generation
Desire low voltage (and hence easily integrated) approach:
Use H-Bridge Configuration to Switch +/- Current

Out+

Antenna

Out-

Issues:
Radiation Efficiency Peak Current Antenna DC Bias

E.g. Ipeak=8mA for 2ns/5MHz -- P=100mW (Vdd=1.2V)

Wideband LNA
Issues:
Low Noise, Wide Bandwidth for Low Bias Current Flat Gain vs. Frequency Input Matching to Antenna

Example:
Shunt-Shunt Feedback LNA (1.2V, 0.15mm Process)
M2 Vout Vin M1 M3

Gain = (gM1/gM2) > 26dB Total Ibias = 500mA Target System NF < 10dB

Clock Generation
Oscillator Requirements: (5MHz)
Drift (100 Chips/0.5ns Bin)  Crystal Accuracy (+/- 20ppm) Jitter (0.1ns)  Phase Noise (-100 dBc/Hz @ 100kHz)

Clock Generation:
Precise Delay: Tdelay Sampling Clock Spacing: Tsample OSC: Sample CLK: Tsample
Time

Tdelay

Sample/Hold
Would Like To Use Passive Sampling
• Tracking Bandwidth = 1GHz • Sources of Error: Clock Feed-through Channel Charge Thermal Noise Constrain Csample Relative To Switch Size: Csample = 70fF for < ½ LSB Error Then, Rds = 2kW for 1GHz Tracking Can Use a 1mm/0.3mm Switch (1.2V, 0.15mm Process)
Vin fCLK Vout Csample

A/D Conversion
Primary Issue: Low Power, Low Area
Rate (5MHz) and Width (4bits) Are Not Aggressive

Low-Power Approach:
Use Dynamic Comparators Integrate Into Sample/Hold No Interstage Amplifiers No Static Currents

VMSB

+

VMSB-1

+

Architecture: Flash
Issues: Area, Vref Generation, Comparator Offset

Vin VLSB

+

Power Est. = N*Csample*Vdd2 *fclk

Digital Backend
Order of Magnitude Power/Area Estimates
Multiply-Accumulate (12x 4bx4b MAC’s) Data Recovery (RX) (~ 4-bit MAC) Synch Detector (24 4-bit Thresh+Logic) PN Generator (32-bit Shift Reg/XOR) Data Spreading (TX) 0.252mm2
(13,967 INV)

150mW 0.6mW 5mW 0.2mW <0.1mW

0.004mm2
(222 INV)

0.049mm2
(2722 INV)

0.002mm2
(112 INV)

<0.001mm2
(<56 INV)

Total

0.308mm2
(16,722 INV)

156mW

STMicro CMOS Lib 0.25mm: 2V, 5MHz, pactivity=1/2

Expected Research Contributions
• System to Facilitate UWB Implementations • Low-Power, Wideband Circuit Design in CMOS

• Demonstrate Highly Integrated, UWB Radio for PicoRadio Project (Network of Sensors)
• Better Understand Trade-offs of UWB

Communication Compared to Conventional Narrowband Approach


				
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