From RTL to Silicon by chenboying



The Main Steps of Chip Design Primer and Introduction

Worksheets for students designing VLSI integrated circuits at the VLSI laboratory of the DED (V2-302) using the Mentor Graphics Design Environment on PC’s under LINUX Operating System.

dr. Peter Gärtner


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Introduction Itinerary Through the Design Detailed Design Guide 0. Overview of the module and file system 1. Prepare the work with the tools 2. Check the sinthesizability of the Verilog description 3. Preliminary synthesis without I/O pads 4. Pre-layout simulation with the Verilog simulator 5. Add pads to the design 6. Final synthesis 7. Final pre-layout simulation 8. Add power pads to the top-level Verilog netlist 9. Load the Verilog netlist into SE 10. Add corner cells to the design 11. Make a floorplan for the chip 12. Do pad-preplacement 13. Fill the padring 14. Create power-ring 15. Create power stripes 16. Complete the rows with cap-cells 17. Do placement 18. Fill the rows 19. Finish power routing 20. Do global and final routing 21. Verify geometry and connectivity 22. Write out netlist and timing data 23. Verify the design with post-layout simulation Appendix 1. File and information system of the tools 1.1. Default working directories 1.2. Envisia PKS 1.3. Silicon Ensemble 2. Chip structure of the 0,35 µm AMS technology 3. The views of the AMS cell library and their usage 4. Short Users’ Guide to the Artwork Window of SE 4.1. Switch boxes on the left 4.2. Display Options window 4.3. Colors of display 4.4. Selecting objects and viewing their properties 4.5. Environment variables
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3 4 5 5 5 6 7 9 9 10 12 12 13 13 13 14 15 16 16 18 19 19 19 20 21 22 24 25 25 25 25 25 25 27 29 29 29 30 31 31 2

It is true that the functionality of a chip is created in the logic design phase but the Verilog description is only software. Further on everything is directed towards giving it an optimal physical form while maintaining the functions. The majority of the activities are tiresome routine jobs, many of the steps can be done automatically. Yet they are important because without them the chip could not be manufactured. During the semester you have to design an ASIC chip for a given specification. First you have to complete the exciting and interesting logic design which results in an RTL level Verilog description. The brochure Verilog for Synthesis describes the way how to arrive at that objective. This brochure will take you through the second part of the design work. Even if this part mainly consists of routine activities, the synthesis as well as the placement and routing are also exciting and interesting, and they can get the designer sweating. Anyhow, they are also part of the tasks of the ASIC designer and, therefore, you have to learn and exercise it. Nowadays chip design can be subdivided into three main phases, each of which is closely connected to a design tool: 1. The Verilog phase. (Logic design) The idea and/or necessity gives rise to a specification which is then coded in a hardware description language (HDL), in our case Verilog, but it may also be VHDL, and is verified by simulation. The coding usually starts on a behavioural level and is partitioned and refined until arriving at the RTL (register transfer) level. These activities are covered in the brochure “Verilog for Synthesis”. The synthesis phase. It consists of two not sharply separated steps: a) conversion into a technology-independent generic gate-level netlist (“the synthesis”) and b) its mapping into the elements of a given technology which is intended for the realization of the chip. Both steps are performed under optimization constraints aiming at silicon area and/or time (propagation delay). The result is a netlist containing the cells of the target technology. Our synthesis tool is Envisia PKS (Physically Knowledgable Synthesis) which delivers a gate-level netlist. The netlist can (and has to) be verified by the Verilog simulator (pre-layout simulation) before starting the last phase, the physical (layout) design by placement and routing. The target technology is AMS 0,35µm, 3 metal layers. The layout phase. The cells of the target technology are described with different views. The synthesis has used the view containing the logic model and timing of the cells. Now it comes to the layout view or its simplified version, the graphic phantom. The graphic phantom describes only those parts of the layout which are relevant to the placement and routing, mainly the metalization. The netlist contains the component cells of the chip and their connections. Based upon this information:  a floorplan has to be estimated,  the cells have to be placed,  the connections have to be implemented (routing). Roughly speaking the layout design consists of these steps, which can be performed using the tool Silicon Encounter (SE). Eventually the post-layout simulation verifies and completes the design work.



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Itinerary Through the Design
The steps described in the 2nd and 3rd phases really cover the essential tasks of the design from RTL to the layout. However, the description is very much simplified. In order to give a good overview, a lot of “small chores” have not been mentioned at all. They belong to two main groups: creating auxiliary parts on the chip, mainly the power supply, without which the chip could not work, and preparing and establishing the background for the tools without which they could not work. Next a detailed list of these small chores is given, together with the “great steps”, possibly in the order of their execution. 1. Prepare the work with the tools: Verilog, PKS and SE. 2. Check the sinthesizability of the Verilog description. (Make a generic netlist.) 3. Preliminary synthesis without I/O pads. 4. Pre-layout simulation with the Verilog simulator (functionality check). 5. Add pads to the design. (Construct a top-level Verilog description with pads around the core.) 6. Final synthesis with pad-cells. 7. Final pre-layout simulation (timing check based upon the wire-load model). 8. Add power pads to the top-level Verilog netlist. 9. Load the Verilog netlist into SE. 10. Add corner cells to the design. 11. Make (estimate) a floorplan for the chip. 12. Do pad-preplacement: Have SE create a list of all pads, arrange them with the text editor and let SE execute the pad-preplacement accordingly. 13. Fill the padring by adding filler cells. 14. Create power-ring around the core. 15. Create power stripes for lowering the impedance of the power supply. 16. Complete the rows with cap-cells. 17. Do placement. 18. Fill the rows by adding filler cells. 19. Finish power routing  connect all cells to the power supply. 20. Do global and final routing and, if necessary, repair violations. 21. Verify geometry and connectivity. 22. Write out netlist and timing data. 23. Using the timing data verify the design with post-layout simulation.

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Detailed Design Guide
0. Overview of the module and file system. In the followings a detailed description of the design-steps, listed in the itinerary, will be given. Starting from RTL-Verilog they bring the design to “tape-out” of the layout. However, first you have to get a good overview of the Verilog files and modules which you will encounter during the design activities. So far you have a top RTL module projectxy and a test-bench tb_projectxy. The top module may contain instances of different sub-modules but they will not play any critical role. There are two main advices to follow: 1. Never have two files and two top-modules with the same name while stepping through the different stages of the design because it may cause very bad confusion. Both filename and top-module-name can be created using the underscore and a “stageidentifier”. 2. You should have only one separate file containing the test-bench module which calls the top module of your design. It contains the stimuli and they should be identical in each simulation run. Accordingly, you should adjust the name of the top module by means of a text editor in the different design stages. In step 3. you will get a preliminary syntesized netlist, rename the top module xy_preopt. In step 5. you will create a new top-level module which calls the core of the chip, xy_preopt, and the signal-pads. Give it the name xy_top. In step 7. you will get the final synthesized netlist, rename the top module xy_optimized. In step 8 you will add the power-pads to xy_optimized. Rename the new module xy_chip. 1. Prepare for working with the tools: Verilog, PKS and SE. In order to maintain clear overview we recommend the following data structure. Create a new subdirectory in your home directory referring to your project XY (mkdir projectxy). Then change to this subdirectory (cd projectxy) and execute the preparatory unix script. Type
source ~gaertner/chip/admin/initproject <CR>

This script performs the follwing tasks:  copies the setup file of SE se.ini into your home directory.  creates in projectxy three new subdirectories:  veri for Verilog,  synth for PKS and  se for SE.  copies the Verilog modules of the AMS library to veri for the simulation of the synthesized gate-level Verilog netlists:  csx_HRDLIB.v  csx_IOLIB_3M.v  udp.v  copies the tcl-script load_libs.tcl to synth which will load the cell library of the target technology into PKS.  creates in se the subdirectory DB (data base) for SE and copies the preprocessed cell library into it (LBRARY_TLF.*, 16 files, it takes 1-2 minutes).  creates in se the subdirectory cds_vbin for compiling the Verilog netlist.  copies the following auxiliary files to se:  cds.lib  path for Verilog modules of the cells of the target library,  corner.def  corner cells for the I/O-ring,  fillperi.mac  SE macroscript for closing the I/O-ring,  fillcore.mac  SE macroscript for filling up the rows of the cells,   Map-file for outputting GDSII format,  csd3.3V.gfc  Links to the timing libraries.
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You may have created many different files while developing your project. Now it is time to select those containing your Verilog description with all hierarchical modules, however, only those, without the test bench. Wherever they may stay, copy them to the previously created subdirectory synth for the synthesis. 2. Check the sinthesizability of the Verilog description. Start PKS: left double click at the sign PKS (blue cogwheel on the desktop). The start-up window opens and requests the working directory (only at the very first start). Type projectxy/synth<CR>. The PKS graphical user interface opens. It consists of a menu bar on the top, a command shell window on the bottom as well as two main window browsers in the middle with several tabs (Fig. 1. with the Commands roll-down menu). Left click File > Open. The Open a File window opens. Click on the box Tcl source script. Select in the browser the tcl-script load_libs.tcl and click OK (Fig. 2.). The script will be loaded and executed and a message will be written to the command shell window indicating that the ambit libraries csx_HRDLIB.alf and csx_IOLIB.alf have been read. They contain the complete cell library (function and timing) of the target technology AMS 0,35µm (csx) in PKS-format. Again left click on File –> Open in the main menu bar. In the Open a File browser window activate the switchbox Verilog. A list of your Verilog files will appear in the browser pane.

Fig. 1. The main window of PKS.

Fig. 2. Opening load_libs.tcl. Select each one by clicking on it. The selected files will be listed in the box underneath. (They have to contain all the modules of your project, not less and not more.) A click on OK starts the reading (Fig. 3.). Its result will be reported in the command shell pane. It is mainly at this step that PKS sends warnings (orange) or error messages (red) if it encounters problems with the Verilog description.
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Fig. 3. Open Verilog file(s) If you happen to correct some Verilog file(s) then you can start a new synthesis process by clicking File > NEW. Then after clicking OK you have to load again all your Verilog files (but the cell library remains loaded). Now you have arrived at the most important step of the synthesis: converting the behavioural (RTL) description to a (generic) netlist. Left click in the main menu bar on Commands –> Build Generic (Fig. 4.). An option window pops up. Don’t change the defaults and click OK. PKS starts processing the modules, one by one. This activity is documented in the command shell but the same text is also stored in the log-file ac_shell.log. Error and warning messages may also appear. Whenever it appears, ignore the error message “Cannot find symbol library csx_IOLIB_3M.sym”.

Fig. 4. Build generic netlist. At the end PKS displays the hierarchy of the modules in the Modules pane on the left-hand side. If, for some Verilog constructs of your description, PKS takes an instance of a functional block (e.g. an adder) from the Ambit library, – as it is the typical case –, then it also appears in the hierarchical list. Before optimization you may have a look at the structure of the synthesized generic network. Select the top module to be inspected (or any other one) by a left double click on its name. The header of the right-hand pane changes to the Schematic tab and in the pane the synthesized module will be displayed (Fig. 5. next page). The menu bar of the Schematic pane offers possibilities for zooming and navigating in the hierarchy. Unfortunately, the schematic drawing program of PKS has a bug, so the schematic diagram on the screen is often faulty, even if the circuit is synthesized correctly. 3. Preliminary synthesis without I/O pads. This is the point where timing constraints could be given. At this stage, however, it can be left to the final synthesis with pads (section 6.). Left click Commands –> Set Target Technology. In the pop-up window set csx_HRDLIB for the target technology (if it is not the default) and click OK.
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Fig. 5. Generic schematic. The selected element is highlighted. Select the top module in the left pane. Right click on the highlighted (light blue) top module. A pop-up menu comes up. Left click on Set Current Module. Repeat the process for Set Top Timing Module. (These steps may be omitted if you see the report in the command shell window that they have already been made automatically.) Left click Commands –> Optimize. The Optimize window pops up (Fig. 6.). Switch the Priority to Area then click OK.

Fig. 6. Settings for optimization. (This window has been changed in the new version.) Now PKS starts mapping the generic netlist to the cells of HRDLIB and tries to optimize for chip area. Meanwhile lots of messages appear in the command shell window. The error message “Symbol library cannot be found” can be ignored. If no serious error has been encountered then the hierarchy list and the schematic in the central windows will be changed for the optimized network, you may inspect it. The process is documented in ac_shell.log If there are no errors then the preliminary synthesized gate level netlist has to be stored. In the command shell window type: 18.03.2007. PG. 8

write_verilog –hier projectxy_preopt.v

This file will be written either to your working directory synth or your home directory. The only question remains if it produces the same simulation results as the original RTL description did. 4. Pre-layout simulation with the Verilog simulator. Copy the synthesized netlist to the Verilog directory veri. Add a timescale statement to it because PKS doesn’t provide it and on gate-level it is needed (‘timescale 1ns/100ps). Add “_preopt” to the top modul name so that it can clearly be distinguished from the top module of your RTL description. Also copy the test-bench to this directory and modify it so that it calls the synthesized “preopt” module. The library modules are already prepared (copied) here. When starting the Verilog simulation they have to be compiled and elaborated together with the gate-level Verilog netlist, because they contain the Verilog modules for the AMS library cells which form the synthesized netlist. Check carefully if the netlist produces the same results as the previous simulation on RTL level. (Whether the synthesis has not changed the functionality. Special attention has to be payed to the beginning and to the ending of counting activities, if they take place in the expected clock cycle.). 5. Add pads to the design. The core of the would-be chip is ready, its synthesizability has been checked. This module will form the main part of the highest-level module describing the whole chip. The top-level module must have a different name from the core. For this purpose add _top to it. Beside the core it contains the I/O-pads. In order to use the same test-bench, the top-level module shall have I/O pins with the same name as the core module does. Therefore, the core module has to be instantiated in the top-level module with slightly different pinnames, e.g. with a postfix _c added. This will indicate that they are the same signals, but inside the padring, in the core. The pads, establishing the connection between the outside world and the core, each one will have an input and an output pin with the same name, however, one of them will be distinguished by the postfix _c at the core-side. There are no generic pad-modules in Verilog. The pad-cells of the chosen technology (AMS 0.35µm) have to be added. They are ICP for the inputs and BU1P for the outputs. The instance name of the pads should refer to their signal but they must not be identical. The simplest way to create meaningful pad-names is to add p to the signal name for single variables and p0, p1, p2, etc. for buses. A simple example follows for the core module myproject(aa, bb, cc, jj, kk, ll). Only the top module is shown. Notice the different position of the _c postfix at the input and output pads. (Pads for the power supply will be built in only after synthesis.)
module myproject_top(aa, bb, cc, jj, kk, ll); input aa, bb; input [1:0] cc; output jj, kk; output [1:0] ll; wire aa, bb; wire [1:0] cc; wire jj, kk; wire [1:0] ll; // // wires from the core to the pads: // wire aa_c, bb_c; wire [1:0] cc_c; wire jj_c, kk_c; wire [1:0] ll_c; // // the core is instatiated: // myproject c(aa_c, bb_c, cc_c, jj_c, kk_c, ll_c);
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// // input pads (based upon module ICP(PAD, core);) // ICP aap(aa, aa_c); ICP bbp(bb, bb_c); ICP ccp0(cc[0], cc_c[0]); ICP ccp1(cc[1], cc_c[1]); // // output pads (based upon module BU1P(core, PAD);) // BU1P jjp(jj_c, jj); BU1P kkp(kk_c, kk); BU1P llp0(ll_c[0], ll[0]); BU1P llp1(ll_c[1], ll[1]); endmodule

When constructing the description by means of a text editor be careful about what to add and where, and check it afterwards! The last step is to place a timescale statement into the first line of the file. Now you can modify the testbanch so that it calls the projectxy_top module and check the correctness by simulation. 6. Final synthesis. These steps are identical with those for the core as described in sections 2. and 3, but applied for the top-level module. However, with the exception of very low clock frequencies (a couple of MHz or lower), the timing behaviour, too, has to be verified. For this purpose the mapping and optimization (see section 3.) has to be extended to timing as well. Before giving the optimizing click define an ideal clock. Left click on the tab Constraints – the constraints browser will be displayed (Fig. 7.). Right click on the left part of the Constraints tab window and select New Ideal Clock. The New Ideal Clock window pops up. Enter master in the name field and the specified clock period (nsec-s) in the other one, then click OK. Click on the number under Period and enter the period again. Click on the number under Trail Time and enter half of the period (Fig. 7. already shows it). Bind the clock port to the ideal clock. Right click in the right half of the Constraints window under the Clock Pin and select New Port Clock. The New Port Clock window opens. Set master as the Ideal clock and the clock pin of your chip as Port clock (Fig. 8, next page). Enter 0.2 (nsec) as Early rise time and <half clock period + 0.2 (nsec)> as Early fall time, then click OK.

Fig. 7. Constraints window – set ideal clock.
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Fig. 8. New port clock window Check the worst path delay. Click on the Schematic tab on the center-right window. The generic schematic appears again. Use the right mouse button to bring up the menu. Select Worst Path. The worst path of the network appears highlighted (Fig. 9.).

Fig. 9. Checking the worst path. Now you can go and set the target technology as described in section 3. and afterwards set the operating parameter. Left click Commands –> Set Operating Parameters (see Fig. 4.). The Set Operating Parameters window pops up with tipical default values: Voltage=3.3, Process=1.0, Temperature=25.0. They can be left so or modified upon special need. Here you can start the optimization and, when it is finished, you can check the worst path delay just as you did it with the generic network. Again, if there are no errors then the final synthesized gate level netlist and its calculated
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delays have to be stored. Type in the command shell window:
write_verilog –hier projectxy_optimized.v write_sdf –delimiter . –precision 4 projectxy.sdf

In the Verilog file modify the module-name from projectxy_top to projectxy_optimized and add a timescale statement. Accordingly, in the .sdf file also modify the module name to projectxy_optimized. Now copy these two files to your Verilog directory veri for the final prelayout simulation. 7. Final pre-layout simulation. Basically, it is done as described in section 4. with one difference. Here you have to add the timing data contained in projectxy.sdf in order to get realistic timing behaviour (based upon the wire-load model). First add an initial statement to the testbench so that it be the very first initial statement in the module:
projectxy_optimized top(inputs, outputs, etc. . . .); initial $sdf_annotate("projectxy.sdf", top);

(Here it is supposed, that the instance name of the top-level module in the testbench is just top.) The compilation is done as usually. When it comes to the elaboration: Select Tools Elaborator and click on the Advanced Options button (Fig. 10.). The Elaborator Advanced Options window appears. Here select the Verilog Perfomance tab, and click on the checkbox Delay Modes and select path mode. Then select the Programming Language Interface (PLI) tab, and switch on Enable delay annotation at simulation time. Select Annotation, switch on Specify delay types and select Maximum mode. In the Verilog only group switch on, too, Use worst case rounding for SDF. Now you can go on with the simulation as usually. Check carefully if the backannotated netlist produces the same results as the previous simulations.

Fig. 10. Elaborator window and its advanced options. Should NCverilog send a message that projectxy.sdf cannot be found then check the blue titlebar at the top of the NC-Verilog window, because NC-Verilog is searching for projectxy.sdf at that directory. Should it be not there, copy it to that place and try again. 8. Add power pads to the top-level Verilog netlist. Having no logic function, PKS ignores the power pads. Therefore, they can be added only after the synthesis. Copy your top-level file projectxy_optimized.v from synth to se and change its name to projectxy_chip.v. Then open it with the text editor. Depending upon how many power pads are needed, the following statements have to be inserted into the Verilog netlist:
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gnd1(); gnd2(); ... vdd1(); vdd2(); ...

9. Load the Verilog netlist into SE. COMING SOON!

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