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SHARC Processor Overview

             David Miller
         SHARC Applications
         Engineering Manager

•   Target Markets
•   SHARC Processor advantages
•   Family Summary
•   SHARC Hardware Overview
•   I/O Processor
•   Direct Memory Access
•   SHARC Peripherals
•   Additional Support
•   Resources
Analog Devices SHARC Processor Family
SHARC: Floating-Point Processor

         Performance             Partners            Operating          High Integration
         2.4 GFLOPS                                 Temperature         RAM, SPORTs,
                                                     Ambient:            SRC, UARTs

                Wide range of floating-point processors from $5 to $25

                             Close collaboration with partners

                       High integration enables single-chip solutions
 Target Markets

       Digital Home                                 Pro-Audio
Established leadership market                 Established leadership market
position in digital home                      position in pro-audio
• Advanced TVs                                 • Mixers
• High definition DVD                          • Amplifiers
• Home theater systems                         • Synthesizers

       Industrial                                   Automotive
       and Instrumentation
Established leadership market position in     Established leadership market position
industrial and instrumentation applications   among first-tier automotive suppliers
• Medical                                      • Audio amplifiers
• Test and measurement
SHARC Features

•   High performance 32-bit/40-bit floating-point operations
•   High performance 32-bit fixed-point operations
•   Up to 400 MHz (2.5 ns) core instruction rate
      •   Performs 2400 MFLOPS/800 MMACS
•   Single-Instruction Multiple-Data (SIMD) computational architecture provides:
      •   Two computational units
      •   Concurrent code execution
      •   Single-cycle execution of a dual multiply or dual ALU operation
      •   A dual-memory read or write, and an instruction fetch
      •   Transfers data between core and memory at a sustained 5.4 Gbyte/s bandwidth
•   Floating-point advantages of SHARC
      •   Reduces quantization errors due to number representation
            •   Floating-point has less quantization noise than fixed-point
      •   Better precision
      •   Higher dynamic range
Common and Market-Specific Advantages of SHARC Features

           •   32-bit floating-point
           •   Large on-chip memory
           •   Glueless I/F to external memory

           •   Audio decoders in ROM                     Special
           •   Sample rate converters (HW)       Advantages in Consumer
           •   S/PDIF Rx/Tx (HW)                     and Automotive

           •   DTCP cipher engine (HW)                 Specific
           •   105oC ambient operating temp            Features
Floating-Point Product Portfolio


       ADSP-21161                 ADSP-21262/21266   ADSP-21362–21366                  ADSP-21367–21369
       • 0.6 GFLOPS               • 1.2 GFLOPS       • 2 GFLOPS                        • 2.4 GFLOPS
                                                     • Audio processing acceleration   • Optimized for system
                                                                                         and performance cost

        Low Cost

        ADSP-21065L                ADSP-21261                                          ADSP-21371/21375
        • 0.37 GFLOPS              • 0.9 GFLOPS                                        • 1.6 GFLOPS
SHARC Family Summary

   Key Features           ADSP-    ADSP-   ADSP-   ADSP-     ADSP-   ADSP-   ADSP-   ADSP-   ADSP-   ADSP-   ADSP-   ADSP-   ADSP-   ADSP-
                          21161    21261   21262   21266     21362   21363   21364   21365   21366   21367   21368   21369   21371   21375

  RAM/ROM (Mbits)          0/1      1/3     2/4      2/4      3/4     3/4     3/4     3/4     3/4     2/6     2/6     2/6     1/4    0.5/2

   Max Frequency           110      150     200    150/200    333     333     333     333     333     400     400     400     266     266

Core Voltage (3.3v I/O)    1.8      1.2     1.2      1.2      1.2     1.2     1.2     1.2     1.2     1.3     1.3     1.3     1.2     1.2

 MP/Shared Memory          Yes      No      No       No       No      No      No      No      No      No      Yes     No      No      No

  SDRAM Controller         x32      No      No       No       No      No      No      No      No      x32     x32     x32     x32     x16

       SPORTs               4        4       6        6        6       6       6       6       6       8       8       8       8       4

      Link Ports            2       No      No       No       No      No      No      No      No      No      No      No      No      No

         SPI                1        1       1        1        2       2       2       2       2       2       2       2       2       2

Audio Decoders in ROM      No       No      No      Yes       No      No      No      Yes     Yes     Yes     No      No      No      No

        UART               No       No      No       No       No      No      No      No      No       2       2       2       1       1

        DTCP               N/A      N/A     N/A      N/A      Yes     No      No      Yes     No      No      No      No      No      No

        S/PDIF             No       No      No       No       Yes     No      Yes     Yes     Yes     Yes     Yes     Yes     Yes     No

SRC Performance (dB)       N/A      N/A     N/A      N/A      128     No      140     128     128     128     140     128     No      No

     BGA (Balls)           225      136     136     136       136     136     136     136     136     256     256     256     No      No

                                                                                                      208             208     208     208
     LQFP (leads)          N/A      144     144     144       144     144     144     144     144    200M     N/A    200M    200MH   200MH
                                                                                                      Hz              Hz       z       z

                          0°C to
Temp Grades (Ambient)     +85°C
                                    CI      CI       CI
    C = 0°C to +70°C        and
                                   (BGA    (BGA     (BGA     CIA     CIA     CIA     CIA     CIA      CI      CI      CI      CI      CI
   I = -40°C to +85°C      -40°C
                                   only)   only)    only)
  A = -40°C to +105°C*       to
Low-pin-count devices with SRAM interface

Features                      ADSP‐21261         ADSP‐21262               ADSP‐21364               ADSP‐21366

Pipeline stages                   3                   3                        5                        5

Frequency – MHz (max)            150                 200                      333                      333

Audio Decoders in ROM             No                 No                       No                       Yes

On‐Chip RAM – Mbits               1                   2                        3                        3

Serial Ports                      6                   6                        6                        6

External Memory Interface     SRAM, Flash       SRAM, Flash               SRAM, Flash             SRAM, Flash

mBGA – Balls                     136                 136                      136                      136

LQFP EPad – Leads                144                 144                      144                      144

Temperature Grades            Commercial    Commercial, Industrial   Commercial, Industrial   Commercial, Industrial
With SDRAM support

            Key Features     ADSP-21367   ADSP-21369   ADSP-21375     ADSP-21371

     Max Frequency MHz          400          400          266             266

     RAM – Mbits                 2            2           0.5              1

     SDRAM Clk MHz              166          166          133             133

     SDRAM Bus Width             32           32           16             32

     UART                       Yes          Yes          Yes             Yes

     TWI                        Yes          Yes          Yes             Yes

     Serial Ports                8            8            4               8

     Audio Decoders in ROM      Yes          No           No          Coefficients

     SBGA – Balls               256          256          No              No

     EP_LQFP – Leads            208          208          208             208

     Production                 Now          Now          Now            Now

                                                                    Pin Compatible

                                                                    Pin Compatible
SHARC Hardware Overview
ADSP-21369 Architecture Block Diagram

                   DAG 1              DAG 2                     PROGRAM
                  8 x 4 x 32        8 x 4 x 32                 SEQUENCER

                                             PMA BUS      32
                                          DMA BUS 32
                                   PMD BUS       64

                    BUS CONNECT

                                             DMD BUS 64

     Processing Element X                                                               Processing Element Y

                               REGISTER                                      REGISTER
                                 FILE       MULTIPLIER/                        FILE
             BARREL                                            MULTIPLIER/                 BARREL
     ALU                                       MAC                                                      ALU
             SHIFTER                                              MAC                      SHIFTER
ADSP-21369 Architecture Block Diagram
Integrated RAM and ROM

•   On-chip RAM
    •   Same speed as core                           Product      RAM (Mbits)   ROM (Mbits)

    •   Zero wait states for code/data access        ADSP-21362       3              4

    •   Improves performance over external memory    ADSP-21363       3              4
    •   Predictable performance                      ADSP-21364       3              4
    •   RAM blocks are partitioned to allow
                                                     ADSP-21365       3              4
        simultaneous access to RAM by core and DMA
                                                     ADSP-21366       3              4
•   On-chip ROM
    •   Enables security mechanism that disallows    ADSP-21367       2              6
        access to ROM code                           ADSP-21368       2              6
    •   Audio decoders are available in ROM on       ADSP-21369       2              6
        selected SHARCs
                                                     ADSP-21375       0.5       2 (optional)
    •   ADI enables customer code to be programmed
        into ROM (mask programmable)                 ADSP-21371       1         4 (optional)
         •   Minimum quantity and NRE requirements
External Memory Interface in SHARCs

Product                                        SDRAM                           SRAM                       Parallel Flash





•   SHARC processors allow glueless connection to external memory
      •   SDRAMs
            •   Supports SDRAMs of 64 Mbits, 128 Mbits, 256 Mbits, and 512 Mbits with configurations x4, x8, x16
            •   16/32 bits wide
            •   Up to 166 MHz SDCLK frequency
            •   Up to four processors can share memory (ADSP-21368)
      •   Parallel flash memories
            •   8/16 bits wide
            •   Asynchronous interface
            •   SHARC processors can be booted from flash device
      •   SRAMs
            •   8/16 bits wide
            •   Asynchronous interface
Enhanced SHARC Instruction Cache (ADSP-21371 and ADSP-21375)

          32-Bit x 48-Bit

            Sequencer                                          External Port
                                                                                    SDRAM             Data
                                    PM Address Bus                                  Controller

                                    DM Address Bus                                                  Control

                                       PM Data Bus
                                                                                     Memory         Address
                                       DM Data Bus                                  Interface

•   32-entry two-way set associative cache
      •   Acts as instruction cache when program sequencer executes instructions from external memory
      •   Acts as traditional conflict cache when sequencer executes instructions located in internal memory
•   Context switching happens automatically without user intervention
•   During instruction execution from cache, external port is freed up
I/O Processor
ADSP-21369 Architecture Block Diagram
I/O Processor Features

•   The I/O processor supports I/O for the SHARC
      •   Communicates between external world and the SHARC’s core and on-chip memory
•   DMA controller with up to 34 DMA channels
      •   16 for SPORTs, four for UARTs, two for SPIs, two for external ports, two for memory to memory,
          eight for input data ports
•   The Digital Audio Interface (DAI)
      •   SPORTs, clock generators, sample rate converters, S/PDIF, input data port
      •   Signal Routing Unit 1 (SRU1) supports software-configurable interconnects to peripherals
          and DAI pins
      •   20 software-configurable DAI pins
      •   The DAI has an interrupt controller, supports up to 32 interrupt requests
•   The Digital Peripheral Interface (DPI)
      •   UARTs, SPI, Two Wire Interface (TWI), timers
      •   Signal Routing Unit 2 (SRU2) supports software-configurable interconnects to peripherals
          and DPI pins
      •   14 software-configurable DPI pins
      •   The DPI has an interrupt controller, supports up to 32 interrupt requests
Advantages of SRU/DAI/DPI

•   Most designs leave pins:
      •   Unused
      •   Connected in parallel
      •   Tied low
      •   Tied high
•   More pins = more die area = higher cost
      •   Why pay for a pin if you are just going to tie it to ground?
      •   As on-chip peripherals increase there is less need to route their I/O off-chip
          (more compact, better signal integrity, etc.)
      •   Software-assigned pins provide new functionality
•   Only use the specific pins that you need at any moment
      •   Many pins are multiplexed
      •   Pins may be used for unrelated functions at different times
Direct Memory Access (DMA)
ADSP-21369 Architecture Block Diagram
Direct Memory Access (DMA)

•   Allows for zero-overhead background transfers at full clock rate without processor
      •   Both code and data can be transferred through DMA
      •   DMA transfers occur at 532 Mbytes/s*
      •   Relieves the core processor from the task of moving data from peripherals to
          internal memory
            •   Supports memory to memory DMA
      •   External bus packing to 8-bit, 16-bit, 32-bit, 40-bit, 48-bit automatically performed during DMA
•   Control of DMA and I/O processing through memory-mapped IOP registers
    accessible by core

      *Assuming 333 MHz core clock and 133 MHz
DMA Features

•   DMA transfers are configured and initiated by the SHARC core processor
•   34 DMA channels on ADSP-2136x, 32 DMA channels on ADSP-2137x
•   DMA can be paused and restarted; different peripherals support different flavors
    of DMA, such as circular buffering, chaining, etc.
•   DMA can compete with core for internal memory access—conflict minimized
    by strategic placement of code and data in separate memory banks
SHARC Peripherals
ADSP-21369 Architecture Block Diagram
SHARC Synchronous Serial Ports (SPORTs)

•   Designed to be an extremely flexible serial interface to the
    SHARC processor
      •   Supports interfacing to several types of serial devices and SHARC to SHARC communications
•   Supports interfacing to devices with a 3- to 32-bit serial word length
•   SPORTs have several modes of operation, each with several programmable
•   The SPORTs support Time Division Multiplexed data
      •   Up to 128 channels of up to 32-bit serial data

•   Operates up to 1/8 of the processor core clock
•   Supports full duplex
•   Each SPORT has four signals
      •   SCLK, frame sync, data A, data B
•   Each can be independently configured for one of four modes
      •   Normal SPORT mode
      •   Multichannel TDM mode (128 channels per frame)
      •   I2S mode (24 I2S channels)
      •   Left-justified sample pair mode
•   SPORT programmable parameters
      •   Data transfers from 3 to 32 bits in length
            •   Either MSB or LSB first
      •   Internal or external source for clock and frame sync
      •   Early frame sync
      •   Late frame sync
      •   No frame sync
      •   TDM (Time Division Multiplexed) multichannel mode (1 to 128 channels)
      •   Data direction for A and B channels is programmable as transmitter or receiver
SPORTs Configuration

•   Signal routing unit allows for multiple SPORTs to be arbitrarily combined to run
    off as little as one SCLK and frame sync source
•   SPORTs can be configured for a number of different input and output options
•   Data signals are configured through software as inputs or outputs
      •   Enables many input/output combinations
            •   12 channels out
            •   2 channels in and 10 out
            •   4 channels in and 8 out
            •   6 channels in and 6 out
            •   The inverse of the above four options
Industry Standard Serial Interfaces

•   Serial Peripheral Interface (SPI)
      •   4-wire serial interface (developed by Motorola) that enables the SHARC processor to communicate
          with other SPI-compatible devices
      •   The SPI port features
            •   Full duplex operation, Master and slave mode, Multimaster mode, Open drain outputs, Word widths 8, 16, or 32
                bits, Programmable baud rates, clock polarities and phases, Master or slave booting from a master SPI device
•   UART
      •   Industrial standard 16450 compliant
      •   Two independant UARTs
      •   Supports half-duplex IrDA SIR (9.6/115.2 Kbps rate)
•   Two Wire Interface (TWI)
      •   Fully compliant to the Philips I2C bus protocol
      •   Supports master and slave operation
      •   SCCB (Serial Camera Control Bus) support in master mode only
•   S/PDIF-compatible digital audio receiver/transmitter
      •   EIAJ CP-340 (CP-1201), IEC-958, AES/EBU standards
      •   Left or right justified, I2S, serial data input with 16-, 18-, 20- or 24-bit word widths (transmitter)
Sample Rate Converters

• 4 independent asynchronous stereo sample rate converters (SRC).
• Each converter supports
    •   The SRC block is used to perform synchronous or asynchronous sample rate conversion across
        independent stereo channels, without using internal processor resources
    •   Provides up to 128 dB SNR
    •   Separate serial input and output ports
    •   A de-emphasis filter providing up to –140 dB SNR performance
    •   Left or right justified, I2S, TDM, data modes
    •   Data word lengths of 24-, 20-,18-, and 16 bits
    •   The four SRC blocks can also be configured to operate together to convert multichannel audio data
        without phase mismatches
    •   The SRC can be used to clean up audio data from jittery clock sources such as the S/PDIF receiver.
Precision Clock Generators

• 4 independent Precision Clock Generators (PCG)
• Each PCG generates a clock and frame sync signal
• The PCG’s output can be routed to on chip peripherals or off chip via the SRU
Timers and PWM module

•   Up to 4 timers
      •   One core timer
      •   3 General Purpose timers
•   Core timer
      •   Counts core clock cycles and generates an interrupt when count expires
•   3 General Purpose Timers
      •   Counts at the IOP clock rate
      •   Independent of one another
      •   Generate periodic interrupts
      •   Pulse waveform generation mode
      •   Pulse width count/capture mode
      •   External event watchdog mode
•   PWM Module
      •   The PWM module has four groups of four PWM outputs each.
      •   Each PWM group produces two pairs of PWM signals on the four PWM outputs
      •   The PWM generator can generate either center-aligned or edge-aligned PWM waveforms.
      •   In addition, it can generate complementary signals on two outputs in paired mode or independent
          signals in nonpaired mode (applicable to a single group of four PWM waveforms).
ADSP-21369 Architecture Block Diagram
CROSSCORE®, Analog Devices development tools product line, provides easier and
more robust methods for engineers to develop and optimize systems by shortening
product development cycles for faster time to market.

CROSSCORE includes:
  •   VisualDSP++® integrated development
      and debugging environment
  •   Emulators
           •   USB
  •   Evaluation boards
           •   EZ-KIT Lite® evaluation kits (expandable)
  •   Daughter board
           •   EZ-Extender®
VisualDSP++ Features

•   Connectionless IDDE
•   Session Wizard
•   Automatic Breakpoints
•   Code Generation Tools
         •   C/C++ Compiler, C/C++ Run-Time Library, DSP & Math
             Libraries, Assembler, Linker, Loader & Splitter
•   Compiled Simulation
•   Compiler Annotations
•   Profile Guided Optimization
•   VisualDSP++ RTOS/Kernel/Scheduler (VDK)
•   Background Telemetry Channel Support
•   Statistical Profiling and Graphical Plotting
•   Expert Linker
•   Cache and Pipeline Viewer Multiple Processor (MP)
    Support, Multi-Project Support
•   Royalty-Free Run-Time Libraries
•   Automation API
•   COM Automation-Aware Scripting
•   Integrated Source Code Control
•   Online Help
•   System Builder
•   Start-up Code Wizard
•   Ethernet Support
•   Image Viewer
•   Loader Compression
•   Energy-Aware Programming
•   And many more…..
           EZ-KIT Lite
           • EZ-KIT Lite provides developers with an easy            EZ-KIT Lite
            and cost-effective method for initial evaluation         •   ADSP-21375 EZ-KIT Lite
            of an ADI processor or DSP                               •   ADSP-21369 EZ-KIT Lite
           • Includes a DSP desktop evaluation board and             •   ADSP-21364 EZ-KIT Lite
            evaluation version of VisualDSP++                        •   ADSP-21262 EZ-KIT Lite

           • Capability can be expanded by adding an EZ-
            Extender® daughter board

           EZ-Extender                                               EZ-Extender
                                                                     •   SHARC EZ-Extender
           • EZ-Extender daughter boards give developers
                                                                     •   SHARC USB EZ-Extender
            access to and ability to connect to various
            peripherals from Analog Devices and third parties
            via the expansion interface of the EZ-KIT Lite
            evaluation kits

                                                                     USB Emulators
           USB Emulators
                                                                     •   USB Emulator
           • Provide nonintrusive target-based debugging
                                                                     •   HP-USB Emulator
             of processor systems
           • Wide range of functions including single-step
             and full-speed execution with pre-defined
             breakpoints, viewing, and/or altering of register and
             memory contents
    Additional Support
Third Parties and Software
SHARC Third Parties
•   AeVee Labs is a full-service electronics engineering firm specializing in audio, video, telecommunications,
    digital signal processing, and more. We provide the expertise to produce advanced, reliable products and a
    reputation for high performance that can improve market acceptance of your new product.

•   Danville Signal Processing develops and manufactures products based on Analog Devices DSPs for the
    audio, military, communications, and instrumentation markets, leveraging our expertise in DSP technology
    to provide state-of-the-art solutions worldwide.

•   DSP Concepts works with product developers and delivers customized embedded audio processing
    libraries found in consumer, automotive, and professional audio products. We also work with audio IP
    developers to optimize, port, and commercialize their algorithms.

•   Kaztek Systems provides worldwide training, HW/SW development support, and rapid prototyping design
    service using DSM (DSP Subsystem Modules) servicing the automotive, robotics, defense, industrial, and
    energy markets.

•   Mathworks Embedded IDE Link™ VS connects MATLAB® and Simulink® with the VisualDSP++ integrated
    development and debugging environment (IDDE) from Analog Devices. Embedded IDE Link VS software
    lets you debug and verify embedded code running on Analog Devices processors using MATLAB scripts
    and Simulink models. You can create test benches in MATLAB and Simulink to verify handwritten or
    automatically generated embedded code.
Extensive Audio Algorithm Library

 •   Licensed Algorithms:
      •   Dolby®                                    • ADI      library algorithms:
           •   AC3, DPL2x, EX, DVS, DH
                                                      •   Post-processing algorithms
                                                           •   Filters (EQ, tone control, cross-over)
                                                           •   Loudness
                                                           •   Dynamics processing
           •   Audistry              (in design)
                                                           •   Delay-management
      •   Digital Theater Systems                          •   Mixers/clickless volume control
                                                           •   Tone/noise generators
           •   DTS®5.1, 6.1,96/24, DTS-HD, Neo:6™
                                                      •   Bass enhancement algorithms
      •   SRS Algorithms                              •   Special algorithms
                                                           •   Automatic room EQ
           •              (test phase)                     •   Midnight mode
                                                           •   Reverb
           •   SRS WOW HD                                  •   Automatic volume control (AVC)
                                                      •   Spatializers/Virtualizer/Surround
      •   Waves Algorithms
                                                           •   Phat Stereo
           •   MaxxBass
                                                           •   ADI Surround
      •   BBE                                              •   ADI Virtual
                                                      •   Signal Display
      •   Audyssey                                         •   Spectrum analyzer
                                                           •   VU meter

•   Target Markets – SHARC is suited to a variety of applications
•   SHARC Processor advantages – peripherals, memory and performance
•   Family Summary – Large set of family members
•   SHARC Hardware Overview – SIMD architecture with dual comp units
•   I/O Processor – SRU, DAI, DPI
•   Direct Memory Access – Up to 34 channels of DMA
•   SHARC Peripherals – Serial interfaces, SRC’s, SPORTs, PCGs, GPIO
•   Additional Support – Tools and 3rd Parties
For More Information

•   Analog Devices website which has links to white papers, application notes, manuals,
    data sheets, FAQs, Knowledge Base, sample code, development tools and much

•   Take a 90-day Test Drive of VisualDSP++ for SHARC processors:

•   Multi-Day Workshops: In-depth technical training designed to develop a strong
    working knowledge of embedded processors and development tools through lecture
    and hands-on exercises.

•   For specific questions click on the “Ask a question” button.

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