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					“Tour of the Black Holes of Computing!”

CS 105

Virtual Memory

Topics
  

Motivations for VM Address translation Accelerating translation with TLBs

What Is Virtual Memory?
If you think it’s there, and it’s there…it’s real. If you think it’s not there, and it’s there…it’s transparent. If you think it’s there, and it’s not there…it’s imaginary. If you think it’s not there, and it’s not there…it’s nonexistent.

Virtual memory is imaginary memory: it gives you the illusion of a memory arrangement that’s not physically there.
–2– CS 105

Motivations for Virtual Memory
Use physical DRAM as cache for the disk
 

Address space of a process can exceed physical memory size Sum of address spaces of multiple processes can exceed physical memory (more common modern case)

Simplify memory management


Multiple processes resident in main memory
 Each with its own address space



Only ―active‖ code and data is actually in memory
 Allocate more memory to process as needed

Provide protection


One process can’t interfere with another
 Because they operate in different address spaces


–3–

User process cannot access privileged information
 Different sections of address spaces have different permissions
CS 105

Motivation #1: DRAM as ―Cache‖ for Disk
Full address space is quite large:
 

32-bit addresses: ~4,000,000,000 (4 billion) bytes 64-bit addresses: ~16,000,000,000,000,000,000 (16 quintillion) bytes

Disk storage is ~250X cheaper than DRAM storage
 

1 TB of DRAM: ~ $28,000 (667 MHz, late 2008 prices) 1 TB of disk: ~ $115

To get cost-effective access to large amounts of data, bulk of data must be stored on disk
4GB: ~$56 2 MB: ~$150 SRAM
–4–

1 TB: ~$115

DRAM

Disk
CS 105

Levels in Memory Hierarchy
cache virtual memory

CPU regs

8B

C a c h e

32 B

Memory

4 KB

disk

Register size: speed: $/Mbyte: line size: 32 B 0.3 ns 4B

Cache 32 KB-4MB 2 ns? $75/MB 32 B

Memory 4096 MB 7.5 ns $0.014/MB 4 KB

Disk Memory 1 TB 8 ms $0.00012/MB

larger, slower, cheaper

–5–

CS 105

DRAM vs. SRAM as a ―Cache‖
DRAM vs. disk is more extreme than SRAM vs. DRAM


Access latencies:
 DRAM ~10X slower than SRAM  Disk ~100,000X slower than DRAM



Importance of exploiting spatial locality:
 First byte is ~100,000X slower than successive bytes on disk

» vs. ~4X improvement for page-mode vs. regular accesses to DRAM


Bottom line:
 Design decisions made for disk caches in DRAM driven by

enormous cost of misses

SRAM
–6–

DRAM

Disk
CS 105

Impact of Properties on Design
If disk cache were organized like L1/L2 cache, how would we set following design parameters?


Line size?
 Large, since disk better at transferring large blocks



Associativity?
 High, to mimimize miss rate



Write through or write back?
 Write back, since can’t afford small writes to disk

What would the impact of these choices be on:


Miss rate
 Extremely low: << 1%



Hit time
 Must match cache/DRAM performance



Miss latency
 Very high: ~10ms



Tag storage overhead
 Low, relative to block size
CS 105

–7–

Locating an Object in a ―Cache‖
Review of SRAM (L1/L2) Cache
 

Tag stored with cache line Maps from cache block to memory blocks
 From cached to uncached form
 Save a few bits by only storing tag of blocks that are in cache  No tag for block not in cache



Hardware retrieves information
 Can quickly match against multiple tags

―Cache‖
Data 243 17 • • • 105
CS 105

Tag Object Name X 0: D X • • • J

= X?

1: N-1:

–8–

Locating an Object in a ―Cache‖
DRAM (disk) Cache
 

Each allocated page of virtual memory has entry in page table Mapping from virtual to physical pages
 From uncached form to cached form



Page table entry (tag) even if page not in memory
 Specifies disk address  Only way to know where to find page



OS retrieves information from disk as needed
Page Table Location ―Cache‖ Data 0: 1: N-1: 243 17 • • • 105
CS 105

Object Name X

D: J: X:

0
On Disk

• • • 1

–9–

A System with Physical Memory Only
Examples:


Most Cray machines, early PCs, nearly all embedded systems, etc. Memory

Physical Addresses

0: 1:

CPU

N-1:


Addresses generated by the CPU correspond directly to bytes in physical memory
CS 105

– 10 –

A System with Virtual Memory
Examples:


Memory Page Table 0: 1:

Workstations, servers, modern PCs, etc.

Virtual Addresses

0: 1:

Physical Addresses

CPU

P-1:

N-1: Disk



Address Translation: Hardware converts virtual addresses to physical ones via OS-managed lookup table (page table)
CS 105

– 11 –

Page Faults (Like ―Cache Misses‖)
What if object is on disk rather than in memory?
 

Page table entry indicates virtual address not in memory OS exception handler invoked to move data from disk into memory - VM and Multiprogramming are symbiotic
 Current process suspends, others can resume
 OS has full control over placement, etc.

Before fault
Page Table
Virtual Addresses CPU Physical Addresses

Memory

After fault
Memory Page Table Virtual Addresses CPU Physical Addresses

Disk – 12 –

Disk CS 105

Servicing Page Fault
(1) Initiate Block Read

Processor signals controller


Read block of length P starting at disk address X and store starting at memory address Y

Processor
Reg

(3) Read Done

Cache

Read occurs
 

Direct Memory Access (DMA) Under control of I/O controller

Memory-I/O bus (2) DMA Transfer Memory I/O controller

I/O controller signals completion
 

Interrupt processor OS resumes suspended process

disk Disk

disk Disk

– 13 –

CS 105

Motivation #2: Memory Mgmt
Multiple processes can reside in physical memory. How do we resolve address conflicts?


What if two processes access something at same address?
kernel virtual memory stack memory invisible to user code

%esp

Linux/x86 process memory image
0

Memory-mapped region for shared libraries

the ―brk‖ pointer runtime heap (via malloc) uninitialized data (.bss) initialized data (.data) program text (.text) forbidden CS 105

– 14 –

Solution: Separate Virtual Address Spaces


Virtual and physical address spaces divided into equal-sized blocks
 Blocks are called ―pages‖ (both virtual and physical)



Each process has its own virtual address space
 Operating system controls how virtual pages are assigned to

physical memory
0

Virtual Address Space for Process 1:

0

Address Translation

VP 1 VP 2

PP 2

...

Physical Address Space (DRAM)
(e.g., read/only library code)

N-1 PP 7

Virtual Address Space for Process 2:
– 15 –

0

VP 1 VP 2

...

PP 10 M-1 CS 105

N-1

Motivation #3: Protection
Page table entry contains access-rights information


Hardware enforces this protection (trap into OS if violation occurs) Page Tables
Read? Write? VP 0: Yes No Yes No Physical Addr PP 9 PP 4 XXXXXXX

Memory

0: 1:

Process i:

VP 1: Yes VP 2: No

• • •

• • •

• • •

Read? Write? VP 0: Yes Yes No

Physical Addr PP 6 PP 9

Process j:

VP 1: Yes

N-1:

VP 2:

No

• • •

No

• • •

XXXXXXX

• • •

– 16 –

CS 105

VM Address Translation
Virtual Address Space


V = {0, 1, …, N–1}

Physical Address Space



P = {0, 1, …, M–1} M < N—Usually… PDP-11/70, 32-bit Pentiums violate this
MAP: V  P  {} For virtual address a:
 MAP(a) = a′ if data at virtual address a is at physical address

Address Translation




a′ in P  MAP(a) =  if data at virtual address a is not in physical memory » Either invalid or stored on disk

– 17 –

CS 105

VM Address Translation: Hit

Processor Hardware Addr Trans Mechanism Main Memory a' physical address

a virtual address

part of on-chip memory mgmt unit (MMU)

– 18 –

CS 105

VM Address Translation: Miss
page fault Processor Hardware Addr Trans Mechanism  a' physical address fault handler Main Memory Secondary memory

a
virtual address

OS performs this transfer (only if miss)

part of on-chip memory mgmt unit (MMU)

– 19 –

CS 105

VM Address Translation
Parameters
  

P = 2p = page size (bytes). N = 2n = Virtual-address limit M = 2m = Physical-address limit
p p–1 virtual page number page offset 0 virtual address

n–1

address translation

m–1 p p–1 physical page number page offset

0 physical address

Page offset bits don’t change as a result of translation
– 20 – CS 105

Page Tables
Virtual Page Number Memory-resident page table
(physical page Valid or disk address) 1 1 0 1 1 1 0 1 0 1

Physical Memory

Disk Storage (swap file or regular file system file)

– 21 –

CS 105

Address Translation via Page Table
page table base register VPN acts as table index virtual address n–1 p p–1 virtual page number (VPN) page offset valid access physical page number (PPN) 0

if valid=0 then page not in memory

m–1 p p–1 physical page number (PPN) page offset physical address

0

– 22 –

CS 105

Page Table Operation
Translation
 

Separate (set of) page table(s) per process VPN forms index into page table (points to a page table entry)
page table base register VPN acts as table index virtual address n–1 p p–1 virtual page number (VPN) page offset valid access physical page number (PPN) 0

if valid=0 then page not in memory

m–1 p p–1 physical page number (PPN) page offset physical address

0

– 23 –

CS 105

Page Table Operation
Computing physical address


Page Table Entry (PTE) provides information about page
 If (valid bit = 1) then page is in memory.

» Use physical page number (PPN) to construct address  If (valid bit = 0) then page is on disk (or nonexistent) » Page fault
page table base register VPN acts as table index virtual address n–1 p p–1 virtual page number (VPN) page offset valid access physical page number (PPN) 0

if valid=0 then page not in memory

m–1 p p–1 physical page number (PPN) page offset physical address

0

– 24 –

CS 105

Page Table Operation
Checking protection


Access-rights field indicates allowable access
 E.g., read-only, read-write, execute-only  Typically support multiple protection modes (e.g., kernel vs. user)



Protection-violation fault if user doesn’t have necessary permission
page table base register VPN acts as table index virtual address n–1 p p–1 virtual page number (VPN) page offset valid access physical page number (PPN) 0

if valid=0 then page not in memory

m–1 p p–1 physical page number (PPN) page offset physical address

0

– 25 –

CS 105

Integrating VM and Cache
VA CPU Translation hit PA Cache miss Main Memory

data

Most caches ―physically addressed‖
   

Accessed by physical addresses Allows multiple processes to have blocks in cache at same time else context switch == cache flush Allows multiple processes to share pages Cache doesn’t need to be concerned with protection issues
 Access rights checked as part of address translation

Perform address translation before cache lookup
 
– 26 –

Could involve memory access itself (to get PTE) So page table entries can also be cached
CS 105

Speeding up Translation With a TLB
―Translation Lookaside Buffer‖ (TLB)
  

Small hardware cache in MMU Maps virtual page numbers to physical page numbers Contains complete page table entries for small number of pages
VA CPU TLB Lookup hit PA miss Main Memory

Cache hit

miss
Translation

data
– 27 – CS 105

Address Translation With a TLB
n–1 p p–1 0 virtual page number page offset virtual address

valid

tag physical page number

.

.
=

.

TLB

TLB hit
physical address tag valid tag data index byte offset

Cache

=

cache hit
– 28 –

data
CS 105

Multi-Level Page Tables
Given:
  

Level 2 Tables

4KB (212) page size 32-bit address space 4-byte PTE Would need a 4 MB page table!
 220 *4 bytes  Per-process

Problem:


Level 1 Table

Common solution
 

...

Multi-level page tables E.g., 2-level table (P6)
 Level-1 table: 1024 entries, each of

– 36 –

which points to a Level 2 page table.  Level-2 table: 1024 entries, each of which points to a page
CS 105

Main Themes
Programmer’s View


Large ―flat‖ address space
 Can allocate large blocks of contiguous addresses



Process ―owns‖ machine
 Has private address space
 Unaffected by behavior of other processes

System View


User virtual address space created by mapping to set of pages
 Need not be contiguous  Allocated dynamically  Enforce protection during address translation



OS manages many processes simultaneously
 Continually switching among processes
 Especially when one must wait for resource

– 37 –

» E.g., disk I/O to handle page fault

CS 105


				
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