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Adeleke Ajirotutu is a seasoned and motivated engineering director with excellent technical leadership, project management, communication skills and proven success leading development of multiple generations of hand-held consumer electronics products, low power ultra-mobile PC (UMPC) SOC, wireless LAN, and Graphics products.
ADELEKE AJIROTUTU 916.337.0649 email@example.com SUMMARY A seasoned and motivated engineering director with excellent technical leadership, project management, communication skills and proven success leading development of multiple generations of hand-held consumer electronics products, low power ultra-mobile PC (UMPC) SOC, wireless LAN, and Graphics products. Proven track record managing silicon design from definition to high-volume production. Worked in Startup (ShareWave, Inc –acquired by Cirrus Logic) and Fortune 500 companies (Sun/Intel) Developed low power, low cost, quick turn wireless chips; High volume, high performance Graphics chips. 20+ years of engineering success in the complete product life-cycle for complex ASIC’s, and mixed- signal ICs Led development of the industry’s first pre-standard wireless multimedia chips at ShareWave, Inc. _________________________________________________________________________________________________ PROFESSIONAL EXPERIENCE Adeleke Ajirotutu Consulting 01/2012 – Present Semiconductor development consultant, -multimedia and Wi-Fi IC specialist Worked with early stage and mature companies ensure product development in semiconductor intensive markets. Helped delivered targeted solutions to the unique elements of clients situations. Helps clients ensure success by partnering in: o Product development infrastructure, planning, and execution: SOC, EDA, Libraries, IP and re-use, IT, feasibility, cost, and development estimates, Vendor contracts and relationship management, and Project management o Organizational Design: Structure, Skills assessment, Staffing, Coaching, Remote and int'l development centers DSP Group, Rancho Cordova, CA 11/06 – 01/2012 Senior Director of Engineering Successfully delivered 3 multimedia products into production on time. Responsible for all 802.11 Wi-Fi hardware and software (driver) development of the first 2 products Responsible for leading and managing all US sites for DSPG and reported to the division manager in Israel. Also managed a verification team in Israel. Responsible for the 802.11 Wi-Fi MAC and Baseband processor architecture, RTL design, verification and FPGA emulation of the system. Provided technical leadership through all phases of the product design cycle from conceptual design, specification, prototyping, hardware bring-up, compliance testing and release to manufacturing. Assessed projects risks; made adjustment needed to keep development on schedule and delivered on time. Successfully delivered working SOCs that tightly integrate digital technologies that includes two ARM cores, multimedia hardware engines (video processors, 2D/3D graphics, Bluetooth, DECT, Wi-Fi networking) and a wide range of chip interfaces. Managed hardware bring-up, Wi-Fi compliance testing and released to manufacturing. Managed managers, senior engineers with varying skill levels and projects; defined requirements, design and test specifications, project schedules and program reviews. Managed customers, 3rd party vendors and contract relationships. Developed and drive high performance engineering teams. Drove efficiency and increase productivity across the sites. Worked through all personnel issues. Provided guidance on employee development, performance, productivity issues and resolve conflicts. Adeleke Ajirotutu Page Two 916-337-0649 Established, developed and maintained strong relationships across the sites and across the DSP Group global community to achieve projects goals. Prepared department weekly, monthly, and quarterly reports for the executive team. Drove Engineering project planning/reviews quarterly in Israel. Hired, motivated and retained high performance engineering teams. Identified, negotiated, and managed contractors. INTEL Corp., Folsom, CA 06/05 – 08/06 Senior Engineering Manager Led an organization of 53 engineers including 6 functional managers to design, simulate and validate high speed ultra mobile PC chipset (11.5 million gates, 120 embedded memories, multi-vdd, 0.13um process, 5 PLLs, 9 clocks range from 33MHz-533MHz operating frequencies, 3D/2D graphics, Video decode engine, FSB, DDR2 interfaces, etc.). Participated in staffing the silicon design teams including definition, specification micro-architecture, RTL, circuit design, pre-silicon validation, physical design, full chip integration and silicon debug. Led day-to-day development activities through a strong presence, clarified team goals and made adjustments needed to keep on schedule. Evaluated and acquired 3rd party video engine IP. Worked through all personnel issues- provided guidance on employee development, performance, productivity issues and resolved conflicts. Managed across three sites. Prepared department weekly, monthly, and quarterly reports. CRESTA LOGIC INC., El Dorado Hills, CA 03/03 – 06/05 President of Design Services Built a strong team of consultants that provide VLSI engineering design services to customers including Sony. Collaborated with customers in System-On-Chip (SOC) design, design verification, pre-silicon verification, chip emulation, FPGA prototyping, physical design (Synopsys Astro), physical verification, and timing closure. Plan, organize, and monitor the work. Additionally, strong knowledge of cost-effective development, design-for-test, design re-usability, design portability across foundry process technologies. Managed project schedules, budgets, technical requirements and project deliverables. CIRRUS LOGIC (Formerly SHAREWAVE INC.), El Dorado Hills, CA 08/97 – 12/02 Director of Engineering, Wireless Networking Division 10/01 – 12/02 Responsible for the development of a highly integrated SOC that included IEEE 802.11a/b/g MAC, ARM processor, host processor interfaces, hardware co-processing encryption engines (WEP/AES), baseband analog and RF components. The chip was on .18um TSMC process technology. Led a team of 15 engineers that developed an 802.11b baseband processor ASIC for use in WLAN systems. The chip taped out to .18um UMC technology using Artisan library. Successfully led an external backend design, foundry services and worked closely with a 3rd party IP partner that designed the ADC/DAC. Director of VLSI Development, ShareWave Inc 08/00 – 10/01 Managed the Wireless hardware group responsible for developing highly integrated ASICs for high performance, multimedia, broadband gateways and wireless in-home network products (Bridge Access Point 10/100 Mbps, NIC cards, PCMCIA Card, USB, PCI, mini-PCI). Designed and implemented a highly integrated 802.11 Wireless MAC (ARM processor), Baseband processor ASICs used for PC Network Controller and Broadband Network & System Controllers. Managed board design. Grew the team to 25 engineers. Directed and motivated team members. Adeleke Ajirotutu Page Three 916-337-0649 Director of VLSI Development, ShareWave Inc 08/97 – 08/01 Established and managed development team, IT, EDA flow and infrastructure and foundry interface. Built and managed a strong ASIC design organization of 20 people from scratch in a start-up company. Oversee scheduling and ensure delivery on time and budget. Successfully designed and taped-out 5 complex, high performance VLSI chips used for multimedia product. The chips are: Two Network controller chips (ARM based, wireless MAC) .35um, 100MHz. Compression and Decompression chips (Wavelet transform) .35um, 100MHz. The first chip combined Wavelet Compression/Decompression for proof of concept. All the chips were first time functional. Managed the chips from initial architecture to production with outstanding project management, team building, and interpersonal skills. Provided technical management, chip bring-up, bug tracking/fixes, chip qualification, board qualification, product sampling, production ramp, and product launch. Led all the chip design disciplines from micro-architecture, logic design, logic simulation, physical design and timing closure. Supervised physical design, tape-out and silicon debug. SUN MICROSYSTEMS INC, Mountain View, CA 06/88 – 08/97 Senior Hardware Design Manager, Graphics Product Division 07/92– 08/97 Worked on 3 really great programs at Sun. These products were leadership products and great revenue generators for Sun. Managed a team of 25 ASIC engineers that developed 4 complex VLSI chips simultaneously for a high performance 3D graphics accelerator targeted at mid to high-end Mechanical CAD/Solid Modeling markets. 4 Chips and 16 instances of these chips were on a single S-Bus card with all Drivers and Application development. The chips perform geometry preprocessing, vertex processing (transform, lighting and setup) and primitives conversion to pixels all the way to the frame buffer. Responsibilities include project chips technical direction, methodology (structure design), foundry selection, board design; project planning; resource planning and system bring-up (chips, board, and software). Managed the 4 chips from definition to high volume production. Managed 4 technical lead engineers. Hardware Lead Design Engineer, Graphics Product Division 07/88 – 06/92 Led the design and debug effort of a full custom VLSI floating-point processor for a 3D graphics accelerator. The chip performed the vertex processing of a 3D accelerator. Responsible for project planning, resource planning, micro-architecture, design specification, chip and module partitions, logic design, chip integration, chip layout, physical design, backend verification and vendor management. ____________________________________________________________________________________________ EDUCATION MS Electrical Engineering, University of Santa Clara, CA BS Electrical Engineering and Computer Science, University of California, Berkeley, CA ____________________________________________________________________________________________________________ PATENTS Floating Point Processor for a three dimensional Graphics accelerator which includes Floating point, Lighting, and Set-up cores for improved performance. U.S. Patent issued April28, 1998, (No. 5,745,125).
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