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TUTORIAL EC2001 PRINCIPLES OF ELECTRONICS ENGINEERING Module 1: RC Filters, Diode and their types, Rectifiers, Filters, Clipper, Clamper, Zener diode and its applications. 1. Refer to figure 1. Explain why it is called a high pass RC circuit. Show that its transfer function is given as Vo (s) RCS -------- = A(s) = ----------- and C Vi (s) 1+RCS R V0 1 Vs | A(s) | = ---------------------------- where fo = 1 / 2RC [1+(f )o/ f)2] ½ Fig. 1 And = arctan (fo / f). Where is the angle by which output voltage leads the input voltage and f o is the cut-off frequency. At this frequency fo, the magnitude of capacitive reactance is equal to the resistance and the gain is 0.707. 2. Refer to figure 2. Explain why is it called a low pass RC circuit, show that its transfer function is given as Vo (s) RCS -------- = A(s) = ----------- and Vi (s) 1+RCS, R 1 | A(s) | = ---------------------------- and = tan-1 (f / f2) C v0 [1+(f / f2)2] ½ 1 Where f2 = ---------------- , the upper 3 dB frequency. 2RC Fig. 2 2. Explain the working of a PN junction diode. Define space charge region or depletion region. 3. What do you mean by Ideal diode & explain the V-I Characteristic of non Ideal diode in forward region, reverse region and breakdown region. 4. (a) How does the reverse saturation current of a p-n diode vary with temperature? (b) How does the diode voltage (at constant current) vary with temperature? 5. (a) Define dynamic resistance of a diode. Calculate the dynamic resistance r for a silicon diode at room temperature for a dc current of 1mA. (b) Explain the transition capacitors CT and the diffusion capacitance CD of a diode. What is a varactor diode. 6. (a) Explain physical mechanism for avalanche breakdown in diodes. (b) Explain physical mechanism for Zener breakdown in diodes. 7. A silicon diode is operating at 25oC with a forward bias of 0.6V and current of 0.5A. Calculate IO. If current is held constant at 0.5A, what voltage will exist across the diode at the following temperatures (i) 75oC, (ii) –45oC ? 8. A silicon diode operates at a forward voltage of 0.4V. Calculate the factor by which the current will be multiplied when temperature is increased from 25 to 150oC. 9. (a) A silicon diode has a reverse breakdown voltage V B of 100V. Its reverse current IR, is 1 A at 22oC when reverse voltage applied across the diode is 95V. (b) What is the diode’s reverse saturation current at 22oC? (c) How much current will flow through the diode when it is forward biased with 0.5V at room temperature? (d) What will be the forward current at 0.5V forward bias when temperature raises 30oC? 11. What does a dc load line drawn on diode’s characteristic represent? 12. Explain with the aid of a sketch the use of a diode’s characteristic and dc load line to determine the dc current that will flow through a diode when it is connected in series with a resistor and a dc supply. 13. (a) Explain how to obtain the dynamic characteristic from static volt-ampere curve of a diode. (b) Draw the dc load line for (i) infinite load resistance, RL = , (ii) RL = 0. (c) Define for a diode (i) static characteristic (ii) dynamic characteristic (iii) transfer or transmission characteristic. 14. For a Zener diode explains: Zener knee current Izk, Zener test current and test voltage, and the dynamic impedance Zz. 15. Explain briefly the two different mechanisms at work in Zener diodes below and above approximately 6V breakdown. 16. (a) Draw a circuit using Zener diode to regulate the voltage across the load. Explain its operation. Can this circuit regulate the variations input voltage? Explain. (b) Two p-n, Ge diodes are connected in series opposing. A 5V battery is imposed upon this series arrangement. Find the voltage across each junction at room temperature, Assume that the magnitude of the Zener voltage is greater than 5V. Note that the result is independent of reverse saturation current. Is it also independent of temperature? 17. If the magnitude of the Zener voltage is 4.9V, what be the current in the circuit? The reverse saturation current is 5A. 18. Design a voltage regulator circuit to provide 12V across a load whose current varies from 5mA to 35mA. An unregulated 18V dc source is to be used. For Zener it is given that Vz = 12V at IzT = 20mA. Determine: (a) The voltage dropping resistor and its power rating using an average value for I L when Lz = IzT. (b) Minimum power rating of the Zener diode. (c) The maximum value of Izk to maintain reasonable voltage regulation when load current is at its maximum. (d) Assuming that for average Zener current of 20mA the Z z = 10 ohms; calculate the approximate voltage variation and percent regulation expected from 5mA to 35mA variation in load current. 19. (a) A 10V Zener diode is operated at a reverse current of 5mA at room temperature of 20oC. Determine its Zener voltage at temperature of 750C.Assume Zener temperature coefficient z = 0.06% / oC. (b) Assuming the change in Zener voltage in part (a) is more than that can be tolerated, what change will take place at 75oC if diode is operated at 40ma. Assume z = 0.035% / o C in this case. 20. What would be the overall change in Zener voltage at 75 oC if two 5V Zener diodes were operated in series at a current of 4mA? Take Vz = 5V at 20oC and z = 0.005% / oC. 21. A 12V Zener operating at 5mA has dynamic impedance Z z = 25 ohms. Calculate the change in Zener voltage for 1.5mA change in its current. 22. A Zener diode has Zener voltage 4V at room temperature. Will this increase or decrease or remain same when the temperature rises to 50oC? 26. (a) Refer to fig.1 The avalanche diode regulates at 50V over a range of diode currents from 5 to 40 mA. The supply voltage V = 200V. Calculate R to allow voltage regulation from a load current IL = 0 up to Imax, the maximum possible value of IL. What is Imax? (b) If R is set as in part (a) and the load current is set at IL = 25 mA, what are the limits between which V may vary without loss of regulation in the circuit? R IL RL V VL Fig 1 Module – 1 Rectifiers and filters: 1. What do you mean by rectification? Explain the working of a half wave rectifier. 2. Define ripple factor, ratio of rectification and transformer utilization factor. 3. Show that the ripple factor for a half wave rectifier is 1.21. Also find the values of ratio of rectification and transformer utilization factor. 4. Derive the ripple factor for a full wave rectifier. Also find out the values of ratio of rectification and transformer utilization factor. 5. Define in words and as an equation the (i) dc current, I dc (ii) DC voltage, Vdc (iii) ac current Irms. 6. (a) Show that, for a half wave rectifier the following: (i) Idc = Iav= Im/ (ii) Irms = Im/2 (iii) Vdc = Vm/ - Idc (Rf + Rs). (b) Similarly, obtain the expressions for Idc, Vdc, and Irms for a full wave rectifier. 7. Define regulation. A power supply has 100% regulation. Is it a good power supply? Justify your answer. 8. Derive the regulation equation for a full-wave rectifier. 9. (a) Define PIV. What is the PIV for a full wave rectifier using ideal diodes for (i) circuit using two diodes, (ii) bridge circuit? (b) What is the PIV for a half-wave rectifier? 10. Is it possible for a dc power supply to have a voltage regulation in excess of 100% using passive loads only? Explain. 11. What are the advantages of a full-wave rectifier over a half-wave rectifier? 12. Show that the ripple factor can be written as: Irms 2 r= ------- -1 Idc 13. Show that if Rs = Rf = 0, one can write for the output voltage of full-wave rectifier as: v(t) = 2Vm/ - ( 4Vm/3 ) cos 2t - ( 4Vm/5 ) cost 4t; and if Rs and Rf are not negligible, then v(t) =I(t) RL. 14. What is the lowest ripple frequency in a half rectifier and in a full-wave rectifier? 15. Determine the rating of a transformer to deliver 100 Watts of do power to a load under following conditions: (i) Half-wave rectifier (ii) Full-wave rectifier using two diodes (iii) Bridge rectifier. 16. A half-wave rectifier consists of a diode having dynamic resistance of 1 ohm at its operating point and a transformer whose open circuit secondary voltage is 12.6V, 50Hz. It has secondary winding resistance of 3 ohms. (a) What is the no load dc voltage of the rectifier? (b) What is the output voltage when full load draws a dc current of 100mA? (c) What is the percentage voltage regulation of this power supply? (d) What is the internal resistance of this power supply? 17. (a) A dc power supply is known to have a ripple factor of 10%. If the dc output voltage is 10V, what is the rms value of output voltage in the output? (b) Assuming ripple is approximately sinusoidal in nature, what is the peak-to-peak voltage? (c) Assuming that this ripple is approximated as a triangular wave; what is its peak-to- peak voltage? 18. (a) What is the necessary ac input power from the transformer secondary used in a half- wave rectifier to deliver 500W of dc power to the load? (b) What is ac input power for the same load in a full-wave rectifier? 19. A 120V, 50Hz voltage is applied to the primary of a 5:1 step-down transformer whose secondary is center-tapped, allowing a load of 1K to be connected to a full-wave rectifier utilizing two diodes. Neglecting the voltage drop across the diodes, determine: a. The dc voltage across the load. b. The dc current through the load. c. The dc power delivered to the load. d. The VA rating of the transformer secondary. e. The ac input power to the transformer assuming an 80% efficient transformer and ratio of rectification of this circuit of 0.812. f. The ripple voltage across the load. g. The reading of an ac voltmeter (that responds to peak-to-peak value) connected across the load. h. The PIV across each diode. 20. Prove that the regulation of both the half-wave and the full-wave rectifier is given by: % Regulation = Rf / RL x 100 21. What is a filter? Why is it needed at the output of a rectifier? Describe the CLC or -filter. 22. A 12.6V center-tapped transformer is used in full-wave rectifier. 100 F capacitor is used to provide a filtering for a 1K-ohm resistive load. Determine: (a) The percent ripple in the output (b) The dc output voltage. 23. An LC filter is to be used to provide a dc output with 1% ripple when operating from a full- wave rectifier at 50Hz. To conserve the size of choke, L/C = 0.01 is recommended (L in henrys, C in microfarads). Determine the required values of L and C. 24. Design a full-wave rectifier with an CLC filter to provide 12V dc at 250mA with a maximum ripple of 50% specify: (a) Your suggested practical values of L and C. (b) A bleeder resistor to maintain good voltage regulation. (c) The transformer secondary voltage assuming the choke has a dc resistance of 10 ohms and bridge rectifier is used. (d) The PIV capability of the diodes. (e) The peak current capability of the diodes. 25. (a) A -type CLC filter is to be used at 50Hz to provide 6V dc output with 0.1% ripple for a load of 10K. If the two capacitors are both 50 F, what must be the minimum value of inductance to use? (b) Repeat part (a) for a 1K load. 26. A full wave rectifier employs a CLC filter consisting of two 40µF capacitances and a 20H choke. The load current is 50 µA. Calculate the DC output voltage and ripple voltage. The resistance of the choke is 200Ω. 27. The output of a FWR is fed from a 40-0-40 volt transformer. The load current is 0.1 A. Two 40µF capacitors are available. The load resistance is 50 Ω. Calculate the value of inductance for the CLC filter if the ripple factor is 0.0001. 28. Determine the output waveform for the given circuit (fig.2) if a. input is a sinusoidal wave with a peak voltage of 20V. b. input is a square wave with a positive peak of 20V and a negative peak of 10V. V=5V + + vi R Vo - - Fig 2 29. Determine Vo for the network shown (fig.3) a. if the input is a triangular wave of peak voltage 16V. b. if it is a silicon diode with VT=0.7V. R + + vi Vo V= 4V - - Fig 3 30. What is a clamper? Determine Vo for the network shown in the figure (fig.4) for a square wave input with positive peak of 10V and negative peak of 20V. C=1F + + vi 100kΩ Vo V= 5V - - Fig 4 Module – 2 BJTs 1. What do you mean by a transistor? Explain the working of an npn transistor. 2. What are the basic types of transistor amplifier configuration? What do you understand by active region of operation of a transistor? 3. Define current gain alpha in words and as an equation. 4. Sketch a family of CB output characteristics for a transistor. Indicate the active, cut-off, and saturation regions. 5. Explain Early effect and base width modulation in transistors. 6. (a) Find an expression for Ic for a CB transistor configuration. (b) Find an expression for Ic for a CE transistor configuration. Define ICBO. 7. Define , hFE, ICEO. 8. (a) For a transistor in CE configuration, given that VBB = 5V; Rb = 200K; Rc = 3K; Vcc = 10V; = 100; the transistor is silicon, n-p-n with Icc = 20 nA. Find the transistor currents. (a) Repeat part (a) if Re = 2K emitter resistor is added to the circuit. Also determine if the transistor is in active region. 9. (a) The transistor in CE configuration as in above problem is modified by changing R b = 50K. Determine whether or not the silicon transistor is in saturation and find IB and IC. (b) Repeat part (a) above with the 2K-emitter resistance added. 10. Refer to Fig.5. If = 0.98 and VBE = 0.7 V find R1 in the circuit shown for an emitter current IE = -2 mA. Neglect the reverse saturation current. 12 V 3.3 R1 k IC Fig 5 2 mA R2 20k Re 100 11. Refer to circuit in Fig.6, given that VCC = 24V, RC = 10K and Re = 270. If a silicon transistor is used with = 45 and if VCE = 5V; find R. Neglect the reverse saturation current. VCC RC R C Re 12. Derive the relationship between and for a transistor. 13. Let IB = 50A, IC = 15 mA, VBE = 0.65V, and VCE = 5V for an npn transistor operating in the active region. Calculate (i) IE, (ii) VCB, and (iii) the total power dissipated by the transistor. 14. (a) Prove the relation ICEO = (+1) ICBO (b) Refer to Fig. 7. Given that dc = 75, VBE = 0.6V ICEO = 2 A, VCC = 4.5V. Find IC and VCE. VCC 2K Fig 7 100 Fig. 7 15. Refer to Fig. 8. Given that dc = 75, VBE = 0.6V, ICEO = 1.3A, and Rsat = 40 (a) Find dc and ICBO. Let VBB = 6V, RB = 27K, and VCC = 9V. (b) Calculate IC if RC = 400 ohm (c) Find IC if RC = 800 ohm. R C RB VCC VBB Fig 8 16. (a) What does a dc load line represent? (b) Can this be used when an ac signal is present? (c) When is it necessary to draw an ac load line? And, how is it drawn? 17. (a) What is the main advantage of a CE over a CB as far as biasing is concerned? (b) Why is loading of input signal by the bias resistor not generally a problem in a CE amplifier compared with a CB? 18. (a) What three factors contribute to thermal instability in a CE amplifier? Which one has the least effect in silicon transistors? Why? (b) What do you understand by the term thermal runaway? Explain in your own words. 19. (a) Define the stability factor S. Find S for a fixed bias CE amplifier and a CB amplifier. (b) Derive the stability factor S for collector to base bias circuit in a CE amplifier. Discuss the disadvantages of collector to base bias. (c) Determine the base resistor RB for collector to base bias and calculate the stability factor S. Given: VCC = 12V, RL = 330 ohms; IB = 0.3 mA; = 100, VCEQ= 6V. 20. (a) Explain how self-bias or emitter bias circuit provides thermal stability. (b) Derive the expression for the thermal stability factor S for emitter bias. (c) Determine the bias resistor RB to provide a bias current of 0.3 mA, for a self-bias circuit. Also calculate the stability factor S, and compare it with the fixed bias circuit. Given: VCC = 12V, RL = 330 ohms, Re = 100 ohms, VBE = 0.2V; ICQ = 18 mA; = 100. 21. (a) Draw the circuit for voltage divider bias with emitter bias. This is also known as voltage divider with self-bias. Derive the expression for the stability factor S for this type of bias. Mention its advantages over self-bias. (b) Explain the function of emitter bypass capacitor. Why is capacitive coupling is used to connect a signal source to an amplifier? 22. In a voltage divider with self-bias circuit R1 is connected to +VCC and base of the transistor Q. R2 is connected from base to ground. Determine the values of R1 and R2 to provide a bias current IB = 0.3 mA, so as to locate the operating point at ICQ = 18 mA and VCEQ = 4.25V. VCC = 12V. RL = 330 ohms, Re = 100 ohms, VBE = 0.2V; = 100, Make the stability factor S = 10. Module – 3: Transistors at low frequencies 1. Draw the hybrid h-parameter equivalent circuit for a linear four terminal network. Write the equations relating input and output variables. 2. Define all the four hybrid h-parameters for a CE-connection. How these parameters can be determined from CE input and output characteristics? 3. Are the h-parameters for transistor constant? What do they vary with? Which ones show greatest variation? What other factors determine the values of a transistor’s h- parameters? 4. (a) What are approximate conversion formulas for h-parameters from CE values to CC values. (b) What are the approximate conversion formulas for h-parameters from CE to CB values? 5. Derive the general expressions; valid for CE, CB and CC amplifiers; for the current gain, input resistance; voltage gain, and output resistance. 6. Derive the general expressions for voltage and current gains taking into account the Rg of the source. 7. Consider a CB amplifier with RL = 1.5 K, Rg = 600 ohms, Vg= 0.15V. The CB, h- parameters are hib = 20 ohms, hrb = 3 x 10-4, hfb = -0.98, hob = 0.5x10-6 mho. Calculate Ai, Ri, Av, Ro, Ap, Avg and Aig. 8. (a) Show that Ri < hie in a CE amplifier. (b) Show that Ri > hib in a CE amplifier. 9. The CE h-parameters are hie = 4K, hre = 7 x 10-4, hfe = 135, hoe = 50 Siemens. Obtain the CB h-parameters. 10. Draw the approximate hybrid h-parameter equivalent circuit for a CE at low frequencies. Under what conditions this equivalent circuit is valid? 11. Draw the circuit of an emitter follower. List its three most important characteristics. 12. Using approximate h-parameter model for the emitter follower circuit, obtain the expressions for AI, Ri, Av and Ro. 13. (a) State Miller’s theorem with the aid of a circuit diagram. (b) Repeat part (a) above for the dual of Miller’s theorem. 14. For the network shown in the figure (fig. 9) determine re, Zi, Zo, Av and Ai. 10 Ie 10F + F + Ii =0.98 vi zi 1kΩ 5kΩ r0= 1MΩ 2 8 - V V - Fig 9 15. For the emitter follower network (fig.10) determine re, Zi, Zo, Av and Ai. 12V 220kΩ =100, r = ∞ vi Ω10F Ii V0 Io Zi 3.3kΩ Z 0 Fig. 10 16. For the network shown in the figure (fig.11) determine re, Zi, Zo, Av and Ai. Fig 10 16 V I 90k 2.2k o C Ω Ω =210, r0 = v 1 50KΩ C i I 2 V i 10kΩ 0 Z 0.68k Z i Ω 0 F11 11 17. For the network shown in the figure (fig.12) determine Zi, Zo, Av and Ai. 8V Io 330kΩ 2.7kΩ C1 V0 C2 vi Ii hfe=120, hie =1.175KΩ, Zi hoe=20 A/V Fig 12 18. For the network shown in the figure (fig.13) determine Zi, Zo, Av and Ai. + + Ii V0 hfb=0.99, zi 2.2kΩ hib =14.3Ω, 3.3kΩ hob=0.5 A/V Z0 4V 10V - - Fig 13 Module – 3 :Transistor at high frequencies 1 What are the physical origins of resistances and capacitances in the hybrid - model of CS amplifier at high frequencies? What is the order of magnitude of each capacitor and resistor in the hybrid - model? 2 Define fB and fT. What is the relation between them? 3 The following low frequency parameters are known for a given transistor at I c = 10 mA, VCE = 10 V and at room temperature: hie = 500 ohm, hfe = 100 ohm, hoe = 10-5s, hre = 10-4, fT = 50 MHz and CC = 4pF. Compute the values of all the hybrid - parameters. 4 A silicon pnp transistor has an fT = 400 MHz. What is the base thickness? 5 Given a germanium pnp transistor whose base width is 10-4 cm at room temperature and for a dc emitter current 2 mA, find a) the emitter diffusion capacitance b) fT 6 Given the following transistor measurement made at Ic = 5 mA, Vce = 10V and at room temperature: hfe = 100, hie = 600 ohm, Ai = 10 at 10MHz, Cc= 3 pF. Calculate fB, fT, Ce, rb’,e and rbb’. 7 A transistor amplifier in CE configuration operating at high frequencies has the following parameters: fT = 6MHz, hfe = 50, Rs = 500 ohm, gm = 0.04 A/v, rbb’ = 100 ohm and cc = 10 pF. The load connected is 1 K ohm. Find voltage gain, current gain, 3dB frequency, voltage gain-bandwidth product and current gain – bandwidth product. 8 (a) With hfe = 40, hie = 0.75 K ohm, Ce = 45 pF, Cc = 2 pF, find fB and fT for the transistor. (b) What current gain is possible at a bandwidth of 100 MHz? 9 A single-stage CE amplifier is measured to have the following data: fB = 5MHz, RL = 500 ohm, hfe = 100, fT = 400 MHz. rbb’ = 100 ohm and gm = 100 mA/V. (a) Assuming Cc = 1 pF, Prove that Rs = 439 ohm gives the required bandwidth. (b) With the value of Rs = 439 ohms, show the midband voltage gain Vo/Vs is given by - 32.5 using the approximate analysis. 10 The CE current gain at high frequency is given by the expression. = 0 / [1+j (f/f)] Show that CB current gain can be written in the following form =0 / [1+j (f/f)] where 0 = o/ (1+ 0) f = f/(1+0) 11 (a) Consider hybrid - circuit at low frequencies so that Ce and Cc can be neglected. Omit none of the other elements in the circuit. If the lead resistance is R L = 1/gL, prove that Vce/Vb’c = -gm + gb’c / (gb’c + gce + gL) (b) Do the same by Miller’s theorem. 12 A transistor’s short circuit current gain is measured to be 25 at a frequency 2 MHz. If the fβ = 200 KHz determine: (a) Current gain – Bandwidth product (b) hfe (c) The short circuit current gain at 10 MHz and 100 MHz. 13 Show that at low frequencies the Giacolectto’s model with rb’c and rce taken to be infinite reduces to the CE h-parameters model. 14 A bipolar junction transistor has hie = 6 K ohm, hfe = 224 at Ic = 1 mA with fT = 86 MHz and Cb’e = 12 pF. Determine: (i) gm , (ii) rb’e, (iii) rbb’ 15 Deduce the relation between the hybrid - model parameters and h-parameters. 16 Obtain the expression for the short circuit current gain of a CE configuration and hence draw the frequency response curve. Module – 4: Amplifiers 1 Discuss the effect of feedback on an amplifier 2 Describe various types of feedback with their basic configuration. 3 An amplifier has a mid-band gain A = 500 lower cut off frequency of 50Hz and upper cut off frequency of 40 KHz. If feedback with = 0.1 is introduced, find the gain with feedback and the new values of cut off frequencies. 4 Determine the voltage gain, input impedance and output impedance with the feedback for the voltage series feedback A= 100, ri = 10 K , R0 = 20 K for the feedback of a) = -0.1 b) = -0.5 Comment on the trade off between the gain and impedance of the amplifier. 5 An amplifier has 5% non-linear distortion generated in its final stage. The amplifier gain without feedback is 1500. If the distortion is to be reduced to 2.5% with distortion calculated Af. 6 If the amplifier with the gain = -1000 and feedback of = -0.1 has a gain change of 20% due to temperature, calculate the change in the gain of feedback amplifier. 7 The overall gain of a two stage amplifier shown in fig. 7 is 200 with negative feedback of 20% applied only to the 2nd stage has a gain of 3000 and 10% distortion without feedback find (a) the distortion of the 2nd stage with feedback and (b) the gain of the 1st stage. A1 A2 = 300 VS D1 =0 D2 =0.1 V0 Fig 7 = 0.2 8 An amplifier must maintain its gain at 59 within 1%. If the gain without feedback varies by 10% due to active parameters find the value of feedback necessary to keep gain within 1% and the value of the gain without feedback. 9 An amplifier has a midband gain of 105. A voltage feedback of 10 dB is introduced. Find the value of Af and feedback gain . 10 An amplifier consists of three identical stage connected in cascade. The O/P voltage is sampled and connected to the input in series opposing. If it is specified that the relative change dAf/Af in the closed loop voltage gain Af must not exceed f . Show that the minimum value of open loop gain A of the amplifier is given by A = 3 Af | 1 | / | f | where 1 = dA1/A1 is the relative change in the voltage gain of each stage of the amp. 11 For the following feedback amplifier Fig. 8, calculate Rif = Vs/Ii, Aif = - I/Ii, A’vf = Vo/Vi, Avf = Vo/Vs and R’of. VCC 22K 220K 4.7K V0 220K Q2 100 Q1 22k Vs 1K 22 K 100 Fig 8 Assume transistors are identical and hie = 1.1 K, hfe = 50, hre = hoe = 0. Neglect the reactance of the capacitors. 12 In the two stage feedback amplifier shown below (Fig. 9), the transistor are identical and have the following parameters, hfe = 50, hie = 2K, hre = hoe = 0. Identical the type of feedback and calculate (a) Aif (b) Rif and (c) Avf. VCC 10K 15K Q2 Q1 Is 10K Rs=1K V0 Ref Fig 9 13 Identifies the type of feedback for the following feedback amplifier (Fig. 10) and calculate (a) Fmf, (b) Avf, (c) Rif and (d) Rof. VCC 10K 100K Assume, V0 Re =0 hfe = 100, hie = 1 K Re hre = hoe = 0 Is Fig 10 14 An amplifier with an open loop gain Av = 1000 100 is available. It is necessary to have an amplifier when voltage gain varies by no more than 0.1% (a) Find the revers transmission factors of the network used. (b) Find the gain with feedback. 15 An amplifier without feedback gives a fundamental O/P of 36V and with percentage 2 nd harmonic distortion when the input is 0.028V. (a) If 1.2% of the O/P is feedback into the I/P in a negative voltage series feedback, what is the input voltage? (b) If the fundament is maintained at 36V but the 2 nd harmonic distortion is reduced to 1%, what is the I/P voltage? 16 An amplifier has an open loop voltage gain of 1000 delivers 10W of O/P power at 10% 2nd harmonic distortion when the I/P signal is 10mV. If 40 dB negative voltage series is applied and the O/P power is to remain at 10W, determine (a) the required I/P signal (b) the percentage 2nd harmonic distortion. 17 The h-parameter model of a transistor can be considered represent a feedback amplifier due to the presence of hre source. Using feedback formula find (a) Rif and (b) Yof = 1/Rof taking hre, hoe and source resistance (Rs) into account. 18 Justify that CE transistor Amplifier is internally voltage series positive feedback with feedback factor nearly ( hre) 19 Prove that the negative feedback in an amplifier improves its sensitivity and distortion. State the assumption made. 20 An amplifier with an open loop voltage gain of 1000 has an output impedance of 10 KΩ. It is desired to modify its output impedance to 1 KΩ. What type of feedback is to be applied? Calculate the feedback factor. Also find the percentage change in overall gain for a 10 % change in the open loop gain of the amplifier and the voltage gain with the feed back. Module – 4: Oscillators 1 State and explain the condition of oscillation. 2 Discuss stability criteria for an oscillator. 3 Explain the working of (a) Hartley oscillator (b) Colpitis oscillator (c) Wien Bridge oscillator (d) RC phase shift oscillator. 4 A phase shift oscillator with CE transistor has RL value of 2K ohms and R value of 1K ohm. What is the minimum value necessary for hfe to obtain sustained oscillation? 5 In a phase shift oscillator shown in the following figure 11 has hfe = 60. A three stage ladder is used with R = RK ohm. What is the value of RL necessary to achieve sustained oscillation? What value of capacitance has to be used in each branch in order to obtain sustained oscillations at 5 KHz? VCC R2 When, R3 = R-Ri R3 C Ri= hie Assume that, R1 C C hoe. Re < 0.1 Neglact the effect of Q1 R1, R2 R2 Re Ce Fig 11 6 For the Fig. 12, prove that = Vf’ / Vo = - 1 / [ 1- 5 2 – j (6- 3)] where = 1/RC Assuming that the network does not load the amplifier. Prove that the phase shift of is 180o for 2 = 6 and at this frequency = 1/29. 7 Take into account the loading of the RC network in the phase-shift oscillator of Fig. 12. If R0 is the output impedance of the amplifier ( assume that Cs is arbitrarily large), prove that frequency of oscillation f and the minimum gain A are given by 2 1 1 R R f and A 29 23 0 4 0 2RC R 6 4 0 R R R VDD C C C Rd V0 R R R Vf Rs Fig 12 8 A two stage FET oscillator uses the phase shifting network as shown in the Fig 13, Prove that V’f / Vi = 1 / [3+ j(RC – 1/RC)] 9 In continuation with the above problem prove that the frequency of oscillation is f o = 1/2 RC and that the gain must exceed 3. R C C V’f Vo R Fig 13 10 Find V’f / V0 for the network shown in the fig. 14. b) Sketch the circuit of a phase shift FET oscillator using this network. c) Find the expression for the frequency of operation (oscillation) assuming that the network does not load down the amplifier. d) Find the minimum gain required for oscillation. C R c O C2 R2 Vo V'f u o Fig 14 11 Consider the two sections RC network shown Fig. 15, Find V’f/Vi function and verify that it is not possible to obtain 180o phase shift with a finite attenuation. C C Vo R R Vf Fig15 12 For the feedback network shown in Fig. 16, find (a) the transfer function, (b) the input impedance, (c) If this network is used in a phase shift oscillator find the frequency of oscillation and minimum voltage gain of the amplifier. Assume that the network does not load down the amplifier. R R R C C C Vo V’f 13 Fig 16 Design the wien Bridge oscillator so that the frequency of oscillation is fo = 1 KHz. 14 For the transistor phase shift oscillator of Fig.17 Show that frequency of oscillation is given by 1 1 Rc f where k 2RC 6 4k R VCC Rc R1 R3 C C C Q1 R R R2 Re C' Fig. 17 15 Show that a transistor with a small signal common emitter short circuit gain less than 44.5 can not be used in the phase shift oscillator of Fig. 17 16 Describe briefly a) Series - operated crystal oscillator b) Shunt - excited crystal oscillator j 2 s2 17 Verify jX for the reactance of the crystal, where the symbols have C ' 2 p 2 their usual meanings. 18 a) Prove that the ratio of the parallel to series resonant frequencies is given 1 approximately by 1 C 2 C' b) If C= 0.04 pF and C’ = 2.0 pF, by what percent is the parallel resonant frequency greater than the series- resonant frequency? 19 A crystal has the following parameters: L = 0.33 H, C= 0.065 pF, C’ = 1.0 pF, and r = 5.5 K. a) Find the series resonant frequency. b) By what percent does the parallel resonant frequency exceed the series resonant frequency? c) Find the Q of the crystal. Module – 5: FETs 23. (a) What are the two main types of field-effect transistors? What are the advantages of the FET over a conventional transistor? What do the terms unipolar and bipolar refer to? (b) Give basic construction and symbol for the N-channel FET. With help of diagrams explain the principles of operation of the N-channel JEET. Explain pinch-off and self- pinch off. 25. Draw the characteristic curves for the N-channel JEET. Explain channel ohmic region and channel pinch-off region. 26. Define (a) Drain resistance (b) Transconductance (c) IDSS, (d) IGSS, (e) Amplification factor for the FET. 27. (a) Draw the circuit for common source AC amplifier and explain its operation. (b)Find the expressions for Av, Ro’, Ri’, Ci for the circuit in part (a) above. (c)For the source follower, give the circuit using p-channel FET and expressions for Av, Ro’ and R’i. 28. (a) Give basic construction, symbol, characteristic curves for the N-Channel depletion type MOSFET and explain its operation. (b) Repeat part (a) above for the enhancement MOSFET. (c) Explain the use of FET as a VVR. Explain voltage-controlled attenuator. 29. If IDSS=4mA, VP=4V, calculate the quiescent value of ID, VGS and VDS. Module – 5: Power Amplifiers 1. What is a power amplifier? What are different types of power amplifier? 2. Draw circuit of a class A power amplifier. Describe its operation with the help of waveforms. 3. (a) Draw circuit of a class A, transformer coupled push-pull amplifier. Describe its operation with the help of waveforms. (b) Show that the dc components and all even harmonics are cancelled in this amplifier. (c) What other advantages does the push pull configuration provide? 4. Derive the maximum efficiency for a class A power amplifier. 5. Draw the circuit of a class B, transformer coupled, push-pull amplifier. Explain its operation with the help of waveforms. 6. Explain cross-over distortion in class B push-pull amplifiers. 7. Derive an expression for maximum conversion efficiency in class B, push-pull amplifier. 8. Derive an expression for maximum conversion efficiency in class B, push-pull amplifier. 9. Calculate the efficiency of a transformer coupled class A amplifier for a supply of 12V and output of a. Vp=12V b. Vp=6V c. Vp=2V. 10. For a class B amplifier using a supply of Vcc=30V and driving a load of 16 Ω, determine the maximum input power, output power and transistor dissipation. 11. Calculate the efficiency of a Class B amplifier for a supply voltage of Vcc=24V with peak output voltage of a. VL(p)=22V b. VL(p)=6V 12. Calculate the harmonic distortion components for an output signal having fundamental amplitude of 2.5 V, second harmonic amplitude of 0.1V and fourth harmonic amplitude of 0.05V. 13. Calculate the total harmonic distortion for the previous problem. 14. For harmonic distortion reading of D2=0.1, D3=0.02, D4=0.01 with I1=4 A and Rc=8Ω, calculate the total harmonic distortion, fundamental power component and total power. 15. The transistor of a class A power amplifier is supplied from a 6 V battery. If the maximum collector current change is 30μA, find the power transferred to a 8 W loudspeaker when (i) it is connected directly to the collector (ii) it is coupled through a transformer or maximum power. Also determine the turns ratio for the coupling transformer. 16. For a power transistor working in a class A operation the 0 signal collector current is 100 mA. If dc supply voltage is 12V. Determine (i) the maximum ac power output. (ii) the power rating of the transistor (iii)the maximum collector efficiency. 17. Explain the need for push pull arrangement for power amplifier operation. 18. What is the advantage of Class B complimentary push pull arrangement over simple push pull amplifier? 19. What is crossover distortion? How can it be removed? 20. Prove that a Class B push-pull amplifier produces only odd harmonics. Module – 6 : 2. What is an OPAMP? 3. What are the ideal characteristics of an OPAMP? 4. Mention some linear and non-linear applications of OPAMP. 5. Why a feedback is needed in an OPAMP? What type of feedback is used? 6. Derive the expression for output voltage (a) inverting amplifier, (b) Non-inverting amplifier, (c) Differential amplifier, (d) Integrator, (e) Differentiator & (f) Logarithmic amplifier. 7. Derive the expression for exact and ideal input and output impedances of (a) Inverting and (b) Non-inverting amplifier. 8. What do you mean by CMRR? What is its importance? What is its ideal value? 9. Why the two input terminals of an OPAMP with closed loop configuration are thought to be virtually short-circuited? 10. What are the disadvantages of a differential amplifier using single OPAMP? How it can be overcome by using three OPAMPS? Find the expression of voltage gain of such a configuration. 11. For the amplifier shown in Fig. 1, (a) Prove that it acts as DIFF-AMP. (b) Repeat above for double ended CIRCUIT (Fig. 1b). R2 R2 R1 R1 V04 V2 Y2 V1 Y1 V03 R1 =R3 R3 R4= R2 R4 Fig 1 (b) Fig 1 (a) 12. For an OPAMP define the following terms: (i) Bandwidth, (ii) CMRR, (iii) Unity gain bandwidth, (iv) Input bias current, (v) Input common mode voltage range, (vi) Input impedance, (vii) Input offset current, (viii) Input offset voltage, (ix) Offset voltage temperature drift, (x) Power supply rejection rate , (xi) Slew rate. 13. Discuss the application of voltage follower. 14. (a) Draw the circuit of an emitter coupled DIFF-AMP. (b) Explain why the CMRR for a symmetrical circuit with Re . 15. Derive expression for Ac, Ad and CMRR for symmetrical emitter coupled DIFF-AMP. 16. Explain why the CMRR is infinite if a true constant current source is used in a symmetrical emitter coupled DIFF-AMP. 17. Sketch the transfer characteristics of a DIFF-AMP. 18. Draw an IC OMAMP in block-diagram form and identify each stage by function. 19. Describe the method of measurement of the following quantities of an OPAMP: (i) R i, (ii) Av, (iii) Rc, (iv) Slew rate. 20. Show that the exact expression of voltage gain for a non-inverting amplifier is given by Avf = Vo/ Vin = Av (R1 +Rf)/ (R1 +Rf+ AR1) 21. Show that the exact expression of voltage gain for an inverting amplifier is given by Avf = Vo/ Vin = -Av Rf)/ (R1 +Rf+ AR1) 22. Consider the situation where the inputs to a differential amplifier in the first case is V x = + 50 v and Vy = 950 v. If the CMRR is 100, calculate the outputs in both the cases. Also repeat the problem for CMRR = 10,000 Module – 7: 1. When is Boolean algebra called switching algebra? 2. Obtain the truth table of the function F = xy + xz + yz 3. State and prove the two forms of DeMorgan’s Law. 4. Why NAND and NOR gates are called universal? 5. Verify (a) AB + ABC + BC = B(C+A) (b) AB = ABC + ABC’ + ABC (c) (A+B)(A+C) = AC + AB (d) BC + AC + AB + BCD = BC + AC 6. Simplify the following Boolean functions to minimum number of literals. (a) Y(WZ + WZ) + XY (b) BC + AC + AB + BCD (c) [CD + A] + A + CD + AB 1. Show that the Boolean expression for the following logic circuit (Fig. 1) is F=(A+B) (C+D) E A B C F D E Fig. 1 8. What is the difference between canonical form and standard form? Which form is obtained from a truth table? 9. Define minterms and maxterms for (i) three variables and (ii) four variables. 10. Express F = AB + CD as a canonical (i) Sum of Product form (SOP) (ii) Product of Sum form (POS) 11. Repeat Q. 10 for the followings. (i) X = AB + BC (ii) F = r + S(t + r) + St (iii) R = (W + X) (Y + Z) (iv) T = L + M (NM + ML) 12. Show how NAND gates can be used to build the logic circuit for (i) Y = A + BC (ii) Y = AB + CD 13. Repeat Q. 12. for NOR gates. 14. Convert the following to other canonical form (i) F = (1, 5, 6 ) (ii) F = (1, 5, 7, 8, 14, 15) 15. Prove that the sum of all minterms of a Boolean function of 3 variables is 1. 16. Prove that the product of all minterms of a Boolean function of 3 variables is 0. 17. Minimize the following switching functions using Karnaugh Map. List all prime implicants and essential prime implicants (nonredundant group). (i) F = (1, 3, 5, 6, 7) (ii) F = (0, 1, 3, 6, 14, 15) (iii) F = (0, 1, 2, 5, 7, 10, 12) (iv) F = (2, 7, 8, 10, 15) (v) F = (2, 7, 9, 14, 15) + d (0, 3, (10) (vi) F = (5, 7, 9, 10, 15) + d (1, 3, 11, 14) 18. Simplify the following non canonical expressions using K– map. (i) F = VW + VWY + VWZ (ii) F = YZ + WXY + WXY + XYZ 19. Simplify the following Boolean functions by Quine McCluskey Method. (i) F = (1, 3, 5, 8, 10, 14) (ii) F = (1, 9, 10, 16, 20) + d (14, 29, 30) (iii) F = (2, 8, 9, 19, 25, 27) + d (28, 30). (iv) F = (0, 8, 14, 19, 31, 52, 58) 20. Give logical design of 2x4 decoders. Realize half adder using above. 21. Show how a full adder can be converted to a full subtractor with the addition of one inverter circuit. 22. One full adder can be realized from two half adder and OR gate. Verify from 1st principle. 23. Repeat Q. 22 for one full subtractor. 24. What are the drawbacks of conventional full adder? How these are minimized in carry look ahead adder? 25. What are the differences between combinational and sequential logic circuits? 26 Explain following with diagram: (i) Clocked SR F/F (ii) Clocked J.K. F/F (iii) Clocked D F/f (iv) Clocked T F/F 27. Repeat Q.52 to positive and negative edge triggering. 27. Explain the role of present and clear in FLIP-FLOPS. 28. Construct the excitation table and write the characteristic equations for the following FLIP-FLOPS: (i) S-R F/F (ii) J-K F/F (iii) T F/F 29. What is race ground condition in J-K F/F? Show how it can be overcome in Master-Slave J-K F/F. 30. Convert an S-R F/F to a J-K F/F waning excitation table.