MonolithIC 3D ICs by u9Zdh3

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									MonolithIC 3D ICs

    October 2012




    MonolithIC 3D Inc. , Patents Pending     1
      MonolithIC 3D Inc. , Patents Pending
 Chapter 1
Monolithic 3D




  MonolithIC 3D Inc. Patents Pending   2
3D ICs at a glance

       A 3D Integrated Circuit is a chip that has active
electronic components stacked on one or more layers
that are integrated both vertically and horizontally
forming a single circuit.



Manufacturing technologies:
-Monolithic
-TSV based stacking
-Chip Stacking w/wire bonding


                     MonolithIC 3D Inc, Patents Pending   3
MonolithIC 3D

        A technology breakthrough allows the fabrication of
semiconductor devices with multiple thin tiers (<1um) of copper
connected active devices utilizing conventional fab equipment.
MonolithIC 3D Inc. offers solutions for logic, memory and electro-
optic technologies, with significant benefits for cost, power and
operating speed.




                         MonolithIC 3D Inc. , Patents Pending    4
  Comparison of Through-Silicon Via (TSV) 3D
   Technology and Monolithic 3D Technology

          The semiconductor industry is actively pursuing 3D Integrated Circuits
(3D-ICs) with Through-Silicon Via (TSV) technology (Figure 1). This can also
be called a parallel 3D process.
          As shown in Figure 2, the International Technology Roadmap for
Semiconductors (ITRS) projects TSV pitch remaining in the range of several
microns, while on-chip interconnect pitch is in the range of 100nm.
          The TSV pitch will not reduce appreciably in the future due to bonder
alignment limitations (0.5-1um) and stacked silicon layer thickness (6-10um).
          While the micron-ranged TSV pitches may provide enough vertical
connections for stacking memory atop processors and memory-on-memory
stacking, they may not be enough to significantly mitigate the well-known on-
chip interconnect problems.
          Monolithic 3D-ICs offer through-silicon connections with <50nm
diameter and therefore provide 10,000 times the areal density of TSV
technology.

                              MonolithIC 3D Inc. , Patents Pending             5
          Typical TSV process

                                                             Figure 1
                                Processed
                                Top Wafer

TSV
                                                           TSV


    Align and bond


                               Processed
                                Bottom
                                 Wafer



               TSV diameter typically ~5um
     Limited by alignment accuracy and silicon thickness
                     MonolithIC 3D Inc. Patents Pending                6
   Two Types of 3D Technology
                 3D-TSV                                                        Monolithic 3D
   Transistors made on separate wafers                        Transistors made monolithically atop
   @ high temp., then thin + align + bond                        wiring (@ sub-400oC for logic)



10um-
50um
                                                                                                     100
                                                                                                     nm




              TSV pitch > 1um*                                                TSV pitch ~ 50-100nm

                           * [Reference: P. Franzon: Tutorial at IEEE 3D-IC Conference 2011]         7
              Figure 2
ITRS Roadmap compared to monolithic 3D




              MonolithIC 3D Inc. , Patents Pending   8
TSV (parallel) vs. Monolithic (sequential)




        Source: CEA Leti Semicon West 2012 presentation
                       MonolithIC 3D Inc. , Patents Pending   9
The Monolithic 3D Challenge


 Once copper or aluminum is added on for bottom
  layer interconnect, the process temperatures need to
  be limited to less than 400ºC !!!
    Forming single crystal silicon requires ~1,200ºC
    Forming transistors in single crystal silicon requires ~800ºC


 The TSV solution overcame the temperature challenge by
  forming the second tier transistors on an independent wafer,
  then thinning and bonding it over the bottom wafer (‘parallel’)
       The limitations:
    Wafer to wafer misalignment ~ 1µ
    Overlaying wafer could not be thinned to less than 50µ
The Monolithic 3D Innovation

   Utilize Ion-Cut (‘Smart-Cut’) to transfer a thin (<100nm) single
    crystal layer on top of the bottom (base) wafer
     Form the cut at less than 400ºC *
         Use co-implant
         Use mechanically assisted cleaving
     Form the bonding at less than 400ºC *
    * See details at: Low Temperature Cleaving, Low Temperature Wafer
        Direct Bonding

   Split the transistor processing to two portions
     High temperature process portion (ion implant and activation) to be
       done before the Ion-Cut
     Low temperature (<400°C) process portion (etch and deposition) to be
       done after layer transfer
    See details in the following slides:
Monolithic 3D ICs




        Using SmartCut technology - the ion cutting process that
Soitec uses to make SOI wafers for AMD and IBM (millions of
wafers had utilized the process over the last 20 years) - to stack
up consecutive layers of active silicon (bond first and then cut).
Soitec’s Smart Cut Patented* Flow (follow this link for video).




     *Soitec’s fundamental patent US 5,374,564 expired Sep. 15, 2012

                            MonolithIC 3D Inc. , Patents Pending       12
Monolithic 3D ICs


        Ion cutting: the key idea is that if you implant a thin layer
of H+ ions into a single crystal of silicon, the ions will weaken the
bonds between the neighboring silicon atoms, creating a fracture
plane (Figure 3). Judicious force will then precisely break the
wafer at the plane of the H+ implant, allowing you to in-effect
peel off very thin layer. This technique is currently being used to
produce the most advanced transistors (Fully Depleted SOI,
UTBB transistors – Ultra Thin Body and BOX), forming
monocrystalline silicon layers that are less than 10nm thick.




                          MonolithIC 3D Inc. , Patents Pending     13
                              Figure 3
 Using ion-cutting to place a thin layer of monocrystalline silicon
  above a processed (transistors and metallization) base wafer

                                                                               Cleave using <400oC
                   Hydrogen implant                                             anneal or sideways
 Oxide                                                Flip top layer and
                      of top layer                                            mechanical force. CMP.
  p- Si                                            bond to bottom layer

Top layer
                       Oxide
                                     H                            p- Si                          p- Si
                        p- Si                                             H
                                                               Oxide                  Oxide
  Oxide                                                        Oxide                  Oxide




Bottom layer
            Similar process (bulk-to-bulk) used for manufacturing all SOI wafers today

                                MonolithIC 3D Inc. , Patents Pending                            14
    Chapter 2
Monolithic 3D RCAT




     MonolithIC 3D Inc. Patents Pending   15
MonolithIC 3D – The RCAT path

The Recessed Channel Array Transistor (RCAT) fits very
nicely into the hot-cold process flow partition
RCAT is the transistor used in commercial DRAM as its 3D
channel overcomes the short channel effect
  Used in DRAM production @ 90nm, 60nm, 50nm nodes
  Higher capacitance, but less leakage, same drive current


 The following slides present the flow to process an RCAT
       without exceeding the 400ºC temperature limit




                            MonolithIC 3D Inc. , Patents Pending   16
RCAT – a monolithic process flow


          Using a new wafer, construct dopant regions in top ~100nm
                          and activate at ~1000ºC



                                                                Oxide

                  P-
       ~100nm
                  N+


  Wafer, ~700µm   P-




                         MonolithIC 3D Inc. , Patents Pending           17
Implant Hydrogen for Ion-Cut




                                                    H+


             Oxide
       ~100nm    P-
                 N+


  Wafer, ~700µm   P-




                       MonolithIC 3D Inc. Patents Pending   18
            Hydrogen cleave plane
      for Ion-Cut formed in donor wafer




           Oxide
             P-
     ~100nm                                               H+
             N+                                                ~10nm


Wafer, ~700µm   P-




                     MonolithIC 3D Inc. Patents Pending            19
           Flip over and bond
the donor wafer to the base (acceptor) wafer


   Donor Wafer,
     ~700µm

                  N+
                                                             H+
        ~100nm
                   P-
               Oxide

1µ Top Portion of
  Base Wafer




   Base Wafer,
     ~700µm

                        MonolithIC 3D Inc. Patents Pending        20
Perform Ion-Cut Cleave




                    N+
        ~100nm      P-
                                                              Oxide

1µ Top Portion of
  Base Wafer

                         MonolithIC 3D Inc. Patents Pending


    Base Wafer
     ~700µm
                                                                      21
Complete Ion-Cut



       ~100nm        N+
                     P-
                                                               Oxide

 1µ Top Portion of
   Base Wafer

                          MonolithIC 3D Inc. Patents Pending




     Base Wafer
      ~700µm


                                                                       22
Etch Isolation regions as the first step to define
RCAT transistors


         ~100nm      N+
                     P-
                                                               Oxide

 1µ Top Portion of
   Base Wafer

                          MonolithIC 3D Inc. Patents Pending




     Base Wafer
      ~700µm


                                                                       23
Fill isolation regions (STI-Shallow Trench
Isolation) with Oxide, and CMP


         ~100nm      N+
                     P-
                                                               Oxide

 1µ Top Portion of
   Base Wafer


                          MonolithIC 3D Inc. Patents Pending




    Base Wafer
     ~700µm


                                                                   24
Etch RCAT Gate Regions

                                                               Gate region

        ~100nm       N+
                     P-
                                                                             Oxide

 1µ Top Portion of
   Base Wafer


                          MonolithIC 3D Inc. Patents Pending




    Base Wafer
     ~700µm


                                                                                 25
Form Gate Oxide



         ~100nm      N+
                     P-
                                                               Oxide

 1µ Top Portion of
   Base Wafer


                          MonolithIC 3D Inc. Patents Pending




     Base Wafer
      ~700µm


                                                                   26
Form Gate Electrode



         ~100nm      N+
                     P-
                                                               Oxide

 1µ Top Portion of
   Base Wafer


                          MonolithIC 3D Inc. Patents Pending




     Base Wafer
      ~700µm


                                                                       27
Add Dielectric and CMP



        ~100nm       N+
                     P-
                                                               Oxide

 1µ Top Portion of
   Base Wafer

                          MonolithIC 3D Inc. Patents Pending




    Base Wafer
     ~700µm


                                                                       28
Etch Thru-Layer-Via and
RCAT Transistor Contacts


         ~100nm      N+
                     P-
                                                               Oxide

 1µ Top Portion of
   Base Wafer


                          MonolithIC 3D Inc. Patents Pending




      Base Wafer
       ~700µm


                                                                       29
Fill in Copper



        ~100nm       N+
                     P-
                                                               Oxide

 1µ Top Portion of
   Base Wafer

                          MonolithIC 3D Inc. Patents Pending




     Base Wafer
      ~700µm


                                                                   30
 Add more layers monolithically




            ~100nm      N+
                        P-
                                                                  Oxide


            ~100nm      N+
                        P-
                                                                  Oxide
  1µ Top Portion of
Base (acceptor) Wafer


        Base Wafer
         ~700µm

                             MonolithIC 3D Inc. Patents Pending           31
    Chapter 3
Monolithic 3D HKMG




     MonolithIC 3D Inc. Patents Pending   32
Technology

The monolithic 3D IC technology is applied to produce
monolithically stacked high performance High-k Metal Gate
(HKMG) devices, the world’s most advanced production
                         transistors.

3D Monolithic State-of-the-Art transistors are formed with ion-cut
applied to a gate-last process, combined with a low
temperature face-up layer transfer, repeating layouts, and an
innovative   inter-layer   via     (ILV)    alignment    scheme.

Monolithic 3D IC provides a path to reduce logic, SOC, and
memory costs without investing in expensive scaling down.


                         MonolithIC 3D Inc. Patents Pending      33
 On the donor wafer, fabricate standard dummy
 gates with oxide and poly-Si; >900ºC OK




                     NMOS                    Poly         PMOS
                                             Oxide




~700µm Donor Wafer

                                                          Silicon




                     MonolithIC 3D Inc. Patents Pending             34
 Form transistor source/drain




                     NMOS                    Poly         PMOS
                                             Oxide




~700µm Donor Wafer

                                                          Silicon




                     MonolithIC 3D Inc. Patents Pending             35
 Form inter layer dielectric (ILD), do high temp
 anneals, CMP near to transistor tops


                                                                                         CMP near to
                                                                                        top of dummy
                     S/D Implant
                                                                        ILD                 gates
                                   NMOS                                       PMOS




~700µm Donor Wafer

                                                                              Silicon




                                   MonolithIC 3D Inc. Patents Pending                             36
 Implant hydrogen to generate cleave plane




                     NMOS                                 PMOS




~700µm Donor Wafer

                                                          Silicon




                     MonolithIC 3D Inc. Patents Pending             37
 Implant hydrogen to generate cleave plane




                     NMOS                                 PMOS




~700µm Donor Wafer

                                                          Silicon




                     MonolithIC 3D Inc. Patents Pending             38
 Implant hydrogen to generate cleave plane




                     NMOS                                 PMOS




                                                                    H+
~700µm Donor Wafer

                                                          Silicon




                     MonolithIC 3D Inc. Patents Pending                  39
 Bond donor wafer to carrier wafer



  ~700µm Carrier Wafer




                                                                        H+
~700µm Donor Wafer


                                                              Silicon




                         MonolithIC 3D Inc. Patents Pending                  40
 Cleave to remove bulk of donor wafer



  ~700µm Carrier Wafer




         Transferred
         Donor Layer
         (nm scale)                                           Silicon
                                                                        H+



~700µm Donor Wafer
                                                              Silicon

                         MonolithIC 3D Inc. Patents Pending                  41
CMP to STI



     ~700µm
   Carrier Wafer



    Transferred
    Donor Layer
     (<100nm)                                    STI




                   MonolithIC 3D Inc. Patents Pending   42
Deposit oxide, ox-ox bond carrier structure to
base wafer that has transistors & circuits


      ~700µm
    Carrier Wafer



     Transferred
     Donor Layer
      (<100nm)                                   STI



                                                                Oxide-oxide bond


       ~700µm
      Base Wafer     NMOS                                PMOS

                    MonolithIC 3D Inc. Patents Pending                   43
Remove carrier wafer


     ~700µm
   Carrier Wafer




     Transferred
     Donor Layer
      (<100nm)


                                                               Oxide-oxide bond


       ~700µm
      Base Wafer    NMOS                                PMOS

                   MonolithIC 3D Inc. Patents Pending                   44
Carrier wafer had been removed




     Transferred
     Donor Layer
      (<100nm)



                                                               Oxide-oxide bond


      ~700µm
     Base Wafer     NMOS                                PMOS

                   MonolithIC 3D Inc. Patents Pending                   45
 CMP to expose gate stacks. Replace dummy gate
 stacks with Hafnium Oxide & Metal (HKMG)at low temp

Note: Replacing the gate oxide and gate electrode results in a gate stack that is not damaged
by the H+ implant


       Transferred
       Donor Layer
        (<100nm)


                                                                            Oxide-oxide bond

         ~700µm
        Base Wafer               NMOS                                PMOS

                                MonolithIC 3D Inc. Patents Pending




                                                                                               46
Form inter layer via (ILV) through oxide only
(similar to standard via)

Note: The second mono-crystal layer is very thin (<100nm) and has a vertical oxide corridor; hence, the
via through it (TLV) may be constructed and sized similarly to other vias in the normal metal stack.



      Transferred
      Donor Layer
       (<100nm)


                                                                                     Oxide-oxide bond

        ~700µm
       Base Wafer
                                   NMOS                                PMOS

                                  MonolithIC 3D Inc. Patents Pending




                                                                                                        47
Form top layer interconnect and
connect layers with inter layer via


                                                                        ILV

   Transferred
   Donor Layer
    (<100nm)


                                                                     Oxide-oxide bond


    ~700µm
   Base Wafer     NMOS                                        PMOS

                 MonolithIC 3D Inc. Patents Pending




                         MonolithIC 3D Inc. Patents Pending                         48
Benefits for RCAT and HKMG

• Maximum State-of-the-Art transistor performance on
 multi-strata
• 2x lower power
• 2x smaller silicon area
• 4x smaller footprint
• Performance of single crystal silicon transistors on all
 layers in the 3DIC
• Scalable: scales normally with equipment capability
• Forestalls next gen litho-tool risk
• High density of vertical interconnects enable innovative
 architectures, repair, and redundancy

                       MonolithIC 3D Inc. Patents Pending    49
              Chapter 4
         Monolithic 3D RC-JLT
(Recessed-Channel Junction-Less Transistor)




               MonolithIC 3D Inc. Patents Pending   50
Technology

Monolithic 3D IC technology is applied to producing monolithically stacked low
leakage Recessed Channel Junction-Less Transistors (RC-JLTs).
Junction-less (gated resistor) transistors are very simple to manufacture, and
they scale easily to devices below 20nm:

•   Bulk Device, not surface

•   Fully Depleted channel

•   Simple alternative to FinFET

Superior contact resistance is achieved with the heavier doped top layer. The
RCAT style transistor structure provides ultra-low leakage.

Monolithic 3D IC provides a path to reduce logic, SOC, and memory costs
without investing in expensive scaling down.

                               MonolithIC 3D Inc. Patents Pending               51
RCJLT – a monolithic process flow


          Using a new wafer, construct dopant regions in top ~100nm
                          and activate at ~1000ºC



                                                                Oxide

                   N+
       ~100nm
                  N++


  Wafer, ~700µm   P-




                         MonolithIC 3D Inc. , Patents Pending           52
Implant Hydrogen for Ion-Cut




                                                    H+


             Oxide
       ~100nm N+
               N++


  Wafer, ~700µm   P-




                       MonolithIC 3D Inc. Patents Pending   53
            Hydrogen cleave plane
      for Ion-Cut formed in donor wafer




           Oxide
             N+
     ~100nm                                               H+
            N++                                                ~10nm


Wafer, ~700µm   P-




                     MonolithIC 3D Inc. Patents Pending            54
           Flip over and bond
the donor wafer to the base (acceptor) wafer


   Donor Wafer,
                    P-
     ~700µm


        ~100nm N++
                                                              H+
               N+
             Oxide

1µ Top Portion of
  Base Wafer




   Base Wafer,
     ~700µm

                         MonolithIC 3D Inc. Patents Pending        55
Perform Ion-Cut Cleave




               N++
        ~100nm N+
                                                          Oxide

1µ Top Portion of
  Base Wafer

                     MonolithIC 3D Inc. Patents Pending


    Base Wafer
     ~700µm
                                                                  56
Complete Ion-Cut



       ~100nm        N++
                     N+
                                                                Oxide

 1µ Top Portion of
   Base Wafer

                           MonolithIC 3D Inc. Patents Pending




     Base Wafer
      ~700µm


                                                                        57
Etch Isolation regions as the first step to define
RCAT transistors


         ~100nm      N++
                     N+
                                                                Oxide

 1µ Top Portion of
   Base Wafer

                           MonolithIC 3D Inc. Patents Pending




     Base Wafer
      ~700µm


                                                                        58
Fill isolation regions (STI-Shallow Trench
Isolation) with Oxide, and CMP


         ~100nm N++
                N+
                                                           Oxide

 1µ Top Portion of
   Base Wafer


                      MonolithIC 3D Inc. Patents Pending




    Base Wafer
     ~700µm


                                                               59
Etch RCAT Gate Regions

                                                                Gate region

        ~100nm       N++
                     N+
                                                                              Oxide

 1µ Top Portion of
   Base Wafer


                           MonolithIC 3D Inc. Patents Pending




    Base Wafer
     ~700µm


                                                                                  60
Form Gate Oxide



         ~100nm      N++
                     N+
                                                                Oxide

 1µ Top Portion of
   Base Wafer


                           MonolithIC 3D Inc. Patents Pending




     Base Wafer
      ~700µm


                                                                    61
Form Gate Electrode



         ~100nm      N++
                     N+
                                                                Oxide

 1µ Top Portion of
   Base Wafer


                           MonolithIC 3D Inc. Patents Pending




     Base Wafer
      ~700µm


                                                                        62
Add Dielectric and CMP



        ~100nm       N++
                     N+
                                                                Oxide

 1µ Top Portion of
   Base Wafer

                           MonolithIC 3D Inc. Patents Pending




    Base Wafer
     ~700µm


                                                                        63
Etch Thru-Layer-Via and
RCJLT Transistor Contacts


         ~100nm      N++
                     N+
                                                                Oxide

 1µ Top Portion of
   Base Wafer


                           MonolithIC 3D Inc. Patents Pending




      Base Wafer
       ~700µm


                                                                        64
Fill in Copper



        ~100nm       N++
                     N+
                                                                Oxide

 1µ Top Portion of
   Base Wafer

                           MonolithIC 3D Inc. Patents Pending




     Base Wafer
      ~700µm


                                                                        65
 Add more layers monolithically




            ~100nm      N++
                        N+
                                                                   Oxide


            ~100nm      N++
                        N+
                                                                   Oxide
  1µ Top Portion of
Base (acceptor) Wafer


        Base Wafer
         ~700µm

                              MonolithIC 3D Inc. Patents Pending           66
Benefits for RCJLT

• 2x lower power
• 2x smaller silicon area
• 4x smaller footprint
• Layer to layer interconnect density at close to full lithographic resolution
  and alignment
• Performance of single crystal silicon transistors on all layers in the 3D IC
• Scalable: scales naturally with equipment capability
• Forestalls next gen litho-tool risk
• Also useful as Anti-Fuse FPGA programming transistors: programmable
         interconnect is 10x-50x smaller & lower power than SRAM FPGA
• Base logic circuits could be UT-BBOX, FinFET, or JLT CMOS logic devices

                                MonolithIC 3D Inc. Patents Pending               67
RC-JLT flow: Summary

Create a layer of Recessed Channel Junction-Less Transistors (RC-JLTs), a
junction-less version of the RCAT used in DRAMs, by activating dopants at
~1000°C before wafer bonding to the CMOS substrate and cleaving, thereby
leaving a very thin doped stack layer from which transistors are completed,
utilizing less than 400°C etch and deposition processes.




                             MonolithIC 3D Inc. Patents Pending          68

								
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