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					Andes (晶心科技) SoC Development
        Solution Training Course
                      (For University)




                                WWW.ANDESTECH.COM
Outline
ANDES自主研發處理器簡介
ADP-XC5FF76 Evaluation Board 介紹
AndeScore指令集架構
AndeSight整合開發環境操作介紹
嵌入式軟體程式設計原理
Hello World
GPIO控制原理
SUM控制原理
MP3
ADP-XC5FF76 Evaluation Board Totally Labs.
使用AndESLive開發數位相框之參考設計
 Page 2             ANDES Confidential
     ANDES自主研發處理器簡介




Page 3    ANDES Confidential
Introduction

What are embedded systems?
Challenges in embedded system design.
Design methodologies.




 Page 4         ANDES Confidential
Embedding a computer



                       output             analog


                        input             analog
            CPU



                        mem
          embedded
          computer


 Page 5              ANDES Confidential
Embedding a computer (cont.)
Examples
  Personal digital assistant (PDA).
  Printer.
  GPS
  Cell phone.
  Automobile: engine, brakes, etc.
  Television.
  Household appliances.




   Page 6              ANDES Confidential
  MCU Connect Your Life
                                                                                   Consumer
                                                                                  Electronics
                                                                                    Domain

                                                                Media Center PC
                                                                                 BT Keyboard
                                                                                 & Mouse
                                             Digital Cable
                                             Ready TV
                                                               Media Phone
                    PC            Media Player     Cable STB
                                                                     DVD+PVR
       Printer                                                                         HDTV
                                        Camera

                 802.11                          MP3      Game System
                 Router                                                        IP Home Stereo
                                                 Player


    Network                                                                           BT Stereo HS
    Storage               Notebook PC                                        Mobile
                                                                             Phone
                                                          VoIP
                                                          Phone


                 MAC



Internet
    Page 7
                  PC Domain Confidential
                        ANDES
Characteristics of Embedded Systems

Sophisticated functionality.
Real-time operation.
Low manufacturing cost.
Low power.
Designed to tight deadlines by small teams.




 Page 8             ANDES Confidential
Design methodologies

A procedure for designing a system.
Understanding your methodology helps you
 ensure you didn’t skip anything.
Compilers, software engineering tools, computer-
 aided design (CAD) tools, etc., can be used to:




 Page 9             ANDES Confidential
 SoC Development Flow
Andes/Partners’ solution
  Customers’ Design
                                                                           Target SW
                                     Compiler
                                                                        Application Layers
                           SW
            SoC                  Assembler/Linker                         Middle ware
          Definition                 Debugger                     Generic Drivers   App Drivers
                                   Tool chains                      OS/Kernel         Libraries
                     HW
                                                                      Andes Virtual Platform
                                Application Models                      Your Virtual SoC
         High Level             Essential IP’s Models
         Modeling
                                    AndeScore
                                  Customer SoC

                                                                         Evaluation Board
                                  Application IPs
            Logic
                                   Essential IPs
            Design
                                    AndeScore                                       SoC
                                  Customer SoC
    Add AICE™, ADP-AG101™, and ADP™-XC5 in v1.3.1

     Page 10                                 ANDES Confidential
Summary
Embedded computers are all around us.
     Many systems have complex embedded hardware and
      software.
Embedded systems pose many design
 challenges: design time, deadlines, power, etc.
Design methodologies help us manage the
 design process.




 Page 11              ANDES Confidential
Overview of Andes Technology

                             Andes Highlights

• Founded in 2005 March
•First tier investors and partners (Government VC, MediaTek, and Faraday)
• USD$20M capital for financial stability

                              Andes’ Mission
• Provide the best processor-based SoC solution

                           Market Opportunities
• The demand of multi-standard and multi-functions for different applications
  due to the device convergence of consumer electronics
• The BRICs demand a big volume for low cost products
• Fast growing market in Asia, world-wide IC designs move to Asia



 Page 12                        ANDES Confidential
Andes’ Main Lines of Business

                  AndeStar™                               AndesCore™
   Andes 16/32-bit Mixable ISA                            CPU Core Family




   AndESLive™                         Andes                         AndeShape™
      ESL Integrated                Embedded™                       SoC + EVB + ICE
 Virtual Environment




                 AndeSight™                               AndeSoft™
           Integrated Development                         Optimized Target SW such as
                      Environment                         Linux/RTOS, Middleware, and
                                                          Application Software.


 Page 13                             ANDES Confidential
Feature Set

AndeSight™                   AndESLive™
       Coder
                                     Pre-built Models of
       Debugger                      AndeScore™
       Profiler                     Per-built peripheral IPs
       Target Manager                and Bus
Toolchains                          Virtual SoC Builder
       Complier                     Visibility of debugging
       Assembler                    Simulation of I/O
       Linker                        devices
       Debugger



 Page 14                 ANDES Confidential
AndesCoreTM Market Segments

   MID/Netbook
   MFP
   Networking
   Gateway/Router
   Home entertainment                                   High-end
   Smartphone/Mobile phone

                                                 N12 series
 Portable audio/media player
 DVB/DMB baseband
 DVD                                                          Mid-range
 DSC                                           N10 Series
 Toys, Games

    MCU
    Storage                                                        Low-end
    Automotive control                          N9 Series
    Toys


   Page 15                      ANDES Confidential
 AndesCore™ – Configurable Options
 Cache:                                            Instruction extensions:
    Instruction queue size: 2/4/8                     Audio extensions

    8KB ~ 64KB, 1/2/4 ways                            Performance extensions

    16B/32B cache line size                           Floating co-processor

    Replacement policy: Pseudo LRU                    String processing acceleration
     or random                                         User-defined extensions
 Local Memory:                                     Debugging support:
    Internal or external, 4KB ~ 1MB                   Embedded Debug Module with HW
 Memory Management                                       breakpoints
    Simplest 2/4 partitions                           Embedded Program Tracer

    MPU with 8 segments                               Embedded performance monitor

    MMU                                            Core:
            microTLB size: 4/8 entries                Big/little endian
            mainTLB size: 32/64/128 entries           Static/Dynamic branch prediction
            Page table walking: hardware or           BTB size: 32/64/128/256 entries
             software
                                                       2/3 nested interrupt levels
 Bus interfaces:
                                                       16/32 GPRs
    AHB/AHB-Lite/APB/AMI
                                                       2R1W/3R2W register file
    HSMP bus


   Page 16                                ANDES Confidential
N903: Low-power Cost-efficient Embedded
Controller
 Features:
       Harvard architecture, 5-stage
        pipeline.
       16 general-purpose registers.
       Static branch prediction                                    JTAG/EDM
       Fast MAC
       Hardware divider
       Fully clock gated pipeline                                  N9 uCore
       2-level nested interrupt
       External instruction/data local
        memory interface                            Instr        Instr          Data    Data
       Instruction/data cache                      LM/IF       Cache          Cache    LM/IF
       APB/AHB/AHB-Lite/AMI bus
        interface
       Power management instructions
       45K ~ 110K gate count                                  External Bus Interface
       250MHz @ 130nm
 Applications:
       MCU                                                      APB/AHB/AHB-Lite/AMI
       Storage
       Automotive control
       Toys
   Page 17                                ANDES Confidential
N903 Competition
           Core’s Features                            N903             ARM7TDMI            Cortex-M3
                           Architecture             Harvard            Von Neumann          Harvard
                        Pipeline Stages                 5                    3                  3
                         Instruction Set       16-/32-bit mixable      Thumb/ARM        16-/32-bit mixable
            General-purpose register #                  16                  16                 16
                     Branch prediction                Static               None               Static
              Interrupt latency (Cycle)                 10                24-42                12
                  Data endian support             Big and Little       Big and Little     Big and Little
                                      Bus        APB/AHB/AMI              1 AHB            3 AHB Lite
                             Sleep Mode                Yes                  No                 Yes
            Vectored interrupt support Yes (internal/external)             None           Yes (external)
                             DMIPS/Mhz                1.38                 0.95               1.25
     Core Area (mm2) (TSMC 0.13G)                     *0.42                0.26             0.43/0.21
Core Power (mW/MHz) (TSMC 0.13G)                      *0.06                0.06           0.165/0.084
Max Frequency (Mhz) (TSMC 0.13G)                      *204                 133               135/50
                 DMIPS (TSMC 0.13G)                  281.52               126.35          168.75/62.5
    Cost Performance (DMIPS/mm2)                      670.3                486              393/298
              *TSMC free library with max speed synthesis constraint
 Page 18                                     ANDES Confidential
N1033A: Lowe-power Cost-efficient
Application Processor
 Features:
       Harvard architecture, 5-stage pipeline.
       32 general-purpose registers
       Dynamic branch prediction
       Fast MAC                                             JTAG/EDM                  EPT I/F
       Hardware divider
       Audio acceleration instructions
                                                                      N10 Core +Audio
       Fully clock gated pipeline                        ITLB                                   DTLB
       3-level nested interrupt                                          MMU/MPU
       Instruction/Data local memory
       Instruction/Data cache
                                                       Instruction Instruction         Data       Data
       DMA support for 1-D and 2-D transfer             LM/INF      Cache            Cache      LM/INF
       AHB/AHB-Lite/APB bus
       MMU/MPU
                                                                             DMA
       Power management instructions
 Applications:                                                      External Bus Interface
       Portable audio/media player
       DVB/DMB baseband
       DVD                                             AHB/AHB(D)/AHB-Lite/APB       AHB(I)
       DSC
       Toys, Games



   Page 19                                 ANDES Confidential
N1033A Competition
           Core’s Features                                N1033A           ARM926EJ
                         Pipeline Stages                      5                  5
                          Instruction Set            16-/32-bit mixable       16 or 32
             General-purpose register#                        32                 16
            Dynamic branch prediction                32/64 -Entry BTB           No
                            DMA support                  1D and 2D              No
                         Cache tag index                Physical tag         Virtual tag
            Vectored interrupt support              Yes (64 addresses)          No
              Nested interruption level                       3                 No
                                       Bus      AHB/2AHB/AHB-Lite/APB          2 AHB
                Audio DSP instructions                 > 40 dedicated     Few general DSP
   Max frequency (Mhz) (TSMC 0.13G)                         *280              276/238
            Performance (DMIPS/MHz)                          1.6                1.1
 Core Power (mW/MHz) (TSMC 0.13G)                           *0.12               0.36
       Core area (mm2) (TSMC 0.13G)                          *1.4            1.61/1.45
                   DMIPS (TSMC 0.13G)                        448               303.6
      Cost Performance (DMIPS/MHz)                           320                189
             *TSMC free library with max speed synthesis constraint
 Page 20                                     ANDES Confidential
 N1213 – High Performance Application
 Processor
                                                         Features:
                                                                  Harvard architecture, 8-stage pipeline.
      JTAG/EDM                  EPT I/F                           32 general-purpose registers
                                                                  Dynamic branch prediction.
                                                                  Multiply-add and multiply-subtract
                                                                   instructions.
             N12 Execution Core
                                                                  Divide instructions.
   ITLB                                     DTLB
                                                                  Instruction/Data local memory.
                      MMU                                         Instruction/Data cache.
                                                                  MMU
                                                                  AHB or HSMP(AXI like) bus
Instruction Instruction         Data         Data
                                                                  Power management instructions
  Cache         LM              LM          Cache
                                                         Applications:
                                                                  Portable media player
                          DMA                                     MFP
                                                                  Networking
                                                                  Gateway/Router
              External Bus Interface                              Home entertainment
                                                                  Smartphone/Mobile phone
    AHB                                HSMP



   Page 21                                ANDES Confidential
N1213 Competition
           Core’s Features                              N1213                  ARM1176        MIPS 24K
                          Instruction Set             16-/32-bit mixable           16 or 32        16 or 32

              General-purpose register#                                  32              16               32

            Page Table Support for MMU                      HW and SW             HW only          SW only

                   Interrupt Stack Level                                  3               2                 1

              unaligned memory access                       ld/st multiple        mode bit    ld/st left/right

                   uncached read burst                    use ld multiple             none             none
                            DMA support                            1D/2D                 1D               No
     Core die size (mm2) (TSMC 90G)                                    *1.38      1.95/1.00            *1.44

           Frequency (MHz) (TSMC 90G)                                  *580        620/320              *520

  Core power (mW/MHz) (TSMC 90G)                                       *0.27      0.37/0.18            *0.40

             Performance (DMIPS/MHz)                                    1.37          1.22              1.55

                     DMIPS (TSMC 90G)                                  *795        756/390              *748

     Cost Performance (DMIPS/mm2)                                      576.1         387.7            519.4

              *TSMC free library with max speed synthesis constraint
 Page 22                                     ANDES Confidential
          Pipeline Overview




Page 23         ANDES Confidential
Computer architecture taxonomy
 von Neumann architecture




 Page 24            ANDES Confidential
Computer architecture taxonomy (cont.)
 Harvard architecture


                              address
            data memory
                               data              PC
                                                 CPU
                              address

           program memory      data




 Page 25                    ANDES Confidential
8-stage pipeline



           F1            F2           I1             I2         E1          E2          E3           E4



           Instruction-Fetch        Instruction Issue and   Data Address     Data Access       Instruction Retire and
            First and Second         Register File Read      Generation     First and Second     Result Write Back



           IF1           IF2          ID            RF         AG          DA1         DA2           WB


                                                                            EX

                               Instruction Decode
                                                              MAC1         MAC2




 Page 26                                            ANDES Confidential
Instruction Fetch Stage
 F1 – Instruction Fetch First
          Instruction Tag/Data Arrays
          ITLB Address Translation
          Branch Target Buffer Prediction
 F2 – Instruction Fetch Second
          Instruction Cache Hit Detection
          Cache Way Selection
          Instruction Alignment




    IF1        IF2      ID      RF       AG        DA1   DA2   WB

                                                    EX

                                        MAC1 MAC2

 Page 27                           ANDES Confidential
Instruction Issue Stage

 I1 – Instruction Issue First / Instruction Decode
          32/16-Bit Instruction Decode
          Return Address Stack prediction
 I2 – Instruction Issue Second / Register File Access
          Instruction Issue Logic
          Register File Access




    IF1        IF2       ID      RF        AG        DA1   DA2   WB

                                                      EX

                                          MAC1 MAC2


 Page 28                             ANDES Confidential
Execution Stage
 E1 – Instruction Execute First / Address Generation / MAC First
          Data Access Address Generation
          Multiply Operation (if MAC presents)
 E2 –Instruction Execute Second / Data Access First / MAC Second / ALU
  Execute
          ALU
          Branch/Jump/Return Resolution
          Data Tag/Data arrays
          DTLB address translation
          Accumulation Operation (if MAC presents)
 E3 –Instruction Execute Third / Data Access Second
          Data Cache Hit Detection
          Cache Way Selection
          Data Alignment



    IF1        IF2        ID          RF          AG    DA1   DA2   WB

                                                         EX

                                              MAC1     MAC2

 Page 29                                ANDES Confidential
Write Back Stage

E4 –Instruction Execute Fourth / Write Back
          Interruption Resolution
          Instruction Retire
          Register File Write Back




        IF1    IF2    ID    RF       AG          DA1    DA2   WB

                                                  EX

                                   MAC1          MAC2



 Page 30                    ANDES Confidential
Instruction Fetch Unit
    F1 – Instruction Fetch First
     Instruction Tag/Data Arrays
     ITLB Address Translation
     Branch Target Buffer Prediction


    F2 – Instruction Fetch Second
     Instruction Cache Hit Detection
     Cache Way Selection
     Instruction Alignment




 Page 31                ANDES Confidential
Branch Prediction Overview
 Why is branch prediction required?
     A deep pipeline is required for high speed
     Increasing the number of stages between fetch and branch
      resolution increases the taken-branch penalty
     Prediction allows the penalty to be avoided in the majority of cases
 Why dynamic branch prediction?
     Static branch prediction requires knowledge of the type of branch
      and the target address before a prediction can be made
     This information is not available before the decode stage and this
      would still increase the penalty for all branches
     Dynamic branch prediction is performed at the instruction fetch
      stage based purely on fetch addresses – no knowledge of the
      incoming instructions is required




 Page 32                      ANDES Confidential
Branch Prediction Unit

  Branch Target Buffer (BTB)
        128 entries of 2-bit saturating counters
        Strongly-taken, Weakly-taken, Weakly-not-taken,
         Strongly-not-taken
        128 entries, 32-bit predicted PC and 26-bit address tag
        Call-return and alignment flags
  Return Address Stack (RAS)
        Four entries
  BTB and RAS updated by committing
   branches/jumps


 Page 33                    ANDES Confidential
BTB Instruction Prediction
 BTB predictions are performed based on the previous PC instead of
  the actual instruction decoding information, BTB may make the
  following two mistakes
     Wrongly predicts the non-branch/jump instructions as branch/jump
      instructions
     Wrongly predicts the instruction boundary (32-bit -> 16-bit)
 If these cases are detected, IFU will trigger a BTB instruction
  misprediction in the I1 stage and re-start the program sequence from
  the recovered PC. There will be a 2-cycle penalty introduced here


                  branch                             BTB instruction misprediction
                              F1     F2      I1
                           PC+4      F1      F2               killed

                                  PC+4       F1               killed

                                   Recovered PC    F1     F2           I1



 Page 34                                 ANDES Confidential
RAS Prediction
 When return instructions present in the instruction
  sequence, RAS predictions are performed and the fetch
  sequence is changed to the predicted PC.
 Since the RAS prediction is performed in the I1 stage.
  There will be a 2-cycle penalty in the case of return
  instructions since the sequential fetches in between will
  not be used.

            return                                 RAS prediction
                        F1     F2      I1
                     PC+4      F1     F2              killed

                            PC+4      F1              killed

                                    target   F1    F2          I1


 Page 35                            ANDES Confidential
Branch Miss-Prediction
 In N12 processor core, the resolution of the branch/return instructions
  is performed by the ALU in the E2 stage and will be used by the IFU
  in the next (F1) stage. In this case, the misprediction penalty will be 5
  cycles.


           branch      F1     F2       I1   I2     E1      E2    predicted taken (wrong)

                    PC+4      F1      F2    I1     I2      E1
                                                                      killed
                           PC+4       F1    F2     I1      I2
                                   target   F1     F2      I1
                                                                       killed
                                                   F1      F2
                                                           F1
                                                    redirect    F1    F2        I1         I2




 Page 36                                         ANDES Confidential
          Cache




Page 37   ANDES Confidential
Cache and CPU



                 address                data
                                                    cache

                           controller
                             cache                           main
           CPU
                                                            memory
                                               address
                   data                          data




 Page 38                           ANDES Confidential
Cache operation
 Many main memory locations are mapped onto one cache
  entry.
 May have caches for:
     instructions;
     data;
     data + instructions (unified).




 Page 39                       ANDES Confidential
Multiple levels of cache




           CPU       L1 cache          L2 cache




 Page 40          ANDES Confidential
Replacement policy
 Replacement policy: strategy for choosing which cache
  entry to throw out to make room for a new memory
  location.
 Two popular strategies:
     Random.
     Least-recently used (LRU).




 Page 41                    ANDES Confidential
Write operations
 Write-through: immediately copy write to main memory.
 Write-back: write to main memory only when location is
  removed from cache.




 Page 42                ANDES Confidential
Improving Cache Performance

Goal: reduce the Average Memory Access Time
 (AMAT)
     AMAT = Hit Time + Miss Rate * Miss Penalty
Approaches
     Reduce Hit Time
     Reduce or Miss Penalty
     Reduce Miss Rate
Notes
     There may be conflicting goals
     Keep track of clock cycle time, area, and power
      consumption


 Page 43                   ANDES Confidential
Tuning Cache Parameters
 Size:
     Must be large enough to fit working set (temporal locality)
     If too big, then hit time degrades
 Associativity
     Need large to avoid conflicts, but 4-8 way is as good a FA
     If too big, then hit time degrades
 Block
     Need large to exploit spatial locality & reduce tag overhead
     If too large, few blocks ⇒ higher misses & miss penalty



    Configurable architecture allows designers to make
           the best performance/cost trade-offs

 Page 44                      ANDES Confidential
Cache configuration

 Cache line per way
    128/256/512/1024
 Cache ways
    2/4 ways
 Cache line size
    16B/32B
 Cache size combination
    8KB/16KB/32KB/64KB
 Replacement policy
    Pseudo LRU (default)
      • 3-BIT per cache line
    Random
      • 2-bit pre cache line


 Page 45                   ANDES Confidential
Cache control— CCTL instruction
 I cache control
       Fill and lock
       Unlock
       Invalidate
       Read/write tag
       Read/write word data
 D cache control
       Invalidate
       Write back
       Read/write tag
       Read/write word data




 Page 46                       ANDES Confidential
Cache data flow


                         I-Cache



                 Uncached Instruction/data
          CPU   Uncached write/write-through       Ext Memory

                                   Write back


                         D-Cache                D-Cache refill




Page 47                  ANDES Confidential
          Memory Management Units
                  (MMU)




Page 48           ANDES Confidential
MMU Functionality
 Memory management unit (MMU) translates addresses


                 logical                  physical
                 address     memory       address
           CPU              management
                               unit




 Page 49             ANDES Confidential
MMU Functionality
 Virtual memory addressing
          Better memory allocation, less fragmentation
          Allows shared memory
          Dynamic loading

 Memory protection (read/write/execute)
          Different permission flags for kernel/user mode
          OS typically runs in kernel mode
          Applications run in user mode

 Cache control (cached/uncached)
          Accesses to peripherals and other processors needs to be
           uncached.




 Page 50                        ANDES Confidential
Multi-Level Page Tables

 1st level page table
     A page table for page
      tables.
 2nd level page table
     Allocated only if one of its
      entries corresponds to
      allocated data.
 Advantages:
     Page table space
      proportional to allocated
      memory
     Can page the page tables.
 Disadvantage:
     Complexity, especially if
      TLB misses handled in
      hardware.




 Page 51                             ANDES Confidential
uITLB/uDTLB Specifications

4/8entrys fully associative
Subset of MTLB contents
Context ID checking support
Pseudo-LRU replacement policy
D type Flip-Flop PTE storage
1T check hit or miss




 Page 52          ANDES Confidential
MTLB (Main TLB) Specifications

32/64/128-entry 4-way set-associative
Support 4K/8K/1M page VA size
TLB locking support
Pseudo-LRU replacement policy
SRAM base PTE storage




 Page 53            ANDES Confidential
MMU Architecture

                                              M-TLB entry index
       IFU              LSU
                                            N(=32) sets k(=4) ways =128-entry
      4/8 I-uTLB      4/8 D-uTLB                 6   Way number        5    4   Set number 0
                                                 Log2(N*K)-1        Log2(N) Log2(N)-1      0


                M-TLB arbiter

                                                        M-TLB Tag          M-TLB data

                   32x4 M-TLB


                    HPTWK                               M-TLB Tag          M-TLB data




             Bus interface unit
 Page 54                           ANDES Confidential
Address Space Attribute

Defines various properties
     Cachebility/Bufferability requirement/hint
     Access permissions
     May even Ordering requirement
Translated: defined in Page Table Entry
Non-translated: Address space attributes are
 defined in MMU control register




 Page 55                    ANDES Confidential
Cachebility & Bufferability
Device space
Device space, write coalesable
Non-cacheable memory
Cacheable, write-back, write-allocate, shared
 memory
Cacheable, write-through, no-write-allocate,
 shared memory
Cacheable, write-back, write allocate, non-shared
 memory
Cacheable, write-through, no-write-allocate, non-
 shared memory

 Page 56            ANDES Confidential
Virtual address translation process
                         Virtual Address Translation Process


                                                Virtual address



                                                                    Found
                                                 Search TLB

                                                        Not found


                      TLB fill       No
                                             Hardware Page Table
                     exception                Walker Enabled?

                                                         Yes


                                                 Load L1PTE


             Non-Leaf PTE not    No
                 present                        L1PTE Valid?
                exception
                                                         Yes
               Hardware Page Table
                    Walker                       Load L2PTE


                                 Yes
                                               Check Exceptions
           Restart                                       No

                                                Insert L2PTE
                                                  into TLB
    Leaf PTE not present
   Read protection violation
   Write protection violation                  Check Exceptions
        Page modified                Yes
     Non-executable page                                No
           Access bit                                                       Optional
           exception
                                               Physical address

 Page 57                                   ANDES Confidential
          Local Memory
              (LM)




Page 58       ANDES Confidential
Local Memory


                 VA   uITLB             PA    Icache
           IFU

                               IBPA
                                               ILM

           BIU        LDMA

                                               DLM
                                       DBPA

           LSU   VA   uDTLB             PA    D-cache


 Page 59               ANDES Confidential
Data Local Memory Access Modes

 Normal access mode
     The processor core and the DMA engine will see the same DLM
      address space and it is possible for them to access the same DLM
      location at the same time using the same address.
 Double-Buffer access mode
     Only DLM is divided into two banks
     The processor pipeline is directed to access one bank
     The DMA engine is directed to access the other bank.




 Page 60                     ANDES Confidential
Local memory constraint

 Base physical address has to be aligned on 1MB
  boundary for any smaller than or equal to 1MB.
 Any access outside of the local memory within
  the allocated 1MB region will cause a
  “Nonexistent local memory address” exception.
 The local memory needs to be mapped onto an
  uncacheable region; otherwise,
  UPREDICTABLE behavior may happen to the
  local memory content.



 Page 61           ANDES Confidential
          Direct Memory Access
                  (DMA)




Page 62         ANDES Confidential
DMA overview
                 Two channels
Local Memory     One active channel
                 Programmed using physical
                  addressing
                 For both instruction and data local
     DMA          memory
   Controller    External address can be
                  incremented with stride
                 Optional 2-D Element Transfer
                  (2DET) feature which provides an
                  easy way to transfer two-
Ext. Memory       dimensional blocks from external
                  memory.


 Page 63         ANDES Confidential
LMDMA Double Buffer Mode



                   Core
                 Pipeline


                                                                 External
                                                                 Memory
              Local Memory
                 Bank 0

              Local Memory
                                               DMA Engine
                 Bank 1




           Computation
           Data Movement
           Bank Switch between core and DMA engine
                   Width byte stride (in DMA Setup register)=1
 Page 64                            ANDES Confidential
          Bus Interface Unit
                (BIU)




Page 65         ANDES Confidential
BIU introduction

Bus Interface unit is responsible for off-CPU
 memory access which includes
     System memory access
     Instruction/data local memory access
     Memory-mapped register access in devices.




 Page 66                 ANDES Confidential
Bus Interface

Compliance to AHB/AHB-Lite/APB
High Speed Memory Port
Andes Memory Interface
External LM Interface




 Page 67          ANDES Confidential
AHB & HSMP bus configuration

            Icache



                              Bus_path_ahb    AHB
           Dcache




           HPTWK




           LM-DMA
                               Bus_path_axi   HSMP



            EDM



 Page 68             ANDES Confidential
HSMP – High speed memory port

N12 also provides a high speed memory port
 interface which has higher bus protocol efficiency
 and can run at a higher frequency to connect to a
 memory controller.
The high speed memory port will be AMBA3.0
 (AXI) protocol compliant, but with reduced I/O
 requirements.




 Page 69             ANDES Confidential
ADP-XC5FF76 Evaluation Board介紹




 Page 70    ANDES Confidential
Overview

ADP-XC5FF676 Main Board
                         AICE Connector (J29)             Power On Button
                                                              (SW2)
                                                                                    Reset
                                                                                 Button(SW3)
     LCM Connector
        (J1,J2)                                                             EBI/X-BUS
                                                                            (J31,J32)

    Debug LED(LED7,8)
                                                                               NOR Flash
                                                                                (U3,U4)
       GPIO Push
     Buttons(SW4~8)
                                                                              SD/MMC
       CPU Oscillator                                                         (CON1)
           (X1)


                                                                            SDRAM (CON2)
       VIRTEX5 FPGA
           (U1)
                                                                            MII Connector
       AHB Connector                                                             (J24)
           (J36)



     FPGA Download                                                                   COM ports
       Port (J4,J11)                                                                 (J67,J68))


      DC-IN Jack (J10)                                                      RJ45 (J25)

       Power
     Switch(SW1)



                                                Audio Phone Jack
                                                   (J6, J8,J9)

 Page 71                 ANDES Confidential
Overview (cont.)
ADP-XC5FF676 Main Board

Hardware features:
•Xilinx XC5VLX110-1FF676 FPGA              •SD memory card slot
•Encrypted Bitstreams support               •IDE connector
•144 pins SO-DIMM for SDRAM                 •Xilinx XCF32P FPGA
•32MB on-board NOR flash                     configuration flash
•10/100 Ethernet                            •JTAG configuration port
•MII connector for external 10/100 PHY      •Five user push button
•RS232 serial port x2                        switches
•X-Bus expansion slot                       •LCD I/F
•AHB bus connector                          •I2S Audio Codec
                                            •7 segment LED display x2




 Page 72                   ANDES Confidential
Software Installation

AndeSight v1.3
Terminal Software
      TeraTerm
TFTP Server for Windows
      Tftp32




 Page 73            ANDES Confidential
Software Setting

TeraTerm




 Page 74           ANDES Confidential
Software Setting

Hyper Terminal




 Page 75           ANDES Confidential
Software Setting

Tftp32




 Page 76           ANDES Confidential
Networking Setting

 ADP-XC5FF676 and Laptop are connecting via Switch
 控制台 / 網路連線 / 區域連線 / 內容




 Page 77             ANDES Confidential
Booting Mode

 HCLK: 40MHz
 CPU: 80MHz
Please pressing GPIO keys:
_________________________________________________________
GPIO1 (SW4): Boot Linux from On-board flash (DPF)
GPIO2 (SW5): Run Diagnostics code
GPIO3 (SW6): Boot Linux from SD Card
GPIO4 (SW7): Burnin Test
_________________________________________________________
  ------------------------------------------------------
   ANDES diagnostic program, built@Apr 9 2008 (release: 1.8)
   CPU: N12 Platform: ADP-XC5FF676 Cache: id0 HCLK: 40MHz CPU: 80MHz
  --------------------------------------------------------------
( 1) SDRAM Test                ( 2) Timer Test            ( 3) DMA Test
( 5) UART Loopback Test ( 6) UART DMA Test                         ( 9) Watchdog Test
(10) Watchdog Reset Test(11) MAC Loopback Test (12) Flash Test
(13) SODIMM sizing               (14) SDRAM(bnk1,2)              (17) AC97 Test
(18) AC97 DMA Test                (20) I2C Test             (21) LCD Test
(23) Query RTC                (24) RTC alarm Test (25) GPIO Test
(35) CF, SD Test              (53) Enable Cache              (54) Disable Cache
(55) CLI                 (67) Set console's UART (75) Burnin test
(91) GO LINUX                 (96) NDS BOOT                   (97) CopyImageFromCard
(98) Exec_User_Programd

Command>>
 Page 78                                            ANDES Confidential
Booting non-OS Program

 Invoke the command line prompt and load the Kermit protocol
    Command>>55
    CLI>loadb 0x500000

 User may now transfer the file onto the target system through the hyper
  terminal, using the Kermit protocol
    kermit download 7760 bytes finished...

 Boot up the kernel image
    CLI>go 0x500000




 Page 79                                     ANDES Confidential
          ANDESCORE指令集架構




Page 80        ANDES Confidential
Data Types

Data Types
       Bit (1-bit, b)
       Byte (8-bit, B)
       Halfword (16-bit, H)
       Word (32-bit, W)
       Double Word (64-bit, D)




 Page 81                  ANDES Confidential
Andes Registers – GPR
 Andes ISA has 32 32-bit GPRs:

                               Reg. index in     Reg. index in
           ISA   # of GPR
                                32-bit ISA        16-bit ISA

     ANDES         32                    5           5/4/3

       MIPS        32                    5            3

       ARM         16                    4            3




 Page 82                    ANDES Confidential
General purpose registers
register    name    convention
r0-r5       a0-a5   function arguments
r6-r14      s0-s8   Callee saved
r15         ta      Assembler reserved
r16-r25     t0-t9   Caller saved
r26-r27     p0-p1   Operating system reserved
r28         s9/fp   frame pointer
r29         gp      global pointer
r30         lp      return address
r31         sp      stack pointer




  Page 83                 ANDES Confidential
Andes Registers – GPR Usage

  a0-a5:     function arguments and return
              values
  s0-s8: callee-saved registers
  t0-t9:     caller-saved registers
  ta:        temporary assembler register
  p0-p1: used by OS only.
  fp, gp, lp, sp: frame/global/link/stack pointers




 Page 84             ANDES Confidential
32-Bit Baseline Instruction

  1. Data-processing instructions
  2. Load and Store Instructions
  3. Jump and Branch Instructions
  4. Miscellaneous Instructions




 Page 85               ANDES Confidential
Data-Processing Instructions
 ALU Instructions with Immediate
          OP rt_5, ra_5, imm_15
            •   ADDI, SUBRI, ANDI, ORI, XORI
            •   SLTI, SLTSI: set rt_5 if ra_5 < imm_15 (unsigned or signed comparison)
          OP rt_5, imm_20
            •   MOVI, SETHI: set low or high 20 bits of rt_5 (the rest bits are set to 0).
 ALU Instructions without Immediate
          OP rt_5, ra_5, rb_5
            •   ADD, SUB, AND, NOR, OR, XOR, SLT, SLTS
            •   SVA, SVS: set if overflow on add/sub
          OP rt_5, ra_5
            •   SEB, SEH, ZEB, WSBH: sign- or zero-extension byte/half, word-swap bytes.
 Shift and rotate instructions:
          OP rt_5, ra_5, imm_5
            •   SLLI, SRLI, SRAI, ROTRI
          OP rt_5, ra_5, rb_5
            •   SLL, SRL, SRA, ROTR




 Page 86                                      ANDES Confidential
Data-Processing Instructions (cont.)
 Multiplication-related Instructions
     OP       rt_5, ra_5, rb_5      32-bit results of ra_5 x rb_5 to rt_5
           • MUL
     OP       d_1, ra_5, rb_5       32-bit or 64-bit results to “d” registers
           • MULTS64, MULT64, MADDS64, MADD64, MSUBS64, MSUB64, MULT32,
             MADD32, MSUB32
     OP       rt_5, d_1.{hi, lo}
           • MFUSR, MTUSR: move-from or move-to a USR register
 Example:
      mult64 d0, r0, r1
      mfusr r2, d0.hi
      mfusr r3, d0.lo




 Page 87                             ANDES Confidential
Load/Store Instructions
 Load/Store Single:
      Immediate value is in the unit of access size.
           •   OP rt_5, [ra_5+imm_15]
                –   LWI, LHI, LHSI, LBI, LBSI, SWI, SHI, SBI
           •   OP rt_5, [ra_5], imm_15: with post update
                –   LWI.bi, LHI.bi, LHSI.bi, LBI.bi, LBSI.bi, SWI.bi, SHI.bi, SBI.bi
      Index register is left-shifted by 0,1,2,3 bits by si
           •   OP rt_5, [ra_5+rb_5<< si]
                –   LW, LH, LHS, LB, LBS, SW, SH, SB
           •   OP rt_5, [ra_5], rb_5<<si
                –   LW.bi, LH.bi, LHS.bi, LB.bi, LBS.bi, SW.bi, SH.bi, SB.bi
      Final addresses must be aligned to the access size.




 Page 88                            ANDES Confidential
Jump and Branch Instructions
 Jump Instruction
     OP            imm_24
           • J: unconditional direct branch
           • JAL: direct function call
     OP            rb_5
           • JR: unconditional indirect branch
           • RET: return
           • JRAL: indirect function call
 Branch Instruction
     OP rt_5, ra_5, imm_14
           • BEQ, BNE
     OP rt_5, imm_16
           • BEQZ, BNEZ, BGEZ, BLTZ, BGTZ, BLEZ




 Page 89                           ANDES Confidential
Miscellaneous Instructions

Conditional Move
     CMOVZ rt_5, ra_5, rb_5
           • rt_5 = ra_5 if (rb_5 == 0)
     CMOVN rt_5, ra_5, rb_5
           • rt_5 = ra_5 if (rb_5 != 0)
Example: C code to assembly
     if (r0==0) r3 = r1; else r3 = r2;
           • move           r3, r2
             cmovz          r3, r1, r0




 Page 90                          ANDES Confidential
Miscellaneous Instructions (cont.)
 NOP Instruction
     No Operation
     Never needed for correctness.
     Useful for code alignment in some implementations for better
      performance.
 Breakpoint and System call Instructions
 Trap, Return Exception Instructions
 System Register Access Instructions




 Page 91                     ANDES Confidential
Strength of Andes ISA

 Mixed-length ISA with flexible 16b instructions.
 Efficient constant-setting instructions (up to 20 bits)
 PC-relative jumps for position independent code.
 Bi-endian modes to support flexible data input.
 Performance instruction extensions for greater
  performance.
 Immediate values of load/store word/halfword are in
  the corresponding access size to address wider
  range.
 Load/store with post-update mode..
 Plenty space for custom extensions.


 Page 92               ANDES Confidential
ANDESIGHT整合開發環境操作介紹




 Page 93   ANDES Confidential
AndeSight IDE

Window
View
Perspective
Editor
Preferences…
Help
Advanced features




 Page 94             ANDES Confidential
Andes Total SW Solution
                                            user



                          Integrated Development Environment (IDE)


                                       AndeSight™

                                                                        ICE
                          Simulation          Toolchains:
                            Engine             Compiler
                                              Assembler    Evaluation
                              AndESLive™         AndeShape™ Board
                                                Linker
                                               Debugger
            SoC
           Builder



      Andes SW Solution   =    AndESLive™    +    AndeSight™   +     AndeShape™



 Page 95                               ANDES Confidential
Integrated Development Environment



Toolbar




   Page 96        ANDES Confidential
Windows

What is window
     The overall outer frame
New window
     Menu bar  Window  New Window
           • Same workspace and perspective
     Start another AndeSight
           • Different workspace




 Page 97                       ANDES Confidential
Windows




 Page 98   ANDES Confidential
Views

What is view
     View provides alternative presentations as well as
      ways to navigate the information in your Workbench.




 Page 99                ANDES Confidential
Views




Page 100   ANDES Confidential
Perspectives

What is perspective
     The initial set and layout of views in the Workbench
      window.
     Each perspective provides a set of functionality aimed
      at accomplishing a specific type of task or works.
We provide
       C/C++ coder
       Debug
       VEP Config (AndESLive)
       Profiling



Page 101                 ANDES Confidential
Perspectives




Page 102       ANDES Confidential
Perspectives – Debug and Profiler




Page 103           ANDES Confidential
Perspectives – VEP (Virtual Evalution
Platform) Config




Page 104            ANDES Confidential
Perspectives – Others…




Page 105          ANDES Confidential
Editor

Editors we provide
       C/C++
       Makefile
       Assembly
       Binary Hex
       VEP




Page 106              ANDES Confidential
Features of C/C++ Editor


Content assistant
Function Definition
Auto completion
Syntax highlight
Formatter




Page 107               ANDES Confidential
Content assistant




Page 108            ANDES Confidential
Show Function Definition




Page 109           ANDES Confidential
Text Auto Completion




Page 110          ANDES Confidential
Template Support




Page 111           ANDES Confidential
Formatter




Page 112    ANDES Confidential
Preferences

What settings are provided?
     Is used to set user preferences
     Can be searched using the filter function




Page 113                 ANDES Confidential
Preferences




Page 114      ANDES Confidential
Preference to Change Fonts




Page 115          ANDES Confidential
Commands and Functions




Page 116        ANDES Confidential
Help System

Context sensitive help
     Hot key: F1
Help Content
Search …




Page 117            ANDES Confidential
Profiling

AndeSight IDE


    Trigger Profiling




                        Prof.out                              Profiling
                                                              Analysis
                                                              Engine
            Profiling data preparation


AndESLive Simulator
 Page 118                                ANDES Confidential
Profiling Options
 Function Level
        Pure function profiling without branch and cache information
        With Branch Summary
        With Cache Summary
        With Branch and Cache Summary
 Branch Level
      Pure branch profiling without cache information
      With Cache Summary
 Views
        Flat View
        Call View
        Timeline View
        Chart View
 C and C++ Support
 Fast Mode and Extended Mode
 Goto Source



 Page 119                         ANDES Confidential
Profiling Options




Page 120            ANDES Confidential
Performance Tuning

                             Tune Performance by CPU Configuration

            Co-Sim




            Profiling




           Meet Spec.
                        No

                 Yes

             END
                                                Tune Performance by Software Works


Page 121                            ANDES Confidential
Tune Performance by Profiler

Profile Result of 8KB I$/D$




Profile Result of 64KB I$/D$




 Page 122                      ANDES Confidential
Profiling – Timeline View




Page 123            ANDES Confidential
Profiling – Call View




 Page 124               ANDES Confidential
Profiling – Flat View




 Page 125               ANDES Confidential
Branch Level with Cache Summary




Page 126         ANDES Confidential
Build Options




Page 127        ANDES Confidential
 Endian – SW

SW endian setting gives –EL or –EB option to compiler




  Page 128                        ANDES Confidential
 Endian – HW

HW endian setting gives option to simulator




   Page 129                       ANDES Confidential
 Library – SW

SW library setting gives –mlib option to linker




   Page 130                         ANDES Confidential
 Library – HW

HW library setting should enable Virtual IO support and select
proper library for simulator




                                                        Window > Show View > Other
                                                        VEP > System Call Emulation




   Page 131                        ANDES Confidential
 Toolchain – SW

Toolchain includes one for hardcore, one for softcore




   Page 132                        ANDES Confidential
 CPU Selection

Virtual SoC Builder provides one hardcore and one softcore




  Page 133                        ANDES Confidential
           嵌入式軟體程式設計原理




Page 134       ANDES Confidential
Embedded Software Development Flow
Embedded system usually comes with a booloader
 software, for example AndesBoot
     initialize the hardware
     set up the memory map
In the rest, the embedded s/w itself decides how to
 partition the memory map




Page 135                   ANDES Confidential
Embedded Software Development Flow (cont.)
  An embedded s/w consists of the following sections
  A description file is need to describe which section is
   allocated to which kind memory


                                           stack      sram



                                            bss           sddram
                           text
                                            text

                           data             data      FLASH


                                         Program in
                   Program in file
                                          memory




  Page 136                           ANDES Confidential
Embedded Software Development Flow (cont.)


                                                     stack
             int = 0;

             int j;
                                                      bss
             void main ()
             {                                        text
               int k;
               k = k + 1;
                                                      data
               printf (“hello world\n”);
             }




  Page 137                      ANDES Confidential
ENTRY(_start)
   la    $sp,_stack
   la    $r0,_bss_start_
   la    $r1,_bss_end_
   move $r3,0
   move $r4,0              Setup stack, clear bss
   move $r5,0
   move $r6,0
1:
   smw.bim $r3,[$r0],$r6
   sub      $p0,$r0,$r1
   bltz      $p0,1b
   …
   move      $r0,0
   move      $r1,0
   move      $fp,0
   bal main
1:
   b         1b

 Page 138                        ANDES Confidential
           Thank you



Page 139     ANDES Confidential

				
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