resume - Xilinx FPGA Embedded Linux by leader6

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									              Page 1 Brendan Graham


                                                       Brendan Graham
                            Embedded Systems Engineering Project Management and Architecture.
            (305) 793-3778 URL: http://usysinc.com e-mail: info@usysinc.com Resume: http://usysinc.com/resumee.97.doc

 S ∫ntegral
μ ys              Sep’95- Present uSys Integral, Miami, FL
                                           Current Products and IP under development
    •   Development of a 97% high efficiency 300W @ 12-48 VDC link to 240 VAC Microinverter and a 10kVA, 100kVA, 1000kVA
        @ 400-900 VDC link to 220-265 VAC modular 3-phase Photo Voltaic (PV) cell Grid Tie Inverters for residential and
        commercial applications. Expertise in buck, boost, inverter, full H-bridge, half bridge, push-pull, forward, flyback, voltage fed,
        current fed, continuous, discontinuous and critical conduction mode control, interleaved, synchronous rectification, integrated
        ferro-magnetics design, Spice mixed signal synthesis, design and modeling. DSP’s used: TMS320F2812, ADSP-BF506F,
        dsPIC33FL16. Custom MOSFET, IGBT, analog bimos gate driver and digital control electronics design.
    • Architecture and implementation in HDL of an Elliptic Curve Cryptography encryption/decryption algorithm for implementation
        in a Xilinx Virtex-4 FPGA, with POE for application in defense and commercial monetary transactions environments.
    • Analyst, system architecture, software development of core architectural issues and system integration of GIS based zero-client,
        web browser based, GPS/GPRS tracking solution using a combination of open source and proprietary API’s. Languages used are
        C/C++, Java, JavaScript and PHP. Java Servlet and WAR container is Apache Tomcat. COTS and custom GPS/GPRS modem
        hardware integration.
    • Development of Linux based, 6U VME based, 400fps 4-ch Gb-Ethernet frame grabber. Ported Linux 2.6.23 kernel to embedded
        PPC-405 on Xilinx XC4VFX12, with source synchronous parallel interface to XC5VLX85T FPGA implementing 4 TEMAC,
        Camera Link (CL) and SFPDP interfaces coupled to chained DMA controller, streaming data to 6 CF PATA-6-133MHz media
        interfaces and TMS320DM6446 for H.264 DV compression. Developed kernel device drivers for DMA driven peripheral
        interfaces. Tools used: coLinux, ELDK, Crosstool, gcc.
                                                  S ∫ntegral Client Project Portfolio
                                                 μ ys


              Dec’2008-June’2009 C&S Companies. System architecture and analysis of Fiddlehead Green technology OS
virtualization application of multi head server running Linux host OS and Sun VirtualBox hyper-visor serving multiple Windows OS
clients. Linux kernel, USB EHCI, device driver analysis and coding in C.

ƴ Susceptance Systems      Sept’2008-Dec’2008 Susceptance Systems LLC, Miami, FL. Xilinx FPGA, analog, digital design for piezo-
gyro and silicon accelerometer platform stabilization of a twin axis visual object targeting and tracking control system.


                            March’2008-September’2008 Cirrus Logic, Austin TX. Linux 2.6.25rc9 on Xilinx XC4VFX20 PowerPC
for an embedded 1Gig Ethernet router for the CobraNet audio/video distribution system. Responsible for product architecture, Linux
kernel porting to the FX20, Xilinx XPS project creation with MPMC, NPI, SDMA , DDR2 SDRAM, 2xTEMAC’s, MGT’s, LocalLink
FIFO interfaces with Linux 2.6 LKM interrupt driven platform model device driver support in C/C++ for custom Ethernet router IPIF.


               Feb’2008-March’2008 Intel Corporation. Altera EP1S20 FPGA architecture and development with QuartusII, for
real-time USB EHCI software driver and test vector generator interface to Mentor Graphics Veloce SoC RTL emulator.

ƴ Susceptance Systems      Jan’2007-March’2007 Susceptance Systems LLC, Miami, FL. FPGA design for a Green technology
medical imaging application, of triple Xilinx XC4VFX60-ff1152 based design, incorporationg RocketIO MGT, dual embedded
PowerPC configuration, Tri-Mode Ethernet MAC (TEMAC), QDR II SRAM interface, SPI, LVDS Serial A/D interface, extensive use
of DCMs. User Constraint File (UCF) construction, FPGA bank selection for I/O, synthesis, timing closure, embedded software design.
Tools used were Xilinx ISE9.1i, XPS9.1i, ISE 9.1i CORE Generator, ModelSim 6.2g.

                    June’2006-Dec’2006        Corning Corporation, Corning, NY. Responsible for hardware, software specification,
architecture, design and implementation of digital/analogue/microwave and Digital Signal Processing solutions to composite frequency
doubling, three electrode, 0.5Ω, Fabrey-Perot InGaAlAsP 1060nm DFB DBR Laser, to 530nm MgO-doped PPLN SHG waveguide
crystal, “LAMP” Green Laser HDK. Tools used include C/C++, Java, Verilog HDL, ModelSim, Altera Quartus II, Stratix II, Neos
embedded megafunction uC core with digital signal processing on TI C6416, C6455 DSP’s.

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                  Jan’2005-April’2006 Theseus Logic, Orlando, FL. EDA software development in ANSI C, C++, Java J2EE,
applets, servlets and the JNI for logic synthesis, optimization and simulation of NULL convention asynchronous logic. The project
entailed architecture and design of a custom GUI and Lexical Analyzer and Compiler developed in Java. Architecture involved inter-
process-communication using the RMI API. A Tcl interpretation shell was also integration into the Java based GUI tools. Expertise in
VHDL, Verilog design at the RTL level along with system verification in C/C++/Java are leveraged. Embedded software
development in 8051 assembler/C/C++ targeting the TI Chipcon CC2430, 802.15.4 based ZigBee, 2.4GHz low power Green
technology, wireless telemetry sensor and data acquisition multi-node, multi gateway network system. Responsible for the architecture
specification, development and implementation of a secure custom, self healing, autonomous wireless networking protocol.


                 June’2004-Aug’2004           B.F. Goodrich Aerospace, Vergennes, Vermont. FPGA and MSI based board level
digital-analogue design and specifications documentation for Apache helicopter avionics control system.


                     Feb’2004-April’2004 SimpleTech, Santa Ana, CA. FPGA Verilog based architecture and design, synthesis
and verification of Xilinx Virtex II, xc2v3000 and xc2v6000 devices under Xilinx ISE. Architectural integration of ATA-66MHz and
ATA-133MHz to IDE interfaced NAND CompactFlash IP RTL for a rugged environment flash HDD.


                     Nov’2001-Jan’2004        MoonStorm, Miami, FL. Mixed-Signal, Verilog-Spice and FPGA designe, GUI design
and systems verification with ModelSim Verilog and XSpiceHDL, targeting Xylinx Spartan-II devices. Responsible for the system,
board, module and chip level specification, architecture, characterization, design, RTL implementation and verification, including
Verilog and Verilog PLI/VPI bindings, mixed-signal XSpice/Verilog/C/C++/SystemC co-simulation and scripting for test bench
generation. Embedded Linux web server development on Motorola MCF5272 microprocessor interfacing to Spartan-II devices.
Analog A/D and D/A circuit design and implementation, SMPS design for 100KHz bandwidth switched 4-kW power
electromagnetic bearing characterization, design and implementation. Digital adaptive LMS and neural back propogation
algorithm implementation on ADSP 2181 for variable reluctance current sensing and vibration control of electromagnetic bearing
and positioning platform. Schematic capture and PCB design with ORCAD. Additionally this project called for the design and
development of an in-house XSpice/Verilog HDL EDA co-simulation environment. Participated as principal architect and developer
using C++, wxWidgets API, Verilog PLI/VPI API and XSpice Code Model API’s. A detailed ABSTRACT of this companies EDA
product offering XSpiceHDL based on this technology can be found at http://usysinc.com/xspicehdl.abstract.htm. A development
snapshots of the product XSpiceHDL demonstrating my extensive abilities in EDA tool development can be found at
http://usysinc.com/get.xspicehdlcap.htm.


                    Mar’2001-Oct’2001       Sky Computers, Chelmsford, MA. FPGA design, systems verification with Verilog XL
and MTI, targeting Xylinx Virtex-II and Virtex-E devices. Responsible for the system, module and chip level verification, architecture
and RTL implementation, including Verilog PLI binding, modeling in C/C++ and Verilog scripts for test bench generation. Detailed
Verilog RTL split transaction PowerPC MPX 7410 multiprocessor system chipset interface design and protocol as well as I2C, SPI
and CAN bus master/slave controllers. Design of packet switched inter-processor messaging.

                         Dec’2000-Mar’2001       Smiths Industries, Aerospace, Germantown, MD. FPGA design and systems
verification with VHDL/Verilog/C++ targeting Xylinx XC4000XLA devices. EDA tools used were ModelSim, Exemplar Leonardo,
Renoir, Xilinx Foundation for GPS navigation, targeting, and fire control computer system upgrade for the Saudi Air Force F18A
jet fighter.

                            Oct’2000-Dec’2000 Hamilton Standard, flight control systems, Windsor Locks, CT. FPGA design and
systems verification in VHDL/C++ targeting the ACTEL A42MX FPGA’s. Simulator environment used was ModelSim, synthesis
with Exemplar Leonardo, Mentor Graphics Renoir, place and route with ACT Map Designer tools. This project was fundamentally a
continuation of prior work done in Sept’99-Mar’2000 for the same company.


                  May’2000-Oct’2000   Veridian Systems, Telemetry systems design group, California, MD.
FPGA logic, systems and PCB, board level architecture, design and routing for an Ethernet LAN Telemetry system aboard military
aircraft. FPGA design coded in VHDL using the Mentor Graphics ModelSim simulator, synthesis with Synopsys FPGA Express
targeting the Altera FLEX 10K-20 FPGA. High speed state machine design for a TCP/IP protocol parser and router application was
implemented. Schematic capture and PCB design with ORCAD.

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                 Sept’99-Mar’2000             Texas Instruments, ASIC wireless design group, Schaumburg, IL.
ASIC design and verification at the tester vector generation (TDL) level, for 0.18µm cellular wireless ASIC chipset, factory wafer
testing. Functional verification activities included TDL vector generation, test bench creation, Perl/C++ scripting and TDL vector
parsers. Responsible for the RTL design and test bench in Verilog, of a cache controller located between an ARM micro controller core
and a shared single ported SRAM block.

                             Nov’98-July’99        Hamilton Standard, flight control systems, Windsor Locks, CT. FPGA design and
systems verification in VHDL/C++ targeting the ACTEL A42MX and A54SX FPGA’s. Simulator environment used was ViewLogic
WorkView Office tools suite coupled with the ACT Map and Designer synthesis and place and route tools. Responsible for
architectural design and implementation of a dual-redundant fault tolerant PowerPC603 based custom system chipset comprising main
SRAM memory with block-forward-error-correction in both the read-write data paths, DMA controller subsystems, and various
integrated peripheral communications controllers including high speed 400Kbps UARTS and ARINC 429 controllers. The system was
specifically a single-event-upset, radiation-hardened computer engine controller for the Pratt & Witney, PW4000 and PW6000 jet
turbine engines.


                       Sept’97-June’98 Digital Equipment Corporation, Storage Business Unit, Shrewsbury, MA. ASIC verification
in Verilog on DEC Alpha 5/500 workstation running Digital-UNIX. Responsibilities included conception through design of SCSI
behavioral verification suite using ViewLogicXVcs. The ASIC was a 100k gate, Ultra2 SCSI Bus Expander; Symbios SYM53C140
fabricated in Symbios 0.25µm process. The verification suite consisted of a fully compliant X3T9.2/375R rev.10k bus model
implemented as multiple instantiations of an initiator/target behavioral device, cascaded throughout a multi-Bus Expander configuration.
The top level test bench consisted of eight instantiations of the initiator/target transactors together with four instantiations of the Bus
Expander, the (DUT). A bi-directional communications, command and status bus was implemented between each instantiation of the
initiator/target transactors and simulation control code existing within the top level test bench. Approximately sixty commands could be
exercised in order to control asynchronous interaction amongst any number of initiator/target transactor devices. A full range of SCSI
phases ranging from bus free, arbitration, selection, reselection, asynchronous and synchronous data transfer through message,
command and status could be exercised seamlessly. Special attention and emphasis to the implementation of the reselection, SDTR and
WDTR transactions assure proper rate and width negotiation for a catalogued SCSI nexus without user concern for database
housekeeping. A full range of error and status message reporting was implemented was systematically available in the `vcs.log' file as
well as several other error particular files for use in debugging. Over 860kbytes of Verilog/C++ text code comprise the entire
behavioral suite. The suite of tools also enabled chip level verification of internal register contents in the course of relevant transactions.



                           Aug’96-Aug’97         AT&T Bell Labs, Lucent Technologies, Holmdel, NJ. ASIC and FPGA design on
the Sun SPARC workstation using Verilog-XL, SignalScan, VHDL and the MTI V-system's VHDL/Verilog cross simulator.
Synchronous finite state machine design for a portable wireless RF and Infrared , ATM switched LAN coupled to the PCMCIA type
II bus. Performance of board and system level simulation of ORCA targeted FPGA’s together with MSI logic designs into a unified
Verilog/C++ simulation and synthesizable model designed for full driver stimulus. Development expertise of PCI, PCMCIA and
CardBus interfaces. High-speed mixed Mealy-Moore, synchronous finite state machine design for a giga-bit Ethernet switch ASIC
targeting the Lucent Technologies Microelectronics group's HL350CDE, 0.35µm CMOS standard cell library. Performed timing and
algorithm analysis of an SDRAM controller using a SAND SDRAM behavioral model in Verilog, Synthesizable logic for the SDRAM
controller designed and coded in VHDL while synthesis was performed by Synopsys Design Compiler.


                 Sep’95-July’96         Intel Corporation. OEM Products Division, Server Business Unit,
Hillsboro, OR. Pentium Pro® ’P6’ Server Systems Management comprising an embedded microcontroller firmware architecture.
Responsible for design and implementation of, embedded server systems management functionality, which comprise distributed micro-
controllers with I2C bus communications and monitoring subsystems coupled to an EPLD implemented ISA communications bridge.
EPLD design experience with ALTERA and LATTICE devices in Altera-HDL and ABEL-HDL, extensive 8051 assembler language
firmware design for distributed microcontroller I2C multi-master communications system, and platform drivers done in C++.

WATSCO COMPONENTS, Inc. April’95-Aug’95               Embedded microcontroller Specialist/Consultant. Analog/Digital, C++ &
8051 Micro controller circuit design for HVAC control and protection. Electro-mechanical test fixture design. Signal conditioning.
Cost sensitive embedded systems. Extensive use of TANGO and ORCAD.

TIF INSTRUMENTS. Oct’94-April’95                R&D Electronic Design Engineer/CAD Engineer/Consultant. Hardware, firmware,
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schematic capture and PCB design with ORCAD/TANGO. Mechanical drafting with AutoCad.

VIGILANT TECHNOLOGIES. May’94-Oct’94                      PCB/CAD Engineer/Consultant. PCB design for PC based I/O peripheral
products. Schematic capture, PCB layout and routing.

ARCO ELECTRONICS. May’94-Oct’94 R&D Design Engineer/Consultant. Hardware and Software design of intelligent 8032
based HD/FL disk controllers. Schematic capture and PCB layout and routing.

RALTRON ELECTRONICS. May’94-Oct’94 CAD Engineer/Consultant. Schematic Capture and PCB layout and routing for this
companies line of high stability crystal oscillators.

21 Tech Corp. Jun’93-April’94 R&D Design Engineer/Consultant. Client accounts include IBM, INTERRAX, CENTEC, US
NAVY. Digital Video / multimedia systems integration on ISA & MCA platforms. Major Product Success: "The Vision Board/School
Live Board", a fully compliant IBM MMOTION compatible board for ISA platforms, marketed by and sold exclusively through
CENTEC CORP., Jackson, MS .

BARTEC. Nov’92-May’93 Analog/Digital CAD Engineer/Consultant. Hybrid telecommunications surveillance systems
development and Implementation, serving both Federal and State Agencies requirements. Extensive use of the 8051 processor and
ASIC's for telecommunications. Responsibility for all CAD and mechanical considerations for new product development and revisions
to existing designs. Extensive experience in high density SMD PCB design.

Logical Devices Inc. Jan’92-July’92 Analog/Digital Embedded Systems Design Consultant. Micro/PLD Algorithmic Device
Programmers. Hardware/Firmware development of 8032 micro controller based systems. Serially communicable peripheral devices.

                                                         Other Employment
Tangent Associates, Davie, Fl. Oct’90 - Jan’92 Microcomputer Electronics Engineer. Point of Sale Systems. Development,
debugging, diagnostics, quality control, production assembly and hardware diagnostics responsibilities. Management of on site
installations and crew. On site training at client locations throughout the United States.

Deltana Technologies, Miami, Fl. Aug’87 - Oct’90 Argon-Laser and SMPS Technician. Service calibration and upkeep of laser tubes,
high vacuum re-gassing equipment and peripheral laser support electronics to component level.

                                                             KEYWORDS

Verilog, HDL, PLI, VPI, VHDL, C, C++, Java, Applets, Servlets, ANT, J2SE, J2EE, SystemC, Spice, XSpice, Tcl, PHP, AJAX, JavaScript, DHTML,
XML, XSL, GML, MySQL, wxWidgets, Apache, Tomcat, Compiler, Elaboration, multithreaded Berkley Sockets, Client-Server IPC, Simulator,
GUI, API, ASIC, FPGA, Xilinx, Altera, Actel, Lattice, Virtex, Spartan, Pentium, PowerPC, PPC, MMU, MPX74xx, ARM, RISC, TCP/IP, RMI, IDL,
COBRA, mixed-signal, design, simulation, verification, digital, analog, FLASH, MEMS, Piezo, 8051, PCB, Orcad, ModelSim, NCVerilog, VCS,
Mentor Graphics, MTI, Cadence, Synopsis, SMPS, LMS, adaptive, equalization, fuzzy logic, neural networks, ADSP, TMS, EDA, ISE, Exemplar,
Leonardo, Foundation, UART, ARINC429, I2C, SDRAM, PCI, PCMCIA, CardBus, ATA, IEEE 802.15.4, BlueTooth, ZigBee, NCL, Asynchronous
Logic, Microwave, RF Amplifier, Analog, GPS, GPRS, AVL, WMS, WFS, WFS-T WFS-G, SRS, GeoServer, MapServer, MapGuide, GeoTools,
OpenLayers, MapBuilder, MapBender, Chameleon, Jetty, Maven, GIS, Elliptic Curve Cryptography, Management, Team Leader.




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