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                               ELECTRONIC CIRCUITS LAB

           List of experiments (Twelve experiments to be done):
Code No: 07A30491
I) Design and Simulation in Simulation Laboratory using multiSim OR Pspice
  OR Equivalent Simulation Software (Any Six):
           1.      Common Emitter and Common Source amplifier
           2.      Two Stage RC Coupled Amplifier
           3.      Current shunt and Feedback Amplifier
           4.      Cascade Amplifier
           5.      Wien Bridge oscillator using Transistors
           6.      RC Phase Shift Oscillator using Transistors
           7.      Class A Power Amplifier ( Transformer less)
           8.      Class B Complementary Symmetry Amplifier
           9.      High Frequency Common base (BJT)/ Common gate ( JFET )
                   Amplifier


II)        Testing in the Hardware Laboratory (Six Experiments : 3+3 ):
      A)        Any Three circuits simulated in Simulation laboratory
      B)        Any Three of the following
                1) Class A Power Amplifier (with transformer load )
                2) Class B Power Amplifier
                3) Single Tuned Voltage Amplifier
                4) Series Voltage Regulator
                5) Shunt Voltage Regulator




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                          ELECTRONIC CIRCUITS LAB
                                    (SOFTWARE)


         Design and Simulation in Simulation Laboratory using Multisim


        Introduction to multiSim
  1. Common Emitter and Common Source amplifier
  2. Two Stage RC Coupled Amplifier
  3. RC Phase Shift Oscillator using Transistors
  4. Class A Power Amplifier
  5. Class B Complementary Symmetry Amplifier
  6. Current shunt Feedback amplifier




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     1. COMMON EMITTER AND COMMON SOURCE AMPLIFIER
                       COMMON EMITTER AMPLIFIER


AIM : To design and simulate the frequency response of common emitter amplifier
 for a gain of 50.


CIRCUIT DIAGRAM :




THEORY:


            The CE amplifier provides high gain and wide frequency response. The
emitter lead is common to both the input and output circuits are grounded. The
emitter base junction is at forward biased .The collector current is controlled by the
base current rather than the emitter current. The input signal is applied to the base
terminal of the transistor and amplified output taken across collector terminal. A very
small change in base current produces a much larger change in collector current.
When the positive is fed to input circuit it opposes forward bias of the circuit which
cause the collector current to decrease, it decreases the more negative. Thus when
input cycle varies through a negative half cycle, increases the forward bias of the

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circuit, which causes the collector current increases .Thus the output signal in CE is
out of phase with the input signal.


PROCEDURE


   1. Select different components and place them in the grid.
   2. For calculating the voltage gain the input voltage of 25mv (p-p) amplitude and
       1KHz frequency is applied, then the circuit is simulated and output voltage is
       noted.
   3. The voltage gain is calculated by using the expression
                 Av = Vo/Vi
   4. For plotting frequency response, the input voltage is kept constant at 25mv(p-
       p) and frequency is varied.
   5. Note down the output voltage for each frequency.
   6. All readings are tabulated and Av in db is calculated using the formula
       20 Log Vo/Vi.
   7. A graph is drawn by taking frequency on X-axis and gain in dB on Y-axis on
       a Semi log graph sheet.


THEORITICAL CALCULATIONS :




To calculate Av, Zin(base) and Z in :




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                                      5




PRACTICAL CALCULATIONS :




OBSERVATIONS :


   Frequency(Hz)   Voltage Gain




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INPUT WAVE FORM :




  OUT PUT WAVE FORM :




 FREQUENCY RESPONSE :




BAND WITH:


RESULT : The frequency response of common emitter amplifier is simulated and
           bandwidth is noted.
VIVA QUESTIONS :

   1. What is the phase difference between input and output waveforms of CE
      amplifier?
   2. What type of biasing is used in the given circuit?
   3. If the given transistor is replaced by P-N-P ,Can we get the output or not?
   4. What is the effect of emitter bypass capacitor on frequency response?
   5. What is the effect of coupling capacitor?
   6. What is the region of transistor so that it operates as an amplifier?
   7. Draw the h-parameter model of CE amplifier.
   8. How does transistor acts as an amplifier.




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                          COMMON SOURCE AMPLIFIER
AIM : To design and simulate the frequency response of common source amplifier
       for a gain of 5.


CIRCUIT DIAGRAM:




THEORY:
                A weak signal is applied between gate and source and output is
obtained at drain. For the proper operation of FET, gate must be reverse biased. A
small change in reverse bias on the gate produces a large drain current. This fact
makes FET capable of raising the strength of a weak signal. The gain of the common
source FET amplifier is very high which is greater than unity.




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PROCEDURE:
  1. Select different components and place them in the grid.
  2. For calculating the voltage gain the input voltage of 0.2V(p-p) amplitude and
     1KHz frequency is applied, then the circuit is simulated and output voltage is
     noted.
  3. The voltage gain is calculated by using the expression Av = Vo / Vi
  4. For plotting frequency response the input voltage is kept constant at 0.2V(p-
     p) and frequency is varied.
  5. Note down the output voltage for each frequency.
  6. All readings are tabulated and Av in dB is calculated using 20 Log Vo / Vi.
  7. A graph is drawn by taking frequency on X-axis and gain in dB on Y-axis on
     a Semi-log graph sheet.
THEORITICAL CALCULATIONS :




PRACTICAL CALCULATIONS :




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OBSERVATIONS :
Frequency(Hz) Voltage Gain




INPUT WAVE FORM :




OUT PUT WAVE FORM :




FREQUENCY RESPONSE :




BAND WITH:     f2 - f1 =   Hz


RESULT : The frequency response of common source amplifier is simulated and the
           bandwidth is noted..

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VIVA QUESTIONS:

  1.   How does FET acts as an amplifier?
  2.   What are the parameters of a FET?
  3.   What is an amplification factor?
  4.   Draw the h-parameter model of the FET.
  5.   What are the advantages of FET over BJT?
  6.   What is the region of FET so that it acts as an amplifier?
  7.   What are the differences between JFET and MOSFET?
  8.   What type of biasing is used in the given circuit?




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                   2. TWO STAGE RC COUPLED AMPLIFIER


AIM: To simulate and observe the frequency response of RC coupled amplifier.


CIRCUIT DIAGRAM :




THEORY:


        RC is the most widely used coupling as it provides excellent audio fidelity. A
coupling capacitor is used to connect output of first stage to the input of the second
stage. Resistances R1, R2, R5, R3, R4 and R10 form biasing and stabilisation network.
Emitter bypass capacitors C5 and C6 offer low reactance paths to the signals. The
coupling capacitor C3 transmits ac signal and blocks dc signal. Cascaded stages
amplifies signal and overall gain is improved. The total gain is less than the product
of   gains    of   individual   stages.   Thus   overall   gain   of   two   stages   is
A = A1 x A2, where A1 = Voltage gain of first stage and A2 = Voltage gain of second
stage


        When ac signal is applied to the base of the transistor Q1, its amplified output
appears across the collector resistor R9. It is given to the second stage for further
amplification and signal appears with more strength. Frequency response curve is


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obtained    by plotting a graph      between frequency and gain in dB. The gain is
constant in midband frequency range and gain decreases in low and high frequency
ranges. The gain decreases in the low frequency range due to coupling capacitor C 3
and at high frequencies due to junction capacitance Cbe .


PROCEDURE:


   1. Select different components and place them in the grid.
   2. Apply input by using function generator to the circuit and simulate the circuit.
   3. Observe the output waveform on CRO.
   4. Measure the voltage at
           (i)      Output of the first stage
           (ii)     Output of the second stage
   5. From the readings, calculate voltage gain of first stage, second stage and
      overall gain. Disconnect         second stage and then measure output voltage of
      first stage and calculate voltage gain.
   6. Compare it with the voltage gain obtained when second stage was connected.
   7. For plotting the frequency response, the input voltage is kept constant at 2mv
      (p-p) and the        frequency is varied from 100Hz to 1MHz.
   8. Note down the value of output voltage for each frequency.
   9. All the readings are tabulated and voltage gain in dB is calculated by using
      the expression



                     A graph is drawn by taking frequency on X-axis and gain in dB on
Y-axis on a Semilog graph sheet.
   10. The bandwidth of the amplifier is calculated from the graph using the
      expression
                     Bandwidth = f2 – f1.
      Where f1 = Lower cutoff frequency of CE amplifier.
                  f2 = Upper cutoff frequency of CE amplifier




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THEORITICAL CALCULATIONS :
DC Analysis :
Calculation of RC& RE :


Given                                        for the operating point to be approximately
for the centre point with this data.




        =      +     = 0.025mA + 1mA = 1.025mA



Choose             =2v then         =    =             = 1.95 kΩ



        Then Vc = VCC – (VE + VCE ) = 9 – ( 2 + 5 ) = 2V



              RC =       =          = 2kΩ



It is recommended that RE must be less than RC selected
                   RE = 1kΩ and RC = 2kΩ
Calculation of R3 & R4 :
The Thevenins equivalent voltage base



    VB =                VCC and is equal to sum of VBE & VE.



             VBE + VE = 0.7 + 2 = 2.7v



                    =         =         = 0.3

                              R3 = 2.33 R4
     Choose the current flowing through R4 is


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                         =       =       = 100 μA




                  R4 =       =           = 27kΩ




                  R4 = 2.33kΩ, R3 = 27kΩ


Select R3 = 2.2k Ω, R4 = 27k Ω


AC Analysis:
The voltage gain of an amplifier can be taken as



 Av =     = 10




 Where Re =         =        = 25Ω




Av =       = 10 => RL’ = 250Ω



   RL’ = RCII RL = 2.2kΩ II RL => RL = 282Ω


There is resistance offered between collector and emitter choose RL = 300 Ω
for ac analysis select
        Ce = 100μf, Cc = 1 μf, Rs =2kΩ

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PRACTICAL CALCULATIONS:


        Vi1 =
        Vo1 =




        Av1 =       =



        Vi2 = Vo1
        Vo2 =



        Av2 =       =




       Av =Av1*Av2 =




       Av =         =




OBSERVATIONS:


   Frequency (Hz)       Voltage Gain




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INPUT WAVE FORM :




OUT PUT WAVE FORM OF STAGE 1 :




OUT PUT WAVE FORM OF STAGE 2 :




FREQUENCY RESPONSE :




BAND WITH:   f2 - f1 = Hz



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RESULT: The RC coupled amplifier is simulated, the frequency response is
            observed and the bandwidth is noted.

VIVA QUESTIONS:

   1.   What is the necessity of cascading?
   2.   Define 3-dB bandwidth.
   3.   Why RC-coupling is preferred in audio range.
   4.   Explain various types of capacitors.
   5.   What is loading effect?
   6.   What is meant by RC coupling?




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                     3. RC PHASE SHIFT OSCILLATOR

AIM: To construct and simulate the RC phase shift oscillator and to verify the
      frequency of oscillation.

 CIRCUIT DIAGRAM:




     THEORY:

      RC-Phase shift Oscillator has a CE amplifier followed by three
     sections of RC phase shift feed back networks. The out put of the last
     stage is return to the input of the amplifier. The values of R and C are
     chosen such that the phase shift of each RC section is 60º. Thus The
     RC ladder network produces a total phase shift of 180º between its
     input and output voltage for the given frequencies. Since CE Amplifier
     produces 180 º phases shift the total phase shift from the base of the
     transistor around the circuit and back to the base will be exactly 360º or
     0º. This satisfies the Barkhausen condition for sustaining oscillations
     and total loop gain of this circuit is greater than or equal to 1, this
     condition used to generate the sinusoidal oscillations.
     The frequency of oscillations of RC-Phase Shift Oscillator is,



                                  f=

PROCEDURE:

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  1. Select different components and place them in the grid and simulate the
     circuit.
  2. Observe the output signal and note down the output amplitude and time
     period (Td).
  3. Calculate the frequency of oscillations theoretically and verify it practically
     (f=1/Td).
  4. Calculate the phase shift at each RC section by measuring the time shifts (Tp)
     between the final waveform and the waveform at that section by using the
     below formula.


OBSERVATIONS :
THEORITICAL CALCULATIONS : R = 10000, C = 0.001 μf



                 f=                   =          = 6.497 kHZ




PRACTICAL CALCULATIONS:

                 Td =

                 f=      =




                                0
            (1). θ 1=    *360         =

           (2). θ 2 =        * 3600   =




         (3). θ 3=      *3600 =




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OUT PUT WAVE FORM :




OUT PUT WAVE FORM AT POINT 1 (i. e., θ= 600):




OUT PUT WAVE FORM AT POINT 2 (i. e., θ= 1200):




OUT PUT WAVE FORM AT POINT 3 (i. e., θ= 1800):




RESULT : RC phase shift oscillator is simulated and the phase shift at points 1, 2 &
3 is noted.


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VIVA QUESTIONS:


  1. Mention the conditions for oscillations in RC phase shift oscillator?
  2. Give the formula for frequency of oscillations in RC phase shift oscillator?
  3. The phase produced by a single RC network is RC phase shift oscillator?
  4. RC phase shift oscillator uses positive feedback or negative feedback?
  5. The phase produced by basic amplifier circuit in RC phase shift oscillator is?
  6. What is the difference between damped oscillations undamped oscillations?
  7. What are the applications of RC oscillations?
  8. How many resistors and capacitors are used in RC phase shift feedback
     network.
  9. How the Barkhausen criterion is satisfied in RC phase shift oscillator
  10. Mention the basic reason for any oscillations.




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                      4. CLASS A POWER AMPLIFIER


AIM: To simulate and verify the efficiency of class A power amplifier.


CIRCUIT DIAGRAM:




THEORY:
      The function of power amplifier is to raise the power level of input signal.
Class A power amplifier is one in which the output current flows during the entire
cycle of input signal. Thus the operating point is selected in such away that the
transistor operates only over the linear region of its load line. So this amplifier can
amplify input signal of small amplitude. As the transistor operates over the linear
portion of load line the output wave form is exactly similar to the input wave form.
Hence this amplifier is used where freedom from distortion is the prime aim.


PROCEDURE:
   1. Select different components and place them in the grid.
   2. Apply the input ac signal voltage of 160mV (p-p) and simulate the circuit.
   3. Observe the output wave form on CRO and measure the output voltage V0.
   4. Now connect the ammeter at collector terminal of transistor.




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  5. Disconnect the ac signal from input and measure the collector current Ic in
     ammeter.
  6. calculate the efficiency by using practical calculations compare it with
     theoretically calculated efficiency


OBSERVATION :
THEORITICAL CALCULATIONS :




                               ICQ =




                               ICQ =




                         Pin(dc) =             =




                        Po(a.c)       =




                       (Imax – Imin) =



                       (Vmax –Vmin) = VCC



                     Po(a.c)      =        =
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      % of efficiency =            *100=            * 100=25%




PRACTICAL CALCULATIONS :

                     IC =

                  Pin(d.c) = VCC*ICQ =



                Po(a.c)     =       =




               % of efficiency =           *100 =


IN PUT WAVE FORM:




OUT PUT WAVE FORM :




RESULT: The efficiency of class A Power amplifier is verified.


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VIVA QUESTIONS:
1. Explain class A operation?
2. What is phase shift of input and output signals in class A operation?
3. What is the efficiency of class A power amplifier?
4. Distinguish class A and class B operations
5. What is the formula for the input and output power in class A power amplifier?




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       5. CLASS B COMPLEMENTARY SYMMETRY PUSH PULL
                                    AMPLIFIER


AIM: To simulate and verify the efficiency of class B complementary symmetry push
pull amplifier.


CIRCUIT DIAGRAM:




THEORY:


       Complementary means the circuit uses two identical transistors but one is
NPN and other is PNP. The symmetry means the biasing resistors connected in both
transistors are equal. As a result of this, emitter base junction of each transistor is
biased with the same voltage.


       During the positive half cycle of ac input the base emitter voltage of both
transistors becomes positive. Under this condition only NPN transistor conducts,



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while PNP transistor is cutoff. During this process positive half cycle current flows
through load resistor R5.


      During negative half cycle of ac input only PNP transistor conducts and NPN
transistor is cutoff and the negative half cycle current flows through R 5. We get a
complete amplified wave form of input signal. This amplifier circuit has a unity gain
because of the emitter follower configuration is used



PROCEDURE:


   1. Select different components and place them in the grid.
   2. Apply the input ac signal voltage of 0.8V (p-p) and simulate the circuit.
   3. Observe the output wave form on CRO and measure the output voltage Vo.
   4. Now connect the ammeters at collector terminals of NPN and PNP transistors.
   5. Disconnect the ac signal from input and measure the collector currents Ic1
      and Ic2 in ammeters.
   6. Calculate the efficiency by using practical calculations
   7. Compare it with theoretically calculated efficiency


OBSERVATIONS :
THEORITICAL CALCULATIONS :




                            ICQ =



                            Pin(d.c) = VCC*ICQ




                            Pin(d.c) =           =




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                                                –          –
                     Po(a.c)    =




                          (Imax – Imin) =



                      ( Vmax –Vmin) = VCC




                     Po(a.c)    =                =




            % of efficiency =               =        *100 = ------------------- *100




                                    =   *100 = 78.5%



PRACTICAL CALCULATIONS :


 IC1 =
 IC2 =


 IC =        =




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  ICQ =

  VCC =


 Vo(p-p) =

  Po(a.c) =


  Pin(d.c) = VCC*ICQ
                     Po(a.c)
  % of efficiency = ----------- *100
                     Pin(d.c)




INPUT WAVE FORM:




OUT PUT WAVE FORM:




RESULT: The efficiency of class B complementary symmetry push pull amplifier is
             verified




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VIVA QUESTIONS:
  1. Explain complementary and symmetry concept?
  2. What is the conduction angle in class B operation?
  3. What is the efficiency of class B power amplifier?
  4. what will be change in the above circuit if the two transistors are
     interchanged?
  5. what is the formula for output power in class B power amplifier?




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                    ELECTRONIC CIRCUITS LAB

                                 (HARDWARE)



  1. Two Stage RC Coupled Amplifiers.
  2. Class A power amplifier
  3. Class B complementary symmetry push pull amplifier
  4. Series Voltage Regulator.
  5. Shunt Voltage Regulator.
  6. Class B power Amplifier.




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                 1. TWO STAGE RC COUPLED AMPLIFIER
AIM : To design and construct RC coupled amplifier and verify the voltage gain,
observe the frequency response and find the bandwidth.


APPARATUS:

   1.   Transistors(BC-107)-2
   2.   Resistors -2KΩ -1, 68KΩ - 2, 27KΩ - 2, 2.2KΩ -2, 1.8KΩ - 2, 330Ω -2
   3.   Capacitors-1µF -2,10µF -1,100µF -2
   4.   Regulated Power Supply (0-30V)
   5.   Cathode Ray Oscilloscope
   6.   Bread board


CIRCUIT DIAGRAM :




THEORY:

       RC is the most widely used coupling as it provides excellent audio fidelity. A
coupling capacitor is used to connect output of first stage to the input of the second
stage. Resistances R1, R2, R5, R3, R4 and R10 form biasing and stabilisation network.
Emitter bypass capacitors C5 and C6 offer low reactance paths to the signals. The
coupling capacitor C3 transmits ac signal and blocks dc signal. Cascaded stages
amplifies signal and overall gain is improved. The total gain is less than the product
of gains of individual stages. Thus overall gain of two stages is
A = A1 x A2, where A1 = Voltage gain of first stage and A2 = Voltage gain of second
stage


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       When ac signal is applied to the base of the transistor Q1, its amplified output
appears across the collector resistor R9. It is given to the second stage for further
amplification and signal appears with more strength. Frequency response curve is
obtained by plotting a graph between frequency and gain in dB. The gain is
constant in midband frequency range and gain decreases in low and high frequency
ranges. The gain decreases in the low frequency range due to coupling capacitor C 3
and at high frequencies due to junction capacitance Cbe .

PROCEDURE:

1.  Connections are made as per the circuit diagram.
2.  Apply input by using function generator to the circuit.
3.  Observe the output waveform on CRO.
4.  Measure the voltage at
        (i) Output of the first stage
         (ii) Output of the second stage
5. From the readings, calculate voltage gain of first stage, second stage and overall
   gain. Disconnect second stage and then measure output voltage of first stage and
   calculate voltage gain.
6. Compare it with the voltage gain obtained when second stage was connected.
7. For plotting the frequency response, the input voltage is kept constant at 2mv (p-
   p) and the     frequency is varied from 100Hz to 1MHz.
8. Note down the value of output voltage for each frequency.
9. All the readings are tabulated and voltage gain in dB is calculated by using the
   expression
                    Av =20 Log 10 (Vo/Vi)
10. A graph is drawn by taking frequency on X-axis and gain in dB on Y-axis on a
    Semilog graph         sheet.
11. The bandwidth of the amplifier is calculated from the graph using the
     expression
                    Bandwidth = f2 – f1.
       Where f1 = Lower cutoff frequency of CE amplifier.
                f2 = Upper cutoff frequency of CE amplifier

THEORITICAL CALCULATIONS :
DC Analysis :
Calculation of RC& RE :

Given Ic = 1mA, Vce= 5V , VE =2V for the operating point to be approximately at
the centre point with this data.


     IB =    =       = 0.025mA



     IE = IB + Ic = 0.025mA + 1mA = 1.025mA


Choose VE =2V then       RE =    =           = 1.95 kΩ


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      Then Vc =VCC – (VE + Vce ) = 9 – ( 2 + 5 ) = 2V


           RC =           =       = 2kΩ


It is recommended that RE must be less than RC is selected
            RE = 1kΩ and RC = 2kΩ

Calculation of R3 & R4 :

The Thevinins equivalent voltage at base



    VB =             VCC and is equal to sum of VBE & VE.


        VBE + VE = 0.7 + 2 = 2.7V



             =            =           = 0.3



                  R3 = 2.33* R4


 Choose the current flowing through R4 as I4



                   I4 =       =          = 100 μA




                  R4 =            =       = 27kΩ


                    R4 = 2.33kΩ, R3 = 27kΩ

      Select R3 = 2.2k Ω, R4 = 27k Ω
AC Analysis:
The voltage gain of an amplifier can be taken as

         RL’
 Av = -------- = 10
         Re

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 Where Re =              =           = 25Ω



Av =       = 10 => RL’ = 250Ω

   RL’ = RC//RL = 2.2kΩ// RL => RL = 282Ω

There is resistance offered between collector and emitter choose RL = 300 Ω . For ac
analysis select
         Ce = 100μf ,Cc = 1 μf, Rs =2kΩ


PRACTICAL CALCULATIONS:

           Vi1 =

           Vo1 =



           Av1 =             =



                 =

              =

                 =

             =       *           =

             =           =



OBSERVATIONS:

         Frequency(Hz)               Output voltage(Vo)   Voltage gain in dB
                                                          Av =20 log 10 (Vo/Vi)




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                                                                              36


INPUT WAVE FORM :




OUT PUT WAVE FORM OF STAGE 1 :




OUT PUT WAVE FORM OF STAGE 2 :




FREQUENCY RESPONSE :




BAND WITH:     f2 - f1 = Hz


RESULT: The RC coupled amplifier voltage gain is verified, the frequency response
 is observed and the bandwidth is noted.


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                                                          37



VIVA QUESTIONS:

  1.   What is the necessity of cascading?
  2.   Define 3-dB bandwidth.
  3.   Why RC-coupling is preferred in audio range.
  4.   Explain various types of capacitors.
  5.   What is loading effect?
  6.   What is meant by RC coupling?




                     2. CLASS A POWER AMPLIFIER


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AIM: To simulate and verify the efficiency of class A power amplifier.


CIRCUIT DIAGRAM:




THEORY:
      The function of power amplifier is to raise the power level of input signal.
Class A power amplifier is one in which the output current flows during the entire
cycle of input signal. Thus the operating point is selected in such away that the
transistor operates only over the linear region of its load line. So this amplifier can
amplify input signal of small amplitude. As the transistor operates over the linear
portion of load line the output wave form is exactly similar to the input wave form.
Hence this amplifier is used where freedom from distortion is the prime aim.


PROCEDURE:
   1. Select different components and place them in the grid.
   2. Apply the input ac signal voltage of 160mV (p-p) and simulate the circuit.
   3. Observe the output wave form on CRO and measure the output voltage V0.
   4. Now connect the ammeter at collector terminal of transistor.
   5. Disconnect the ac signal from input and measure the collector current Ic in
      ammeter.
   6. calculate the efficiency by using practical calculations compare it with
      theoretically calculated efficiency

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                                                  39



OBSERVATION :
THEORITICAL CALCULATIONS :




                         ICQ =




                        ICQ =




                   Pin(dc) =          =   =




                  Po(a.c)    =




                 (Imax – Imin) =



                 (Vmax –Vmin) = VCC

                 Po(a.c)    =         =




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      % of efficiency =          *100 =                *100 = 25%




PRACTICAL CALCULATIONS :
                  IC =

                  Pin(d.c) = VCC*ICQ =



                Po(a.c)   =        =



                                   Po(a.c)
              % of efficiency = ------------- *100 =
                                  Pin(d.c)
IN PUT WAVE FORM:




OUT PUT WAVE FORM :




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RESULT: The efficiency of class A Power amplifier is verified.


VIVA QUESTIONS:
1. Explain class A operation?
2. What is phase shift of input and output signals in class A operation?
3. What is the efficiency of class A power amplifier?
4. Distinguish class A and class B operations
5. What is the formula for the input and output power in class A power amplifier?




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       3. CLASS B COMPLEMENTARY SYMMETRY PUSH PULL
                                    AMPLIFIER


AIM: To simulate and verify the efficiency of class B complementary symmetry push
pull amplifier.


CIRCUIT DIAGRAM:




THEORY:


       Complementary means the circuit uses two identical transistors but one is
NPN and other is PNP. The symmetry means the biasing resistors connected in both
transistors are equal. As a result of this, emitter base junction of each transistor is
biased with the same voltage.


       During the positive half cycle of ac input the base emitter voltage of both
transistors becomes positive. Under this condition only NPN transistor conducts,



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while PNP transistor is cutoff. During this process positive half cycle current flows
through load resistor R5.


      During negative half cycle of ac input only PNP transistor conducts and NPN
transistor is cutoff and the negative half cycle current flows through R 5. We get a
complete amplified wave form of input signal. This amplifier circuit has a unity gain
because of the emitter follower configuration is used



PROCEDURE:


   1. Select different components and place them in the grid.
   2. Apply the input ac signal voltage of 0.8V (p-p) and simulate the circuit.
   3. Observe the output wave form on CRO and measure the output voltage V o.
   4. Now connect the ammeters at collector terminals of NPN and PNP transistors.
   5. Disconnect the ac signal from input and measure the collector currents Ic1
      and Ic2 in ammeters.
   6. Calculate the efficiency by using practical calculations
   7. Compare it with theoretically calculated efficiency


OBSERVATIONS :
THEORITICAL CALCULATIONS :




                            ICQ =

                            Pin(d.c) = VCC*ICQ



                            Pin(d.c) =              =




                                         –              –
              Po(a.c)   =


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                                                                         44




                                 (Imax – Imin) =




                             ( Vmax –Vmin) = VCC




                            Po(a.c)   =            =




                            % of efficiency =          - *100 =   *100




                                          =     *100 = 78.5%



PRACTICAL CALCULATIONS :


 IC1 =
 IC2 =
            IC1+IC2
 IC =    -------------- =
                2
             IC

 ICQ =        =

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                                                                             45



  VCC =
  Vo(p-p) =

  Po(a.c) =


  Pin(d.c) = VCC*ICQ

  % of efficiency =           *100




INPUT WAVE FORM:




OUT PUT WAVE FORM:




RESULT: The efficiency of class B complementary symmetry push pull amplifier is
           verified




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                                                                               46




VIVA QUESTIONS:
  1. Explain complementary and symmetry concept?
  2. What is the conduction angle in class B operation?
  3. What is the efficiency of class B power amplifier?
  4. what will be change in the above circuit if the two transistors are
     interchanged?
  5. what is the formula for output power in class B power amplifier?




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                                                                                    47




                       4. SERIES VOLTAGE REGULATOR

AIM: To design, construct and plot the load regulator characteristics of series voltage
regulator


APPARATUS:

   1.   Transistors – SL 100 -2
   2.   Zener diode – 6.2V
   3.   Resistors – 270Ω, 1KΩ, 2.2KΩ, 6.8KΩ, 8.2KΩ
   4.   Decade Resistance Box
   5.   Ammeter (0-100mA)
   6.   Multimeter
   7.   Regulated Power Supply
   8.   Bread board

CIRCUIT DIAGRAM:


(1) LINE REGULATION:




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(2) LOAD REGULATION:




THEORY:
                Voltage regulator converts a dc input voltage in to a chosen dc
voltage which is stable under conditions of load current and input variation. A series
regulator using an additional transistor as an error amplifier, it improves the line and
load regulation of the circuit. Resistor R2 and zener diode are the reference source.
Transistor Q2 and its associated circuit components constitute the error amplifier,
that controls the series pass transistor. When the circuit output changes, the change
is amplified by transistor Q2 and fed back to the base of Q1 to correct the output
voltage level. Now suppose Vo decreases , VBE2 decreases .Because emitter voltage
of Q2 is held at Vz, any decrease in VBE2 appears across the base emitter of Q2.A
reduction ib VBE2 causes IC2 to be reduced,VR1 is reduced and VB1 is increased
causing the output voltage increase.


DESIGN:

Select Vz =0.75*Vo = 0.75* 8V = 9V

For D1, use a IN (    ) Zener diode with Vz= 6.2V

For minimum D1 current,

Select IR2 = 10mA




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                                                                                 49


                            –
R2 =              =             = 290 Ω ( use 270 Ω standard value



IE1(max) = IL(max) + IR2= 40mA + 10mA = 50mA


Specification for Q1,

VCE1(max) = VS = 20V

IC1(max) = IE(max) =50mA

PD(max) =( VS – Vo)* IE1(max) = (20V – 8V)*50mA = 600mW

Assuming hFE1(min) = 50,



IB1(max) =              =       = 1mA



IC2 > IB1(max)

Select IC2 =5mA



R1 =                             =                     = 1.89 kΩ (use 1.8 kΩ
standard value)


IZ = IE2(max) + IR2 = 5mA +10mA = 15mA

I4 > > IB1(max)

I4 = 1mA



R4 =              =                             (use 6.8kΩ standard value)




           R3 =         =               =    = 2.2KΩ




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                                                                                  50


PROCEDURE:

Line Regulation:

   1. Connections are made as per the circuit diagram.
   2. Using the regulated power supply vary the input voltage and note down the
      corresponding output voltage.

Load Regulation:

   1. Connections are made as per the circuit diagram.
   2. Keep the input voltage constant at which the line regulation is obtained and
      DRB is kept at 10KΩ.
   3. By go on decreasing the load resistance, note down the load current and load
      voltages.
   4. Calculate the % load regulation using the following formula
      % Load regulation = (VNL – VFL) / VFL × 100
      Where VNL = Input voltage at which the line regulation is obtained
   5. Plot the graph of load resistance versus % Load regulation


OBSERVATIONS :

LINE REGULATION :


        S.NO        INPUT VOLTAGE (V)               OUTPUT VOLTAGE (V)




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                                                                                  51




LOAD REGULATION :

  S.NO       LOAD                   LOAD              LOAD           % LOAD
             RESISTANCE             CURRENT           VOLTAGE        REGULATION




PRECAUTIONS:

1. Transistor terminals must be identified properly

RESULT: A 9V series voltage regulator is designed, constructed and load regulation
          characteristics is verified.

VIVA Questions:

   1.   What is Regulation?
   2.   What are the characteristics of voltage regulator?
   3.   What is Stabilization factor?
   4.   Why it is called as series regulator?
   5.   Why series regulator is also called as negative feedback regulator?
   6.   What is the purpose of current limiting circuit?
   7.   What is the disadvantage of current limiting circuit? How we can avoid that.
   8.   What is ripple rejection and output voltage in 7805 voltage regulator?
   9.   Using the 7812 voltage regulator, design a current source that will deliver a
        0.5A current to a 25Ω, 10W load.




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                                                                                 52


                        5. SHUNT VOLTAGE REGULATOR

AIM: To design, construct and plot the load regulator characteristics of shunt
     voltage regulator

APPARATUS:

   1.   Transistors – SL 100 -2
   2.   Zener diode – 6.2V
   3.   Resistors – 100Ω, 220Ω, 1KΩ
   4.   Decade Resistance Box
   5.   Ammeter (0-100mA)
   6.   Multimeter
   7.   Regulated Power Supply
   8.   Bread board

CIRCUIT DIAGRAM:

(1) LINE REGULATION:




(2) LOAD REGULATION:




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THEORY:
                 If control element is connected in shunt with the load the regulator
circuit is called shunt voltage regulator. The unregulated input voltage Vin tries to
provide the load current, but part of the current is taken by the control element, to
maintain a constant voltage across the load. If there is any change in load voltage
the sampling circuit provides a feedback signal to the comparator circuit. The
comparator circuit compares the feedback signal with the reference voltage and
generates a control signal which decides the amount of current required to be
shunted to keep the load voltage constant. Now suppose if load voltage increases
than comparator circuit decides the control signal based on the feedback information
which draws increased shunt current ISH value Due to this load current decreases and
hence the load voltage decreases to its normal value. Thus control element
maintains the constant output voltage by shunting the current, hence the regulator
circuit is called a shunt voltage regulator.


PROCEDURE:

Line Regulation:

   1. Connections are made as per the circuit diagram.
   2. Using the regulated power supply vary the input voltage and note down the
      corresponding output voltage.

Load Regulation:

   1. Connections are made as per the circuit diagram.
   2. Keep the input voltage constant at which the line regulation is obtained and
      DRB is kept at 10KΩ.
   3. By go on decreasing the load resistance, note down the load current and load
      voltages.
   4. Calculate the % load regulation using the following formula
      % Load regulation = (VNL – VFL) / VFL × 100
      Where VNL = Input voltage at which the line regulation is obtained
   5. Plot the graph of load resistance versus % Load regulation


OBSERVATIONS:

LINE REGULATION :

        S.NO         INPUT VOLTAGE (V)               OUTPUT VOLTAGE (V)




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                                                  54




LOAD REGULATION :

 S.NO   LOAD         LOAD      LOAD      % LOAD
        RESISTANCE   CURRENT   VOLTAGE   REGULATION




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PRECAUTIONS:

   1. Transistor terminals must be identified properly

RESULT: A 9V shunt voltage regulator is constructed and load regulation
characteristics are verified.


VIVA Questions:

   1.   What is Regulation?
   2.   What are the characteristics of voltage regulator?
   3.   What is Stabilization factor?
   4.   Why it is called as shunt regulator?
   5.   Why series regulator is also called as negative feedback regulator?
   6.   What is the purpose of Fold back circuit/
   7.   What is the disadvantage of current limiting circuit? How we can avoid that.
   8.   What is ripple rejection and output voltage in 7805 voltage regulator?
   9.   Using the 7812 voltage regulator, design a current source that will deliver a
        0.5A current to a 25Ω,10W load.




JNTUWORLD                                                                    Page 55

				
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Anil kumar Gorantala Anil kumar Gorantala
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