PLL_Soumya_Amrit

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Design and Analysis of a 400 MHz Phase Locked Loop
ENEE 614

Amrit Bandyopadhyay
Soumya Krishnamoorthy

1. Introduction

Phase-Locked Loop (PLL) circuits are used for frequency control and synthesis. Figure 1
contains a block diagram of a basic PLL.

Φin Charge
Phase pump and
NΦin detector VCO
filter

Vout, Φout,, fout

1/N

Fig.1

The circuit operation is typical of all phase-locked loops. It is a feedback system that
continually monitors and corrects any deviation in the phase difference between the input
and output signals. The PLL consists of the following blocks as indicated in Fig 1. The
phase detector determines and amplifies any phase differences between the input and the
feedback signal. Normally the frequencies of both signals will be nearly the same. The
phase detector output is a voltage proportional to the phase difference between the two
inputs. This signal is applied to the loop filter. The loop filter determines the PLL's
dynamic characteristics. The filtered signal controls the VCO. Note that the VCO output
is at a frequency that is N times the input supplied to the frequency reference input. This
output signal is sent back to the phase detector via the divide-by-N counter.

Normally, the loop filter is designed to match the characteristics required by the PLL's
application. If the PLL is to acquire and track a signal, the loop filter bandwidth will be
greater than if it expects a fixed-input frequency. The frequency range which the PLL
will accept and lock on is called the capture range. Once the PLL is locked and tracking a
signal, the range of frequencies the PLL will follow is called the tracking range.
Generally, the tracking range is larger than the capture range. The loop filter also
determines how fast the signal frequency can change and still maintain lock. This is the
maximum slewing rate. The narrower the loop filter bandwidth, the smaller the
achievable phase error. This comes at the expense of slower response and reduced
capture range.

The report talks in detail about each block in the PLL and analyses the results obtained.
2. Phase Frequency Detector (PFD)

The phase detector serves as an error amplifier, detecting and amplifying the phase error
between the input and the feedback signal. The loop is said to be locked when this phase
error is a constant. The schematic diagram of the Phase frequency detector is shown in
Fig 2a., and the design for the edge triggered D flip flop used in the PFD is indicated in
Fig 2b.

Fig. 2a Fig. 2b
The advantage of using a phase frequency detector over an XOR detector is that the PFD
does not lock on harmonics of the data (PDIN1 in Fig 2a). Also the width of the inputs
PDIN1 and PDIN2 is irrelevant. However the PFD has poor noise rejection because a
false edge in either input will drastically affect the output of the PFD.

Fig 3a
Fig. 3b

Fig 3a. indicates PDIN1 and PDIN2 with a phase difference indicated by pdout1. The
width of the signal pdout1 includes the propagation delay through the D flip flop and
therefore larger than the phase difference between the two signals. From Fig 3b, Gain of
the PFD , KPDI = Ipump/2π = 246 μA/2π.

3. Charge Pump and Loop Filter

The output of the PFD has to be combined into a single output to drive the loop filter.

M1
R1
M2
C1 C2
R2

Fig 4 Fig 5

As seen in Fig 4, the outputs from the PFD are fed into the charge pump. The currents
through transistors M1 and M2 is regulated and provides a robust solution to power
supply variations. The output of the charge pump is then supplied to the loop filter. The
filter with simply the R1-C1 stage generates a pole that results in instability as can be seen
in Fig 5. The resistor R2 introduces a zero for improved stability.
The Loop filter function can be derived to be as follows:
KF = 1+ sR2C1
---------------------------------
s2R1R2C1C2 + sR1(C1+C2) +1

In order to get ideal damping factor of 0.7 (detailed analysis in future section), the
following values for filter resistors and capacitors were used. R1 =5K, R2= 1K, C1= 1nF,
C2= 10pF. However as this increases lock acquisition time significantly, we utilized an
under-damped system for our purposes with C1= 1pF.

Fig. 6
Fig. 6 indicates the output of the loop filter at 390MHz locking at 8.56 us. The fluctuation
in this voltage after lock is due to greater than required currents being sunk and sourced
by the charge pump. Optimal sizing will result in larger lock acquisition times. These
fluctuations cause the VCO frequency to fluctuate as well, resulting in phase errors.
Further analysis is presented in a future section.
4. Current Starved VCO

The current starved VCO is similar to the ring oscillator. The MOSFETS connected to
the VDD and GND of the inverter limit the current available to it. The two MOSFETS to
the left of the inverter loop have the same drain currents and are set by the input control
voltage. The current in them are mirrored in each inverter/current source stage. The
design has seven inverter stages as shown in figure 7.

Fig. 7

Fig. 8a is plot of output frequency of the VCO against the input voltage, and fig 8b is a
close up into the lock range (370M-430MHz) of the PLL where the output frequency is
linearly dependent on the input voltage. The gain of the VCO block (KVCO) is the slope of
the curve shown in fig. 8b the value for the design is 2π*60MHz/0.4V. This linear range
of VCO input thus determines the lock in range of the PLL ( in our case 60MHz).

Fig. 8a Fig.8b
5. Phase locked Loop Analysis

The loop equation for the PLL can be derived to be:

KPDI KF KVCO
H(s) = -------------------------
s + KPDI KF KVCO

KPDI KVCO (1+sR2C1)
-----------
R1R2C1C2
= ----------------------------------------------------
s3 + s2 (C1+C2) + s KPDI KVCO + KPDI KVCO
------------- ------------ ------------
R2C1C2 R1C2 R1R2C1C2

Thus ωn3 = KPDI KVCO / R1R2C1C2, 2 ωn2ς = KPDI KVCO/ R1C2.. Also, the capture range
(ω) in the design was chosen as 60 MHz (the linear range of the VCO). For critical
damping, ς = 0.577. The lock acquisition time is given by

Tp = 2 R1C1 ln [KVCO/Ipump]
------------------ = 8ms.
[KVCO/Ipump - ω]

Using these design equations at critical damping, R1 =5K, R2= 1K, C1= 1.12nF, C2=
10pF. Physically what determines the lock acquisition time is the RC time constant of
the filter and the amount of current sourced and sunk in by the charge pump. Smaller
currents sourced and sunk in by the pump implies smaller corrections to the loop each
cycle and reduced oscillations on the input VCO voltage. Thus a larger time is required
for the filter to generate the optimal input voltage to the VCO so that it locks. Also larger
the RC time constant induced by the filter, larger the acquisition time.

However choice of C1as 1.12nF increases lock acquisition time significantly, we utilized
an under-damped system for our purposes with C1= 1pF. (lock acquisition time is around
8us in theory and we see 8.56us in the simulation.)
Fig. 9
Figure 9 indicates the output phase locked with the input at 390Mhz. The phase
difference between the two is not a constant. As discussed in section 3, the VCO input
fluctuates introducing a frequency variation at the output. Thus the circuit has a self-
generated jitter. This is indicated in Fig 10. The plot indicates a jitter of 250 ps (0.1
UI/10% of the input pulse width).

Fig. 10

In order to plot this, a SAW tooth wave with frequency identical to the input frequency
was generated. The rise time of the SAW tooth wave is almost equal to the period of the
wave. The output wave was plotted as a function of the SAW tooth wave to generate the
jitter plot indicated above. What this implies is that the rising edge of the output wave
oscillates in this 250ps range once the system is in lock. A critically damped system
along with an optimally sized charge pump would significantly reduce this figure.
6. Conclusions

A 400MHz Phase locked loop has been designed. The lock range is 370MHz to 430 MHz
and the lock acquisition time at 390MHz is 8.56 us for the under damped system. The
self-generated jitter is 250 ps. The VCO linear range is 2.37V to 2.77V.