Reference Manual-Embeded System Development Kit

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					Embeded Systems Development Kit
                                     Cyclone Edition (EP1C6)
                                     Reference Manual




System Level Solutions, Inc. (USA)
14100 Murphy Avenue
San Martin, CA 95046
                                          Board Version:            3.0
(408) 852 - 0067
                                          Document Version:         1.6
http://www.slscorp.com                    Document Date:      July 2009
Copyright©2005-2009, System Level Solutions, Inc. (SLS) All rights reserved. SLS, an Embedded systems company, the
stylized SLS logo, specific device designations, and all other words and logos that are identified as trademarks and/or ser-
vice marks are, unless noted otherwise, the trademarks and service marks of SLS in India and other countries. All other
products or service names are the property of their respective holders. SLS products are protected under numerous U.S.
and foreign patents and pending applications, mask working rights, and copyrights. SLS reserves the right to make
changes to any products and services at any time without notice. SLS assumes no responsibility or liability arising out of
the application or use of any information, products, or service described herein except as expressly agreed to in writing by
SLS. SLS customers are advised to obtain the latest version of specifications before relying on any published information
and before orders for products or services.

rm_dbesd1c6_1.6




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Embedded Systems Development Kit Reference Manual (Cyclone Edition, EP1C6)                                      July 2009
                                                              About this Manual



Introduction             This manual provides component details about ESDK Board, Cyclone
                         Edition (EP1C6).

                         Table below shows the revision history of the reference manual.

                             Version         Date                         Description
                         1.6           July 2009         •    Modified Table 2.20 IDE Connector
                                                         •    Modified Table 2.4, SRAM Pin Table
                                                              (Added chip select description).
                         1.5           January 2009      •    Corrected typos
                         1.4           May 2008          •    Updated Table 2.20, IDE connector (J3)
                                                         •    Updated Table 2.4, SRAM Pin Table
                         1.3           September 2007 •       Correction of FPGA Pin No. in Table A,
                                                              Appendix A.
                         0.1.2         July 2006          Second publication of the Reference Manual
                                                          •    Changed the layout design
                                                          •    Updated Clock Chip Information
                                                          •    Added Appendix- Shared Bus Table
                         0.1.1         November 2005      First Publication of the Reference
                                                          Manual


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July 2009                     Embedded Systems Development Kit Reference Manual (Cyclone Edition, EP1C6)
How to Contact SLS




How to Contact                    For the most up-to-date information about SLS products, go to the SLS
                                  worldwide website at http://www.slscorp.com. For additional information
SLS                               about SLS products, consult the source shown below.

                                           Information Type                             E-mail
                                  Product literature services, SLS liter- support@slscorp.com
                                  ature services, Non-technical cus-
                                  tomer services, Technical support.


Typographic                       The Embedded Systems Development Kit Reference Manual, Cyclone
                                  Edition(EP1C6) uses the typographic conventions as shown below:
Conventions

            Visual Cue                                               Meaning
 Bold Type with Initial Capital       All headings and Sub headings Titles in a document are displayed in
 letters                              bold type with initial capital letters; Example: Features, Memory
                                      Components.
 Bold Type with Italic Letters        All Definitions, Figure and Table Headings are displayed in Italics.
                                      Examples: Figure 2-1.ESDK 1C6 Development Board Components,
                                      Table 2-1.ESDK 1C6 Development board Components & Interfaces.
1., 2.                                Numbered steps are used in a list of items, when the sequence of items
                                      is important. such as steps listed in procedure.

•                                     Bullets are used in a list of items when the sequence of items is not
                                      important.
                                      The hand points to special information that requires special attention




                                      The caution indicates required information that needs special consider-
                                      ation and understanding and should be read prior to starting or continu-
                                      ing with the procedure or process.




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            Visual Cue                                    Meaning
                          The warning indicates information that should be read prior to starting or
                          continuing the procedure or processes.



                          The feet direct you to more information on a particular topic.




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Typographic Conventions




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                                                                                                                                Contents



About this Manual.............................................................................................................. iii
      Introduction ..............................................................................................................................................iii
      How to find Information ..........................................................................................................................iii
      How to Contact SLS ................................................................................................................................ iv
      Typographic Conventions ........................................................................................................................ iv

1. Introduction ............................................................................................................................... 1
      Features ..................................................................................................................................................... 1
      General Description .................................................................................................................................. 2
          Block Diagram ................................................................................................................................... 3

2. Board Components................................................................................................................... 5
      Featured Device ........................................................................................................................................ 9
          The Cyclone EP1C6Q240 Device (U11)........................................................................................... 9
      Memory Components.............................................................................................................................. 11
          SDRAM Device (U6) ...................................................................................................................... 11
          SRAM Device (U7) ......................................................................................................................... 15
          Flash Memory Device (U8) ............................................................................................................. 17
          Serial Configuration Memory Device - EPCS1 (U15) .................................................................... 20
          I2C Memory - EEPROM (U16)....................................................................................................... 21
      Other Components .................................................................................................................................. 21
          I2C RTC (U5) .................................................................................................................................. 21
      User Interfaces ........................................................................................................................................ 22
          LEDs (D3,D4,D5,D6) ...................................................................................................................... 22
          Push Button Switches (SW4,SW5,SW6,SW7)................................................................................ 23
          DIP Switches (SW3) ........................................................................................................................ 24
          Liquid Crystal Display (U1) ............................................................................................................ 25
          Serial Port Connector (SER2).......................................................................................................... 29
          USB Connector (J12)....................................................................................................................... 31
          PS/2 Connector (JP1)....................................................................................................................... 33



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            Parallel Port (CON1) ....................................................................................................................... 34
            VGA Port (VGA CON) ................................................................................................................... 35
            I2C Bus Header(JP18) ..................................................................................................................... 37
       Expansion Connectors............................................................................................................................. 37
            Expansion Prototype Connector (J1, J2, J3, J4) .............................................................................. 38
            IDE Connector (J3) .......................................................................................................................... 41
       General Connector .................................................................................................................................. 43
            Active Serial & JTAG Header (JP11, JP12).................................................................................... 43
       Status LEDs & Reset/Power Switches.................................................................................................... 44
            Power (D12, D11) & Status (D8, D15) LEDs ................................................................................. 45
            Power Switch (SW2) ....................................................................................................................... 45
            User Defined Reset Push-Button Switch (SW8) ............................................................................. 46
            Reset Circuitry (U19)....................................................................................................................... 46
       Clock Circuitry........................................................................................................................................ 46
            Setting the Clocks ............................................................................................................................ 48
            Clock Select Jumper (JP3) ............................................................................................................... 48
            CPU Clock Select Jumper (J7) ........................................................................................................ 49
            PCI Clock Enable Jumper (J5)......................................................................................................... 50
            Clock Headers.................................................................................................................................. 50
            USER Clock Header (JP2)............................................................................................................... 50
            CPU Clock Header (JP4) ................................................................................................................. 51
            Reference Clock Header (JP19)....................................................................................................... 51
            Santa Cruz Header Clocks ............................................................................................................... 52
       Power Supply Circuitry........................................................................................................................... 52
            DC Power Input Jack (SW1) ........................................................................................................... 52
            ESDK 1C6 Board Power Supply ..................................................................................................... 52
            Power Supply Configuration Jumper (JP5) ..................................................................................... 53
            On-Board Power Regulators (U12, U13, U14)................................................................................ 54
            Power Plane Connectors (JP6-JP8, JP10)........................................................................................ 55
            DC Input power Header (JP8) ......................................................................................................... 55
            +5V Power Header (JP6) ................................................................................................................. 55
            +3.3V Power Header (JP7) .............................................................................................................. 56
            +1.5V Power Header (JP10) ............................................................................................................ 56
            Voltage Limiter Switches (U2-U3, U9-U10, U23-U30) ................................................................. 56

Appendix A: Shared Bus Table ..........................................................................................57

Appendix B: Clocking Chip Pin Configuration .................................................................59

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                                                                  1. Introduction



                         This document describes the hardware features of the ESDK Education Kit,
                         Cyclone Edition (EP1C6), here after referred to as ESDK 1C6 Board,
                         including detailed pin-out information, to enable designers to create custom
                         FPGA designs that interface with all components on the board.

Features                 The following are features of the ESDK 1C6 Board.
                             Altera EP1C6Q240 Device and EPCS1configuration device
                             Supports intellectual property based (IP-Based) design both with and
                             without a microprocessor
                             USB 1.1 (Full speed & Low speed)
                             RS 232 Port
                             Parallel port (IEEE 1284)
                             PS/2 Port
                             VGA port
                             IDE (Integrated Drive Electronics)
                             2 KBytes of I2C PROM(Expandable)
                             128 KBytes of SRAM
                             2 MBytes of FLASH
                             8 MByte of SDRAM
                             Supports multiple clocks like CPU clock, USB clock, PCI clock, and
                             IOAPIC clock.
                             JTAG and Active Serial download capability
                             5V tolerant Santa Cruz Expansion Card Header provides 74 I/Os for the
                             development of additional boards providing various functionalities.
                             One user definable 4-bit switch block
                             Four user definable push button switches, and one global reset switch
                             Four user definable LEDs
                             One 16x2 character LCD Module
                             I2C Real Time Clock




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                                                                                             Introduction




General                  The ESDK 1C6 Education Kit provides a powerful educational tool and also
                         a low-cost solution for prototyping and developing products rapidly. The
Description              board serves as an excellent means for system prototyping and emulation with
                         hardware as well as software development.

                         The board ships with a powerful Altera Cyclone FPGA providing around
                         6,000 Logic Elements. It allows hardware design engineer to design,
                         prototype hardware design using HDLs like Verilog or VHDL or any and test
                         IP cores. The entire environment helps to quickly implement any processor
                         as well as any real time operating system on the kit. Along with that one can
                         simulate and test ‘C’ or assembly code also. The board provides industry
                         standard interconnections, Memory Subsystem, Multiple clocks for system
                         design, JTAG Configuration, expansion headers for greater flexibility,
                         capacity and additional user interface features. Further, the board can be used
                         for DSP applications by interfacing directly to a DSP processor or
                         implementing DSP functions inside the FPGA. In short, it is a dual-purpose
                         kit, which can be used for prototyping and developing VLSI designs as well
                         as designing and developing microprocessor based embedded system
                         designs.

                         Figure 1-1. shows the top view of the board.




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General Description




Figure 1-1. ESDK 1C6 Board Top View




                               Block Diagram
                               Figure 1-2. shows the Block Diagram of ESDK 1C6 Board.




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                                                                                                                              Introduction




Figure 1-2. ESDK 1C6 Board Block Diagram



                                           PS/2 Port          Parallel Port           VGA Port
                           Board
                           Power
                           Supply

                                                       Level Shiter                                          Santacruz Long
                                                                                                            Expansion Header
                                                                                                             (74 User I/Os)

                  USB 1.1
                                              USB 1.1 Phy Chip
                   Port

                                                                                       Level
                                                                                      Shifters
             Serial Port




                                       RS232                                                                I2C RTC
                                     Tranciever
                                                                Altera                                        I2C
                                    EPCS Config                Cyclone                                       PROM
                                      PROM                  EP1C6/EP1C12
                                                                FPGA
                                                                                                 System Clock Chip


                                                                                                 User RESET PB SW
                                    AS    JTAG
                                Header    Header




                                                                                                                  Level
                                                                                                                 shifter
            4 LEDs              4-way DIP SW           4 PB SW        2 MB X 8    1 MB X 8       8 MB X 8
                                                                      CFI Flash    SRAM           SDRAM
                                                                                                                  16x2
                                                                                                              Character LCD
                                                                                                                 Display




                                              Next Section explains overview of all the ESDK 1C6 board components.




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                                                                                     2. Board Components



                                            This section introduces the important components of the ESDK 1C6 Board.
                                            Figure 2-1. below shows the components on the ESDK 1C6 Board.

Figure 2-1. ESDK 1C6 Board - Components
                                                                                      J3, J2, J4, J1
                                                                                      Expansion Prototype
                                                                                      Connector
                                                                           (J3)
                                                                           40 Pin Header            (J4)
                                                           (JP18)                                   20 Pin Header
                                                                                           (J2)
                                                           Headers for I2C Bus             14 Pin                   (J1)
                                                           Signals                         Header                   40 Pin Header
                                        VGA Port     (U16)                                                                          (SW2)
                                                     I2C Prom Chip                                                                  On-Off
                                                                                                                                    Switch
                        (CON1)                                                                                                               (SW1)
                        Parallel                                                                                                             Power
                        Port                                                                                                                 Connector
                                                                                                                                                   (JP3)
           (JP1)
                                                                                                                                                   Input Clock
           PS/2 Port
                                                                                                                                                   Selection
                                                                                                                                                   Headers
        (U22)
        USB PHY
        Chip




      (J12)
      USB Port                                                                                                                               (D12)
                                                                                                                                             +5 V Supply
          (SER2)                                                                                                                             LED
          Serial Port                                                                                                                   (D11)
          (D15)                                                                                                                         +3.3 V Supply
          Invalid Input Indicator LED                                                                                                   LED
                                                                                                                         (Y1)
                 (JP11)                                                                                                  Crystal
                                            (SW4)                                                              (U1)
                 ASI Connector                      (SW5)
                                                                                                   (U2)        Liquid Crystal
                         (JP12)                       (SW6)                                        Buffer Chip Display
                         JTAG Connector                 (SW7)                              (SW8) indicated with B
                                                                                           Global Reset
                                                                                           Switch
                                        User Push-button        (D6)
                                                                                   (SW3)
                                        Switches                   (D5)            4 User-definable
                                                                       (D4) (D3)
                                                                                   DIP Switches

                                                             User LEDs




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                                                                                          Board Components




                            Table 2-1 describes the major components on the ESDK 1C6 board and the
                            related interfaces.

Table 2-1. ESDK 1C6 Board Components & Interfaces
     Board Reference               Name                          Description                     Page
Featured Device
U11                      Altera Cyclone FPGA        Altera EP1C6Q240 Cyclone FPGA                  9
Memory Components
U6                       SDRAM                      ISSI Inc. IS42S16400B-7T, 8 MByte,            11
                                                    1 MBit x 16 bit x 4 banks 133 MHz
                                                    SDRAM
U7                       SRAM                       ISSI Inc. IS61LV6416L-10T, 128                15
                                                    KByte, 64KBit x 16 bit High Speed (10
                                                    ns) CMOS SRAM
U8                       Flash Memory               Excel Semiconductor Inc.                      17
                                                    ES29LV160DB-70RTC, 2 MByte,
                                                    2 MBit x 8 bit/1 MBit x 16 bit CMOS
                                                    Flash Memory (CFI Compliant)
U15                      Serial Configuration       Altera EPCS1, 4 MBit flash memory,            20
                         Memory Device              Serial Configuration Device used to
                                                    store FPGA configuration data
U16                      I2C EEPROM                 ISSI Inc. IS24C16, 16 KBit 2-wire             21
                                                    Serial CMOS EEPROM
Other Components
U5                       I2C RTC                    ST Microelectronics M41T00, 2-wire            21
                                                    Serial Access Timekeeper
User Interfaces
D3, D4, D5, D6           User-defined LEDs          Four user-defined LEDs                        22
SW4, SW5, SW6, SW7       User-defined Push But-     Four user-defined momentary-contact           23
                         ton Switches               push-button switches
SW3                      User-defined DIP Switch    One user-defined 4-way DIP Switch             24
U1                       Liquid Crystal Display     One 16 Character x 2 Line Liquid              25
                         (LCD)                      Crystal Display
SER2                     Serial Port                One Full-Modem Serial Port Connec-            29
                                                    tor (DB9)




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Table 2-1. ESDK 1C6 Board Components & Interfaces
     Board Reference                   Name                         Description                    Page
J12                         USB 1.1 Port               One USB 1.1 Device Connector                  31
                                                       (B-Type)
JP1                         PS/2 Port                  One PS/2 Device Connector (6-pin              31
                                                       Mini-Din)
CON1                        Parallel Port              One Parallel Port Connector (DB25)            34
VGA CON                     VGA Port                   One 3-bit VGA Output Connector                35
                                                       (DB15)
JP18                        I2C Bus Header             I2C Bus Interface Header, which sup-          37
                                                       ports adding of additional I2C Periph-
                                                       erals along with the on-board I2C
                                                       EEPROM (U16) and I2C RTC (U5)
Expansion Connectors
J1, J2, J3, J4              Expansion Prototype        Four Expansion Prototype connections          38
                            Connector                  consisting of Santa Cruz Short Expan-
                                                       sion Header and General purpose IO
                                                       headers that can be used for periph-
                                                       eral expansion using Daughter cards
                                                       or for debugging and prototyping pur-
                                                       poses.
General Connectors
JP11                        ASI connector              The active serial interface (ASI) con-        43
                                                       nector, used to program the EPCS1
JP12                        JTAG connector             The Joint Test Action Group (JTAG)            43
                                                       connector, used to directly configure
                                                       the EP1C6Q240 FPGA
JP2                         User Clock Input Header    Header that connects the external             50
                                                       Clock Input to the EP1C6Q240 FPGA
Jumpers
JP5                         Power Supply Jumper        Jumper that enables the input to the          53
                                                       ESDK Power Supply Circuitry.
JP3                         Clock Select Jumper        Jumper that determines the PLL clock          48
                                                       inputs to the EP1C6Q240 FPGA
J7                          CPU Clock Select           Jumper that selects 66.66 MHz/100             49
                            Jumper                     MHz as CPU Clock input to the
                                                       EP1C6Q240 FPGA


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                                                                                        Board Components




Table 2-1. ESDK 1C6 Board Components & Interfaces
      Board Reference             Name                          Description                     Page
J5                       PCI Clock Enable          Jumper that enables/disables PCI              50
                         Jumper                    Clock (33.33 MHz) input to the
                                                   EP1C6Q240 FPGA
J8                       USB Mode Select           Jumper that selects the FSEO Mode             33
                         Jumper                    for the USB Device
J9                       USB D+ Pull-Up Select     Jumper that enables the USB Device            33
                         Jumper                    detection as a Full Speed USB Device
J10                      USB D- Pull-Up Select     Jumper that enables the USB Device            33
                         Jumper                    detection as a Low Speed USB Device
J11                      USB Speed Select          Jumper that selects the USB Device            33
                         Jumper                    Speed as Low Speed or Full Speed
Test Points/Headers
JP6, JP7, JP10           Power Supply Test Points Various Power Supply test point              55,56,56
                                                  headers
JP4                      CPU Clock Test Point      CPU Clock output available on Header          51
                                                   from Clock Chip (as per J7 Selection).
                                                   This pin is not connected to the FPGA.
JP19                     IOAPIC Clock Test Point   14.318 MHz Clock output available on          51
                                                   Header from Clock Chip. This pin is
                                                   not connected to the FPGA.
Status LEDs & Reset/Power Switches
D12                      +5V Power LED             Indicates when +5V Power is Present           45
D11                      +3.3V Power LED           Indicates when +3.3V Power is Pres-           45
                                                   ent
D8                       C_DONE Status LED         Indicates successful configuration of         45
                                                   the EP1C6Q240 Cyclone FPGA on the
                                                   ESDK Board (CONFIG_DONEn is
                                                   asserted)
D15                      INVALIDn Status LED       Indicates if a valid RS232 input is pres-     45
                                                   ent at the Receiver inputs of the
                                                   RS232 Transceiver chip.
SW2                      Power Switch              Power switch that is used to apply            45
                                                   power to the on-board power regula-
                                                   tors



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Featured Device




Table 2-1. ESDK 1C6 Board Components & Interfaces
    Board Reference                   Name                          Description                      Page
SW8                         User-defined reset          User-defined reset push-button switch          46
                            push-button
Clocks
U18                         Clock Generator Chip        Clock chip (PI6C103), which provides           46
                                                        various clocks on the ESDK board
Power Supply
SW1                         DC Power Jack               6-9 V DC Power Source                          52
U12, U13, U14               On-board power              Three voltage regulators on the                54
                            regulators                  ESDK 1C6 Board

U2-U3, U9-U10, U23-         Voltage Limiter Switches    Protects EP1C6 from 5-V Logic                  56
U30                                                     levels


Featured Device                The Cyclone EP1C6Q240 Device (U11)
                               The ESDK 1C6 development board features the Altera Cyclone EP1C6Q240
                               FPGA (U11) in a 240-pin PQFP package. Table 2-2 lists the Cyclone device
                               features.

                                Table 2-2. Cyclone EP1C6Q240 Device Features
                                              Feature                                 Value
                                Logic Elements                         5980
                                RAM Blocks                             20
                                Total RAM Bits                         92160
                                PLLS                                   2
                                 User I/Os                             185*
                                     Note:
                                1.   *185 pins are for the PQFP package used on this ESDK 1C6 board

                               FPGA uses SRAM cells to store configuration data. Since SRAM memory is
                               volatile configuration, the data must be downloaded into Cyclone FPGA each
                               time the device powers up. There are three methods to configure the device:


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                                                                                       Board Components




                         Active serial configuration, Passive serial configuration, JTAG based
                         configuration. The ESDK 1C6 board supports the following two modes:
                               Active Serial Mode — Active serial configuration is carried out through
                               serial configuration device EPCS1. Serial configuration devices provide
                               a serial interface to access configuration data. During device configura-
                               tion, Cyclone FPGA read configuration data via the serial interface,
                               decompresses data if necessary, and program their SRAM cells. This
                               scheme is referred to as an “AS configuration scheme” because the
                               FPGA controls the configuration interface. The Quartus II software auto-
                               matically generates .pof files that can be downloaded into the configura-
                               tion device using Byte-Blaster II or USB Blaster Cable for Active Serial
                               Configuration.
                               JTAG Mode — JTAG (Joint Test Action Group) has developed a spec-
                               ification for boundary-scan testing. This boundary-scan test (BST) archi-
                               tecture offers the capability to efficiently test components on printed
                               circuit boards (PCBs) with tight lead spacing. The BST architecture can
                               test pin connections without using physical test probes and capture func-
                               tional data while a device is operating normally. The user can also use the
                               JTAG circuitry to shift configuration data into Cyclone FPGA. The
                               Quartus II software automatically generates .sof files that can be down-
                               loaded using Byte-Blaster II or USB Blaster Cable for JTAG configura-
                               tion.
                         1.    Cyclone is designed such that JTAG instructions have precedence over
                               any device operating modes. So JTAG configuration can take place
                               without waiting for other configuration to complete (e.g., configuration
                               using serial or enhanced configuration devices).
                               If the user attempts for the JTAG configuration in Cyclone FPGA dur-
                               ing non-JTAG configuration, the non- JTAG configuration will be ter-
                               minated and the JTAG configuration will be initiated.
                         2.    Passive configuration mode has not been supported on this board.
                         3.    This board does not support multiple devices using Active Serial mode.
                         Figure 2-2. displays the EP1C6Q240 Cyclone FPGA.




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Memory Components




                               Figure 2-2. EP1C6Q240 Cyclone FPGA




Memory                         This section describes the memory components on the ESDK 1C6 develop-
                               ment board.
Components
                               SDRAM Device (U6)
                               U6 is a 8 MByte Synchronous Dynamic RAM. It is organized as 1,048,576
                               bits X 16-bit X 4-bank for improved performance. The synchronous DRAMs
                               achieve high speed data transfer using pipeline architecture. All the input and
                               output signals refer to the rising edge of the clock input. Figure 2-3. shows the
                               SDRAM device.

                               Figure 2-3. SDARM Device




                               Figure 2-4. below shows the pin configuration of the SDRAM



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                                                                                   Board Components




                         Figure 2-4. SDARM Pin Configuration




                         Table 2-3 shows the SDRAM pin description with Cyclone FPGA device.




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Memory Components




                                Table 2-3. SDRAM (U6) Pin Table
                                 SDRAM (U6)         Pin Name          FPGA (U11)          Description
                                   Pin No.                              Pin No.
                                1                 VDD             ---              Supply
                                2                 DQ-00           94               Data Line
                                3                 VDDQ            ---              Supply
                                4                 DQ-01           96               Data Line
                                5                 DQ-02           98               Data Line
                                6                 GNDQ            -                GND
                                7                 DQ-03           100              Data Line
                                8                 DQ-04           102              Data Line
                                9                 VDDQ            ---              Supply
                                10                DQ-05           104              Data Line
                                11                DQ-06           106              Data Line
                                12                GNDQ            ---              GND
                                13                DQ-07           113              Data Line
                                14                VDD             ---              Supply
                                15                LDQM            77               Lower Byte, I/O Mask
                                16                WE_n            79               Write Enable Input
                                17                CAS_n           75               Column Address Strobe
                                18                RAS_n           76               Row Address Strobe
                                19                CE_n            119              Chip Enable Input
                                20                BA0             68               Bank Select Address
                                21                BA1             74               Bank Select Address
                                22                AD-10           66               Address Line
                                23                AD-00           93               Address Line
                                24                AD-01           88               Address Line
                                25                AD-02           87               Address Line
                                26                AD-03           86               Address Line
                                27                VDD             ---              Supply



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                                                                                      Board Components




                         Table 2-3. SDRAM (U6) Pin Table
                          SDRAM (U6)           Pin Name       FPGA (U11)            Description
                            Pin No.                             Pin No.
                         28                  GND             ---             GND
                         29                  AD-04           85              Address Line
                         30                  AD-05           84              Address Line
                         31                  AD-06           83              Address Line
                         32                  AD-07           63              Address Line
                         33                  AD-08           64              Address Line
                         34                  AD-09           65              Address Line
                         35                  AD-11           67              Address Line
                         36                  NC              ---             No Connection
                         37                  CKE             115             Clock Enable
                         38                  CLK             11              SDRAM Clock
                         39                  UDQM            82              Upper Byte, I/O Mask
                         40                  NC              ---             No Connection
                         41                  GND             ---             GND
                         42                  DQ-08           95              Data Line
                         43                  VDDQ            ---             Supply
                         44                  DQ-09           97              Data Line
                         45                  DQ-10           99              Data Line
                         46                  GNDQ            ---             GND
                         47                  DQ-11           101             Data Line
                         48                  DQ-12           103             Data Line
                         49                  VDDQ            ---             Supply
                         50                  DQ-13           105             Data Line
                         51                  DQ-14           107             Data Line
                         52                  GNDQ            ---             GND
                         53                  DQ-15           114             Data Line
                         54                  GND             ---             GND



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Memory Components




                               It should be noted that the address lines of the SRAM, FLASH and SDRAM
                               Memories are shared. Also the data lines of the SRAM, FLASH, SDRAM
                               Memories and LCD are shared.

                               SRAM Device (U7)
                               U7 is the 128 KBytes asynchronous SRAM device. It is a high speed,
                               1,048,576-bit static RAM organized as 65,536 words X 16 bits. It is fabri-
                               cated using the ISSI’s high performance CMOS technology. This highly reli-
                               able process is coupled with innovative circuit design techniques, yields
                               access times as fast as 10 ns with low power consumption. The arrow indi-
                               cated in Figure 2-5. shows the SRAM device on the development board.

                               Figure 2-5. SRAM Device




                               Table 2-4 describes signals and pin connections of SRAM.

                                Table 2-4. SRAM (U7) Pin Table
                                 SRAM (U7)        Pin Name        FPGA (U11)          Description
                                  Pin No.                           Pin No.
                                1              AD-15             76            Address Line
                                2              AD-14             75            Address Line
                                3              AD-13             74            Address Line
                                4              AD-12             68            Address Line
                                5              AD-11             67            Address Line



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                         Table 2-4. SRAM (U7) Pin Table
                         SRAM (U7)           Pin Name        FPGA (U11)             Description
                          Pin No.                              Pin No.
                         6                CE_n              116              Chip Select
                         7                DQ-00             94               Data Line
                         8                DQ-01             96               Data Line
                         9                DQ-02             98               Data Line
                         10               DQ-03             100              Data Line
                         11               VCC               ---              Supply
                         12               GND               ---              GND
                         13               DQ-04             102              Data Line
                         14               DQ-05             104              Data Line
                         15               DQ-06             106              Data Line
                         16               DQ-07             113              Data Line
                         17               WE_n              79               Write Enable Input
                         18               AD-10             66               Address Line
                         19               AD-09             65               Address Line
                         20               AD-08             64               Address Line
                         21               AD-07             63               Address Line
                         22               NC                ---              Not Connected
                         23               NC                ---              Not Connected
                         24               AD-06             83               Address Line
                         25               AD-05             84               Address Line
                         26               AD-04             85               Address Line
                         27               AD-03             86               Address Line
                         28               NC                ---              Not Connected
                         29               DQ-08             95               Data Line
                         30               DQ-09             97               Data Line
                         31               DQ-10             99               Data Line
                         32               DQ-11             101              Data Line



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                                Table 2-4. SRAM (U7) Pin Table
                                 SRAM (U7)        Pin Name        FPGA (U11)             Description
                                  Pin No.                           Pin No.
                                33             VCC               ---              Supply
                                34             GND               ---              GND
                                35             DQ-12             103              Data Line
                                36             DQ-13             105              Data Line
                                37             DQ-14             107              Data Line
                                38             DQ-15             114              Data Line
                                39             LB_n              77               Lower Byte Control
                                40             UB_n              82               Upper Byte Control
                                41             OE_n              118              Output Enable Input
                                42             AD-02             87               Address Line
                                43             AD-01             88               Address Line
                                44             AD-00             93               Address Line

                               It should be noted that the address lines of the SRAM, FLASH and SDRAM
                               Memories are shared. Also the data lines of the SRAM, FLASH, SDRAM
                               Memories and LCD are shared.

                               Flash Memory Device (U8)
                               U8 is a 2Mbyte of Flash memory connected to the Cyclone device. The U8 is
                               a 16,777,216-bit, 3.0-V read-only electrically erasable and programmable
                               flash memory organized as 2,097,152 words X 8 bits or as 1,048,576 words X
                               16 bits. The U8 features commands to Read Program and to Erase operations
                               to allow easy interfacing with microprocessors. The Read Program and Erase
                               operations are automatically executed in the chip. Figure 2-6. shows the Flash
                               memory component on the ESDK 1C6 development board.




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                         Figure 2-6. Flash Memory Device




                         Table 2-5 shows the Flash signal description and its connection with FPGA.

                         Table 2-5. Flash Memory (U8) Pin Table
                            Flash           Pin Name        FPGA (U11)             Description
                           Memory                             Pin No.
                         (U8) Pin No.
                         1                A15             76                Address Line
                         2                A14             75                Address Line
                         3                A13             74                Address Line
                         4                A12             68                Address Line
                         5                A11             67                Address Line
                         6                A10             66                Address Line
                         7                A9              65                Address Line
                         8                A8              64                Address Line
                         9                A19             78                Address Line
                         10               NC              ---               Not Connected
                         11               WE#             79                Write Enable Signal
                         12               RESET           ----              System Reset
                         13               NC              ----              Not Connected
                         14               NC              ----              Not Connected
                         15               RY/BY#          80                Ready/Busy Signal



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                                Table 2-5. Flash Memory (U8) Pin Table
                                   Flash         Pin Name        FPGA (U11)         Description
                                  Memory                           Pin No.
                                (U8) Pin No.
                                16              A18            81             Address Line
                                17              A17            82             Address Line
                                18              A7             63             Address Line
                                19              A6             83             Address Line
                                20              A5             84             Address Line
                                21              A4             85             Address Line
                                22              A3             86             Address Line
                                23              A2             87             Address Line
                                24              A1             88             Address Line
                                25              A0             93             Address Line
                                26              CE#            117            Chip Enable Signal
                                27              VSS            ---            GND
                                28              OE#            118            O/P Enable Signal
                                29              DQ0            94             Data Line
                                30              DQ8            95             Data Line
                                31              DQ1            96             Data Line
                                32              DQ9            97             Data Line
                                33              DQ2            98             Data Line
                                34              DQ10           99             Data Line
                                35              DQ3            100            Data Line
                                36              DQ11           101            Data Line
                                37              VDD            ---            Data Line
                                38              DQ4            102            Data Line
                                39              DQ12           103            Data Line
                                40              DQ5            104            Data Line
                                41              DQ13           105            Data Line



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                         Table 2-5. Flash Memory (U8) Pin Table
                            Flash           Pin Name        FPGA (U11)             Description
                           Memory                             Pin No.
                         (U8) Pin No.
                         42               DQ6             106               Data Line
                         43               DQ14            107               Data Line
                         44               DQ7             113               Data Line
                         45               DQ15/A-1        114               Data Line / Address Line
                         46               VSS             ---               GND
                         47               BYTE            115               Word / Byte
                         48               A16             77                Address Line

                         It should be noted that the address lines of the SRAM, FLASH and SDRAM
                         Memories are shared. Also the data lines of the SRAM, FLASH, SDRAM
                         Memories and LCD are shared.

                         Serial Configuration Memory Device - EPCS1 (U15)
                         U15 is a serial configuration device (EPCS1) for the Cyclone FPGA on
                         ESDK 1C6 board. Serial configuration devices are flash memory devices
                         with a serial interface that can store configuration data for a Cyclone device
                         and reload the data into the device upon power-up or re-configuration. With
                         the new data-decompression feature in the Cyclone FPGA family, designers
                         can use smaller serial configuration device to configure larger Cyclone
                         FPGA. On ESDK 1C6 board AS configuration scheme is combined with
                         JTAG-based configuration, referred as “Active Serial & JTAG Configura-
                         tion”. For, how to configure the EPCS1 device, refer General Connector sec-
                         tion.




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Other Components




                               I2C Memory - EEPROM (U16)
                               U16 is a 16 Kbits I2C EEPROM. The I2C interface lines of this I2C Memory
                               are also shared on the headers to add more I2C devices on the bus. Table 2-6
                               shows the I2C EEPROM Signal Assignments.

                                Table 2-6. I2C EEPROM (U16) Pin Table
                                      I2C Memory (U16)              Pin Name             FPGA (U11) Pin No.
                                           Pin No.
                                ---                          A0                         ---
                                ---                          A1                         ---
                                ---                          A2                         ---
                                ---                          GND                        ---
                                JP18.3                       SDA                        21
                                JP18.2                       SCL                        20
                                ---                          WP                         ---
                                ---                          VCC                        ---

                               Notes for the I2C EEPROM Interface:
                               1.      Address lines A0, A1, A2 are shorted to GND
                               2.      SDA and SCL lines are pulled high through 5.6K resistors
                               3.      Write Protect pin is left floating, not to write protect the memory
                               4.      The Write Protect (WP) pin can be tied HIGH with 5.6K resistor to
                                       write protect the entire memory.

Other                          This section describes the other components on the ESDK 1C6 board.

Components                     I2C RTC (U5)
                               U5 is a Real Time Clock chip on I2C bus. The TIMEKEEPER RAM is a low
                               power Serial TIMEKEEPER with a built-in 32.768 kHz oscillator (external
                               crystal controlled). Eight bytes of the RAM are used for the clock/calendar
                               function and are configured in binary coded decimal (BCD) format.
                               Addresses and data are transferred serially via a two-line bi-directional bus.
                               The built-in address register increments automatically after each WRITE or
                               READ data byte. The clock has a built-in power sense circuit that detects

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                         power failures and automatically switches to the battery supply during power
                         failures. The energy needed to sustain the RAM and clock operations can be
                         supplied from a small lithium coin cell. Typical data retention time is in
                         excess of 5 years with a 50mA/h 3V lithium cell. Table 2-7 shows the RTC
                         Pin Configuration.

                         Table 2-7. I2C RTC (U5) Pin Table
                          I2C RTC (U5)         Pin Name        FPGA (U11)      I2C Bus Header (JP18)
                             Pin No.                             Pin No.              Pin No.
                         1                   OSCI             ---              ---
                         2                   OSCO             ---              ---
                         3                   VBAT             ---              ---
                         4                   GND              ---              ---
                         5                   SDA              121              JP18.4
                         6                   SCL              120              JP18.5
                         7                   FT/OUT           ---              JP13.1
                         8                   VCC              ---              ---

                         Notes for the I2C RTC Interface:
                         1.    On ESDK-1C12 board the RTC is battery backed with 3V lithium cell.
                         2.    32.768 KHz crystal is used for the RTC.
                         3.    FT/OUT pin is taken out on the header at JP13.1 for frequency test.
                         4.    Clock, Data and FT/OUT lines are pulled up through 5.6K resistors.

User Interfaces          This section describes the user interfaces, which consist of LEDs, push-but-
                         tons, DIP switches, LCD, Serial Port, USB Device, PS/2 Port, Parallel Port,
                         VGA Port, I2C Bus Connector.

                         LEDs (D3,D4,D5,D6)
                         D3, D4, D5 and D6 are four individual LEDs connected to the Cyclone device
                         general purpose I/O with current limiting resistors. All of them are active high
                         driven (Common Cathode configuration). All the LEDs will glow when there
                         is logic ‘1’ at the corresponding FPGA pins. Table 2-8 shows the Pin Out
                         table for LEDs. LEDs are displayed by the arrow in Figure 2-7.


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                                Table 2-8. LEDs Pin Out Table
                                      LED               D3              D4               D5             D6
                                FPGA Pin No.      56               55              54              53

                               Figure 2-7. LEDs




                               D8 is Configuration Done LED that indicates successful completion of the
                               downloading process. The CONFIG_DONE pin (U11.145) of the Cyclone
                               device controls this LED.

                               D15 is INVALID connection indicator LED that indicates faulty/no
                               connection of the serial cable at the serial port (SER2). If invalid voltage (non
                               RS232 standard voltage) appears at any receive lines of the MAX 3243 chip
                               (U21) then the INVALID LED will glow. U21.21 pin controls this LED.

                               Push Button Switches (SW4,SW5,SW6,SW7)
                               SW4, SW5, SW6 and SW7 are momentary-contact push-button switches and
                               are used to provide stimulus to designs in the Cyclone device. Each switch is
                               connected to the Cyclone general-purpose I/O pin with pull-up resistor. The
                               Cyclone device pin will see logic ‘0’ when each switch is pressed. Figure 2-
                               8. displays the push button switches.




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                         Figure 2-8. Push Button Switches




                         Table 2-9 shows the push button switches Pin Out table.

                         Table 2-9. Push Button Switches Pin Out Table
                              Button              SW4             SW5          SW6             SW7
                         FPGA Pin No.        48              49           57              62

                         SW8 is a global reset switch connected to the RESET IC. The RESET IC pin
                         RESETIN# will see logic ‘0’ when SW8 is pressed. The output of this RESET
                         IC (RESET# Active LOW) is connected to the FPGA pin U11.23. Hence the
                         Cyclone device pin will see logic ‘0’ when SW8 is pressed.

                         DIP Switches (SW3)
                         SW3 is a block of four switches. Each switch is connected to the Cyclone
                         general-purpose I/O pin with pull-up resistor. The Cyclone device pin will see
                         logic ‘0’ when switch is in ON condition. Figure 2-9. shows 4 DIP Switches.




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                               Figure 2-9. DIP Switches




                               Table 2-10 shows the Pin Out table for DIP Switches.

                                Table 2-10.DIP Switches Pin Out Table
                                       Switch           SW 3.1           SW 3.2       SW 3.3          SW 3.4
                                    FPGA Pin No.       58           59              60               61


                               Liquid Crystal Display (U1)
                               U1 is a 16X2 character Liquid Crystal Display. Here 16X2 represents 2 dis-
                               play lines with 16 characters per line. The display contains 2 internal byte
                               wide registers, one for the command and second for characters to be dis-
                               played. It also contains user programmed RAM area that can be programmed
                               to generate any desired character that can be formed using a dot matrix. Table
                               2-11 gives full description about the signals and pin connection of the LCD.

                                Table 2-11. Liquid Crystal Display (U1) Pin Table
                                    LCD (U1)          Pin Name           FPGA (U11)          Description
                                     Pin No.                               Pin No.
                                1               VSS                      ---             GND
                                2               VDO                      ---             +5 V
                                3               VO                       ---             Contrast Setting
                                4               RS(Register Select)      108             All these



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                         Table 2-11. Liquid Crystal Display (U1) Pin Table
                             LCD (U1)             Pin Name         FPGA (U11)          Description
                              Pin No.                                Pin No.
                         5                 R/W (Read/ Write)       73            All of these signals
                                                                                 are level shifted and
                         6                 E(Enable Signal)        50
                                                                                 then connected to the
                         7                 DB0                     94            FPGA pins.
                         8                 DB1                     96
                         9                 DB2                     98
                         10                DB3                     100
                         11                DB4                     102
                         12                DB5                     104
                         13                DB6                     106
                         14                DB7                     113
                         15                LED+                    ---           +5V
                         16                LED-                    ---           GND

                         It should be noted that the address lines of the SRAM, FLASH and SDRAM
                         Memories are shared. Also the data lines of the SRAM, FLASH, SDRAM
                         Memories and LCD are shared. Figure displays LCD and Table 2-12 shows
                         the LCD instruction table.

                         Figure 2-10. LCD




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Table 2-12.LCD Instruction Table
 Instructio                               CODE      Execut                                           Description
     n                                              e Time
                  RS   R/   D7 D6 D5 D4 D3 D2 D1 D0 (max)
                       W
Clear             0    0    0   0     0     0      0      0      0         1         1.64mS Clears all display and
Display                                                                                     returns the cursor to the
                                                                                            home position (Address 0).
Cursor at         0    0    0   0     0     0      0      0      1         -         1.64mS Returns the cursor to the
Home                                                                                        home position (Address 0).
                                                                                            Also returns the display
                                                                                            being shifted to the original
                                                                                            position. DDRAM contents
                                                                                            remain unchanged.
Entry Mode 0           0    0   0     0     0      0      1      I/D       S         40uS     Sets the cursor move
Set                                                                  (1)       (3)            direction and specifies or
                                                                     (2)                      not to shift the display.
                                                                                              These operations are per-
                                                                                              formed during data write
                                                                                              and read.
Display On/ 0          0    0   0     0     0      1      D      C         B         40uS     Sets On/Off of all dis-
Off Control                                                                                   play(D)), cursor On/Off(C),
                                                                                              and blink of cursor position
                                                                                              character(B).
Cursor/           0    0    0   0     0     1      S/C R/L -               -         40uS     Moves the cursor and
Display                                            (4)    (6)                                 shifts the display without
Shift                                              (5)    (7)                                 changing DDRAM con-
                                                                                              tents.
function set 0         0    0   0     1     DL     N      F      -         -         40uS     Sets interface data
                                             (8)   (10)   (12)                                length(DL), number of dis-
                                             (9)   (11)   (13)                                play lines(L) and character
                                                                                              font(F).
CGRAM       0          0    0   0     ACG                                            40uS     Sets the CGRAM address.
address set                                                                                   CGRAM data is sent and
                                                                                              received after this setting.
DDRAM       0          0    1   ADD                                                  40uS     Sets the DDRAM address.
address set                                                                                   DDRAM data is sent and
                                                                                              received after this setting.




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Table 2-12.LCD Instruction Table
 Instructio                                    CODE     Execut                                          Description
     n                                                  e Time
                  RS     R/     D7 D6 D5 D4 D3 D2 D1 D0 (max)
                         W
Busy Flag/        0      1     BF      AC                                           40uS        Reads Busy flag(FB) indi-
Address                         (14)                                                            cating internal operation is
Read                            (15)                                                            being performed and reads
                                                                                                address counter contents.
CGRAM/            1      0     Write Data                                           40uS        Writes data into DDRAM or
DDRAM                                                                                           CGRAM
Data Write
CGRAM /           1      1     Read Data                                            40uS        Reads data from DDRAM
DDRAM                                                                                           or CGRAM
Data Read

                                             Note: to Table 2-12
     (1)    I/D = 1 — Increment
     (2)    I/D = 0 — Decrement
     (3)    S = 1— With Display Shift
     (4)    S/C = 1— Display Shift
     (5)    S/C = 0 — Cursor Movement
     (6)    R/L = 1 — Shift to the Right
     (7)    R/L = 0 — Shift to the Left
     (8)    D/L = 1 — 8 bit
     (9)    D/L = 0 — 4 bit
     (10)   N = 1 — 1/16 Duty
     (11)   N = 0 — 1/8 Duty, 1/11 Duty
     (12)   F = 1 — 5 X 10 dots
     (13)   F = 0 — 5 X 7 dots
     (14)   BF = 1 — Internal Operation is being performed
     (15)   BF = 0 — New Instruction acceptable
     (16)   The above execution time is for fosc = 250 KHz. However, when frequency changes, execution time also changes. when
            fosc=270 KHz, then new execution time will be 40 us X (250/270) = 37 us

                                       LCD Initialization
                                       Normally LCD itself executes internal reset operations at power up. But if the
                                       power supply condition is not satisfied, the internal reset circuit would not
                                       operate properly. It is better to provide initialization sequence by instruction.

                                       Initializing by instruction . The initialization command sequence for the
                                       LCD is as follows:

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                               1.   POWER ON - 15msec Delay
                               2.   Function Set - 4.1msec Delay
                               3.   Function Set - 100microsec
                               4.   Function Set - 5msec Delay
                               5.   Function Set
                               6.   Display OFF
                               7.   Display ON
                               8.   Entry Mode Set.

                               LCD on ESDK 1C6 board is of N = 1 (1/16 Duty) and F = 0 (5X7 dots). After
                               this sequence, LCD is ready for operation.

                               Refer Using LCD on ESDK 1C6 Tutorial for more information.

                               Serial Port Connector (SER2)
                               SER2 is the standard DB-9 Serial connector. It has all 9-pin connections to
                               the FPGA, a FULL Modem interface. This connector is typically used for
                               communication with a host computer using a standard serial cable connected
                               to (for example) a COM port. U21 is a level translator for interfacing the
                               SER2, Full Modem serial port, with the FPGA. Figure 2-11. shows Serial Port
                               connector.

                               Figure 2-11. Serial Port Connector




                               Table 2-13 shows the pin description of the Serial Port connector.



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Table 2-13.Serial Port Connector (SER2) Pin Table
  MAX 3243 (U21)         MAX 3243 (U21)        FPGA        Serial Port(SER2)            Description
     Pin No.               Pin Name          (U11) Pin          Pin No.
                                                No.
1                        C2+                ---           ---                   ---
2                        C2-                ---           ---                   ---
3                        V                  ---           ---                   ---
4                        RSIN1              ---           1                     DCD-232 LEVEL
5                        RSIN2              ---           6                     DSR-232 LEVEL
6                        RSIN2              ---           2                     RX-232 LEVEL
7                        RSIN4              ---           8                     CTS-232 LEVEL
8                        RSIN5              ---           9                     RI-232 LEVEL
9                        RSOUT1             ---           3                     TX-232 LEVEL
10                       RSOUT2             ---           4                     DTR-232 LEVEL
11                       RSOUT3             ---           7                     RTS-232 LEVEL
12                       TTLIN3             45            ---                   RTS-TTL LEVEL
13                       TTLIN2             46            ---                   DTR-TTL LEVEL
14                       TLIN1              47            ---                   TX-TTL LEVEL
15                       TTLOUT5            44            ---                   RI-TTL LEVEL
16                       TLOUT4             43            ---                   CTS-TTL LEVEL
17                       TTLOUT3            42            ---                   RX-TTL LEVEL
18                       TTLOUT2            41            ---                   DSR-TTL LEVEL
19                       TTLOUT1            39            ---                   DCD-TTL LEVEL
20                       R2OUTB             ---           ---                   ---
21                       INVALID            ---           ---                   ---
22                       FORCEOFF           ---           ---                   ---
23                       FORCEON            ---           ---                   ---
24                       C1-                ---           ---                   ---
25                       GND                ---           5                     GND-232 LEVEL



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Table 2-13.Serial Port Connector (SER2) Pin Table
  MAX 3243 (U21)       MAX 3243 (U21)         FPGA        Serial Port(SER2)           Description
     Pin No.             Pin Name           (U11) Pin          Pin No.
                                               No.
26                    VCC                  ---           ---                  ---
27                    V+                   ---           ---                  ---
28                    C1+                  ---           ---                  ---


                               USB Connector (J12)
                               USB is a cable bus that supports data exchange between a host computer and
                               a wide range of simultaneously accessible peripherals. The attached periph-
                               erals share USB bandwidth through a host- detached while the host and other
                               peripherals are in operation.

                               The USB transfers signal and power over a four-wire cable as shown in the
                               figure below. The signaling occurs over two wires on each point-to-point
                               segment.

                               B Type Connector. The figure besides shows B-Type connector
                               (J12) on the ESDK 1C6 board. This connector requires a
                               transceiver (PHY-chip) in order to communicate with FPGA.
                               Table 2-14 shows pin connections of the B- type connector and
                               Table 2-15 describes the USB configuration jumpers.

                               PHY-Chip. U22 is the PHY Chip (1T11A), which acts as the interface
                               between FPGA pins and the two differential lines of the USB Interface. It
                               converts the differential line interface of the USB to the three transmit and
                               three receive signals as shown in the Figure 2-12. shows the PHY Chip Inter-
                               face Diagram.




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Figure 2-12.USB PHY Chip Interface Diagram




                           Table 2-14 gives the details of B Type Connector to PHY Chip to FPGA.

                            Table 2-14.USB Connector (J12) Pin Table
                              PHY Chip          PHY Chip      FPGA (U11) USB Connector             Pin
                            (U22) Pin No.       Pin Name        Pin No.   (J12) Pin no.           Name
                            1                  Mode           ---            ---                ---
                            2                  OE             16             ---                ---
                            3                  RCV            17             ---                ---
                            4                  VP             18             ---                ---
                            5                  VM             19             ---                ---
                            6                  SUSPEND        ---            ---                ---
                            7                  GND            ---            J12.4              GND
                            8                  NC             ---            J12.1              NC
                            9                  SPEED          ---            ---                ---
                            10                 D-             ---            J12.2              D-
                            11                 D+             ---            J12.3              D+
                            12                 VPO            15             ---                ---
                            13                 VMO/FSEO       14             ---                ---
                            14                 VCC            ---            ---                ---




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User Interfaces




                               Table 2-15 below shows the jumper settings of USB.

                                Table 2-15.USB Configuration Jumpers
                                          Jumper                              Speed Select
                                                                 Low Speed                   Full Speed
                                J8 (MODE select)          Short J8.2 and J8.3       Short J8.2 and J8.3
                                J9 (D+)                   Open                      Short J9.1and J9.2
                                J10 (D-)                  Short J10.1and J10.2      Open
                                J11(SPEED select)         Short J11.2 and J11.3     Short J11.1and J11.2


                               PS/2 Connector (JP1)
                               JP1 is a PS/2 Connector. The PS/2 interface allows the connectivity to a PS/
                               2 device. The connector is a female 6-pin mini din type. The Figure 2-13.
                               shows the PS/2 Connector.

                               Figure 2-13. PS/2 Connector




                               Table 2-16 displays the signal description of PS/2 port.

                                Table 2-16.PS/2 Connector (JP1) Pin Table
                                    PS/2 Connector        Pin Name           FPGA (U11)        Description
                                     (JP1) Pin No.                             Pin No.
                                1                       DATA            13                   PS/2 Device
                                                                                             Data
                                2&6                     NC              ---                  ---
                                3                       GND             ---                  ---




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                         Table 2-16.PS/2 Connector (JP1) Pin Table
                              PS/2 Connector         Pin Name        FPGA (U11)          Description
                               (JP1) Pin No.                           Pin No.
                         4                          +5 V           ---                 PS/2 Device
                                                                                       Supply
                         5                          CLK            12                  PS/2 Device
                                                                                       Clock

                         Parallel Port (CON1)
                         CON1 is a standard DB25 Female parallel port connector. Figure 2-14. shows
                         the parallel port connector.

                         Figure 2-14. Parallel Port Connector




                         Table 2-17 shows the Parallel port signal description.

                          Table 2-17.Parallel Port (CON1) Pin Table
                             Parallel Port (CON1)           Pin Name               FPGA (U11) Pin No.
                                    Pin No.
                          1                          C0                        8
                          2                          D0                        6
                          3                          D1                        1
                          4                          D2                        5
                          5                          D3                        3
                          6                          D4                        240
                          7                          D5                        238
                          8                          D6                        237


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User Interfaces




                                Table 2-17.Parallel Port (CON1) Pin Table
                                 Parallel Port (CON1)            Pin Name               FPGA (U11) Pin No.
                                        Pin No.
                                9                         D7                        239
                                10                        S6                        236
                                11                        S7                        235
                                12                        S5                        234
                                13                        S4                        233
                                14                        C1                        7
                                15                        S3                        2
                                16                        +5 V                      ---
                                17                        C3                        4
                                18                        GND                       ---
                                19                        GND                       ---
                                20                        GND                       ---
                                21                        GND                       ---
                                22                        GND                       ---
                                23                        GND                       ---
                                24                        GND                       ---
                                25                        GND                       ---

                               VGA Port (VGA CON)
                               ESDK 1C6 board has a standard VGA connector. It contains 5 active signals.
                               Two signals - compatible with TTL logic levels - horizontal sync and vertical
                               sync, are used for synchronization of the video. Three analog signals with 0.7
                               to 1.0 volt peak-to-peak level are used to control the color.

                               The color signals are Red, Green, and Blue. They are often collectively
                               referred to as the RGB signals. By changing the analog level of the three RGB
                               signals, all other colors are produced. Figure 2-15. shows the VGA port.




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                                                                                      Board Components




                         Figure 2-15. VGA Port




                         The Table 2-18 below shows the Pin Configuration of VGA port.

                         Table 2-18.VGA Port (VGA CON) Pin Table
                          VGA Port (VGA CON)               VGA Interface        FPGA (U11) Pin No.
                               Pin No.
                         1                           Red                       228
                         2                           Green                     122
                         3                           Blue                      170
                         4                           NC                        ---
                         5                           NC                        ---
                         6                           GND                       ---
                         7                           GND                       ---
                         8                           GND                       ---
                         9                           NC                        ---
                         10                          GND                       ---
                         11                          GND                       ---
                         12                          NC                        ---
                         13                          H_sync                    227
                         14                          V_sync                    226
                         15                          NC                        ---




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Expansion Connectors




                               I2C Bus Header(JP18)
                               I2C is a two-wire, bi-directional serial bus that provides a simple and efficient
                               method of data exchange between devices. It is most suitable for short dis-
                               tance communication between many devices. I2C standard is a true multi-
                               master bus, which includes collision detection, and arbitration that prevents
                               data corruption if two or more masters attempt to control the bus simultane-
                               ously.

                               It is the most widely used bus, which allows the connection of many types of
                               ICs that are used in a number of different applications. It provides an interface
                               between microprocessor and peripheral devices without wiring full address,
                               data and control.

                               Two I2C buses have been provided on the ESDK 1C6 board in which one I2C
                               hooks up with memory (I2C EEPROM) and other to I2C RTC. Both are 5V
                               operative.

                               Signals for both the I2C buses are taken out as headers. These headers can be
                               used to connect additional I2C slaves or can be used for debugging purpose
                               for existing I2C slaves (RTC and EEPROM) Table 2-19 Pin description of
                               I2C Bus connector.

                                Table 2-19.I2C Bus Header (JP18) Pin Table
                                      I2C Bus                          Signal Description
                                    Header(JP18)
                                      Pin No.
                                1                    VCC +5 Volts
                                2                    SCL - I2C Bus on which I2C EEPROM is connected
                                3                    SDA - I2C Bus on which I2C EEPROM is connected
                                4                    SDA - I2C Bus on which I2C RTC is connected
                                5                    SCL - I2C Bus on which I2C RTC is connected
                                6                    GND


Expansion                      This section describes the expansion connectors on the ESDK 1C6 develop-
                               ment board.
Connectors

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                         Expansion Prototype Connector (J1, J2, J3, J4)
                         Headers J1, J2, J3 and J4 collectively form the standard-footprint called santa
                         cruz long expansion headers. These are mechanically stable connections that
                         can be used as an interface to a special function daughter card.

                         The expansion prototype connector interface includes
                             74 pins for prototyping (All 74 I/O pins connect to user I/O pins on the
                             Cyclone device)
                             PCI Clock available on the J4 connector from master clock chip
                             User clock available on the J4 connector from FPGA
                             An Active LOW Power On Reset signal
                             Five regulated 3.3V power-supply pins (1A total max load)
                             One regulated 5V power-supply pin. (1A total max load)
                             Numerous ground connections

                         The output logic level on the expansion prototype connector pins is 5 Volts.

                         There are two types of Santa Cruz headers: Short-expansion header and long-
                         expansion header. In short-expansion header, there are J2, J3 & J4 connectors,
                         which are 14 pins, 40pins and 20pins respectively. Where as, long-expansion
                         header includes additional connector J1 having 40pins along with the short-
                         expansion header connectors.

                         The ESDK 1C6 Kit expansion prototype connector provides 62 I/O pins (5
                         Volts tolerant) for expansion purposes. Here all 62 I/O lines are level shifted
                         using bus switches. Figure 2-16. shows the Santa Cruz connector.

                         Figure 2-16. Santa Cruz Connector




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Expansion Connectors




                               Figure 2-17. shows the pin description of the connectors J1, J2, J3 & J4.

Figure 2-17.Expansion Prototype Connector-J1,J2,J3,J4




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                                                                                 Board Components




                          Note: to connector J4:
                                (1) Connector pin J4.9 has a PCI clock coming from the board
                                clock chip
                                (2) Connector pin J4.11 has a clock coming from the FPGA Pin
                                (3) Connector pin J4.13 has a clock coming out of the Prototype
                                card to the FPGA




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Expansion Connectors




                               IDE Connector (J3)
                               J3 on Santa-Cruz connector can be used as IDE interface connector. Hard
                               Drive and CD ROM Drive usually connect to the computer through an Inte-
                               grated Drive Electronics (IDE) interface. Essentially, an IDE interface is a
                               standard way for a storage device to connect to a computer.Table 2-20 gives
                               the pin connections of IDE.

                                Table 2-20.IDE Connector (J3) Pin Table
                                    IDE Connector (J3)           Pin Name                  FPGA (U11)
                                         Pin No.                                             Pin No.

                                1                         RESET#                   ---
                                2                         GND                      ---
                                3                         D7                       217
                                4                         D8                       220
                                5                         D6                       216
                                6                         D9                       219
                                7                         D5                       215
                                8                         D10                      218
                                9                         D4                       206
                                10                        D11                      221
                                11                        D3                       207
                                12                        D12                      222
                                13                        D2                       208
                                14                        D13                      223
                                15                        D1                       213
                                16                        D14                      224
                                17                        D0                       214
                                18                        D15                      225
                                19                        GND                      ---
                                20                        NC                       ---
                                21                        DMARQ                    199


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                         Table 2-20.IDE Connector (J3) Pin Table
                          IDE Connector (J3)                Pin Name                 FPGA (U11)
                               Pin No.                                                 Pin No.

                         22                          GND                       ---
                         23                          WE#                       200
                         24                          GND                       ---
                         25                          OE#                       201
                         26                          GND                       ---
                         27                          IORDY                     202
                         28                          CSEL                      196
                         29                          DMACK                     205
                         30                          GND                       ---
                         31                          INTRQ                     204
                         32                          IOCS16                    197
                         33                          A1                        203
                         34                          PDIAG                     179
                         35                          A0                        176
                         36                          A2                        178
                         37                          CS0#                      174
                         38                          CSI                       124
                         39                          DASP#                     173
                         40                          GND                       ---




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General Connector




General                        This section describes general connectors on the ESDK 1C6 development
                               board.
Connector
                               Active Serial & JTAG Header (JP11, JP12)
                               On ESDK 1C6 board AS configuration scheme is combined with JTAG-
                               based configuration. The MSE (Mode Select Enable) pins are tied low to
                               select the Active Serial Configuration mode. This setup uses two 10-pin
                               download cable headers on the board. The first header (JP11) programs the
                               serial configuration device in-system via the AS programming interface, and
                               the second header (JP12) configures the Cyclone FPGA directly via the
                               JTAG interface.
                               Figure 2-18. shows the Active Serial and JTAG header on the board.

                               Figure 2-18. Active Serial & JTAG Header




                               If you try configuring the device using both schemes simultaneously, JTAG
                               configuration takes precedence and AS configuration will be terminated.

                               Table 2-21 and Table 2-22 shows the Pin Outs of Header JP12 & Header JP11.

                                Table 2-21.JTAG Header (JP12) Pin Table
                                 JTAG Header (JP12)              Pin Name           FPGA (U11) Pin No
                                      Pin No.
                                1                         TCK                     147
                                2                         GND                     ---
                                3                         TDO                     149


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                         Table 2-21.JTAG Header (JP12) Pin Table
                          JTAG Header (JP12)                 Pin Name             FPGA (U11) Pin No
                               Pin No.
                         4                           +3.3V                      ---
                         5                           TMS                        148
                         6                           +3.3V                      ---
                         7                           NC                         ---
                         8                           NC                         ---
                         9                           TDI                        155
                         10                          GND                        ---

                         Table 2-22.Active Serial Header (JP11) Pin Table
                             Active Serial Header         Pin Name           EPCS1         FPGA (U11)
                                (JP11) Pin No.                              (U15) Pin        Pin No.
                                                                               No.
                         1                            DCLK              6                36
                         2                            GND               ---              ---
                         3                            CONF_DONE         ---              145
                         4                            +3.3V             ---              ---
                         5                            CONFIG#           ---              25
                         6                            CE#               ---              32
                         7                            DATA              2                25
                         8                            CSO#              1                24
                         9                            ASDO              5                37
                         10                           GND               ---              ---


Status LEDs &            This section describes the status LEDs and reset switches on the ESDK 1C6
                         development board. Some of the switches are user-defined.
Reset/Power
Switches


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Status LEDs & Reset/Power Switches




                                Power (D12, D11) & Status (D8, D15) LEDs
                                Power LEDs (D12, D11)
                                The Power LEDs (D11, D12) turn on indicating that voltage is supplied to the
                                DC Jack (SW1) and is being distributed to the ESDK 1C6 Board’s on-board
                                Power Regulators.

                                +5V Power LED (D12). When the Power LED D12 is turned on, it indicates
                                that a regulated +5V supply is available on the ESDK 1C6 Board.

                                +3.3V Power LED (D11). When the Power LED D11 is turned on, it indi-
                                cates that a regulated +3.3V supply is available on the ESDK 1C6 Board.

                                Status LEDs (D8, D15)
                                The ESDK 1C6 Board contains two Status LEDs (D8, D15), which are
                                described in the following sections:

                                C_DONE Status LED (D8). The ESDK 1C6 board has one CONF DONE
                                Status LED (D8) that turns on to indicate successful configuration of the
                                EP1C6 FPGA. This LED is driven by the EP1C6 (U11), pin x=145
                                (CONF_DONE). See Table 2-22

                                INVALID Status LED (D15). The ESDK 1C6 board has one INVALID
                                Status LED (D15) that turns on to indicate invalid RS232 voltage level
                                detection at the Receiver inputs of the RS232 Transceiver chip. This LED
                                indicates if a valid RS232 input is present at the Receiver inputs of the RS232
                                Transceiver chip. Usually if no valid RS232 connectivity is present, this LED
                                glows (INVALIDn is asserted). This LED is driven by the RS232 Transceiver
                                chip.

                                Power Switch (SW2)
                                SW2 is a power switch that connects the 6-9V DC input from the DC power
                                jack, SW1, to the on-board power regulators. When SW2 is in the ON posi-
                                tion, Power LEDs (D11, D12) turn on.




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                         User Defined Reset Push-Button Switch (SW8)
                         User Defined Reset Push-Button (SW8) is a USER RESET momentary-con-
                         tact push button. It is used as defined by the user, and could be used for ini-
                         tialization and reset of a user design running on the ESDK 1C6 board. This
                         button must first be defined by the user before it can be used.

                         Reset Circuitry (U19)
                         U19 is an integrated-circuit supply-voltage supervisor. The supply-voltage
                         supervisor monitors the supply for under voltage conditions at the SENSE
                         input. During power up, the RESET output becomes active (low) when VCC
                         attains a value approaching 1 V. As VCC approaches 3 V (assuming that
                         SENSE is above VT+), the delay-timer function activates a time delay, after
                         which outputs RESET and RESET# goes inactive. When an under voltage
                         condition occurs during normal operation, outputs RESET and RESET# goes
                         active. To ensure that a complete reset occurs, the reset outputs remain active
                         for a fixed time delay even after the voltage at the SENSE input exceeds the
                         positive-going threshold value. Table 2-23 shows the Reset Signal Assign-
                         ment.

                          Table 2-23.Reset Circuitry (U19) Pin Table
                                Reset IC(U19)                Signal                 FPGA (U11)
                                  Pin No.                                             Pin No.
                          5                          RESET#                    23


Clock Circuitry          This section describes the components used to set the ESDK 1C6
                         development board clocking options.

                         This development board supports various clock frequencies to support a
                         number of IP blocks requiring different frequencies. U18 is a Master clock
                         chip (PI6C103) on the ESDK 1C6 board, which provides multiple clocks on
                         the board. The clock chip uses 14.318 MHz crystal (Y1) for its inbuilt
                         oscillator.

                         JP3 is a 10-pin header for configuring the input clock to the Cyclone device
                         at CLK1 or CLK3 pins. J7 is a 3-pin header for configuring the CPU clock
                         outputs of the clock chip.


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Clock Circuitry




                                         Various clocks available on the ESDK 1C6 board are:
                                         1.   PCI clock (33.33 MHz)
                                         2.   USB clock (48 MHz)
                                         3.   REFERENCE clock (14.318 MHz)
                                         4.   CPU clock (100 MHz / 66.66 MHz)

                                         Figure 2-19. below shows the clock distribution on the ESDK 1C6 board.

Figure 2-19.ESDK 1C6 Board Clocking Options

                      Clock Chip                        Altera Cyclone FPGA


                             PCI Clock                 CLK0

                                                                                            User Clock Header JP2

                             USB Clock
                                                       CLK1        PLL1_OUTp                User CLK1
                            REF0 Clock



                                              JP3




                                                       CLK3
                             PCI Clock
                                                                                              Santa Cruz Header



                                                                               Translator
                             CPU Clock                 CLK2        PLL2_OUTp     Level      User CLK2


                      CPU_STOP_Clock#                  IO            DPCLK5                 CLK Out



                             PCI Clock                                                      PCI Clock


                      PCI_STOP_Clock#                        J5


                  CPU_CLK_SEL_100/66#                        J7



                            CPU Clock2                      JP4


                            REF1 Clock                      JP19




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                         Setting the Clocks
                         The Clock configuration on the ESDK 1C6 board is controlled by the follow-
                         ing options described in Table 2-24

                         Table 2-24.Clock Setting Options
                          Sr. No.     Jumper/                         Description
                                      Header/
                                        Pin
                         1           JP3          JP3 header is used for configuring the input clock to
                                                  the Cyclone device at CLK1 and CLK3 pins
                         2           J7          J7 header is used for configuring the CPU clock
                                                 outputs of the clock chip as 100 MHz or 66.66 MHz
                         3           J5          J5 Header is used to stop the PCI Clock available on
                                                 the ESDK 1C6 board
                         4           U11.123     FPGA Pin 123 is used to stop the CPU Clock
                                                 available on the ESDK 1C6 board

                         The above mentioned Headers are described in detail below:

                         Clock Select Jumper (JP3)
                         JP3 is a 10-pin header for configuring the input clock to the Cyclone device
                         at CLK1 and CLK3 (PLL Clock input) pins. Table 2-25 below describes the
                         configuration options for CLK1.

                          Table 2-25.Jumper Setting for Clock Input to the FPGA at CLK1
                                    CLK1                Jumper Setting          FPGA (U11) Pin No.
                          USB_CLK (U18.13) 48       Short JP3.4-JP3.3         29
                          MHz
                          REF0_CLK (U18.27)         Short JP3.4-JP3.6         29
                          14.318 MHz




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Clock Circuitry




                               Table 2-26 describes the configuration options for CLK3 inputs.

                                Table 2-26.Jumper Setting for Clock Input to the FPGA at CLK3
                                         CLK3                 Jumper Setting         FPGA (U11) Pin No.
                                PCI_CLK_E (U18.4)         Short JP3.8 & JP3.7       152
                                33.33 MHz
                                REF0_CLK (U18.27)         Short JP3.8 & JP3.6       152
                                14.318 MHz

                               The CLK0 pin of FPGA (U11.28) is directly fed PCI Clock from the Clock
                               Chip. Similarly CLK2 pin of FPGA (U11.153) is directly fed CPU Clock
                               from the Clock chip.

                               CPU Clock Select Jumper (J7)
                               J7 is a 3-pin header for configuring the CPU clock outputs of the clock chip
                               as 100 MHz or 66.66 MHz. The selected CPU clock is available as CLK2
                               input of PLL2 (of Altera Cyclone FPGA) and CPU Clock Header (JP4).Table
                               2-27 below describes the configuration options for the CPU Clock. Refer to
                               Table 2-31 for the details of CPU Clock Header (JP4).

                                Table 2-27.CPU Clock Select Jumper (J7) Settings
                                           CPU Clock                    Jumper Setting           FPGA (U11)
                                                                                                   Pin No.
                                66 MHz                              Short J 7.1 & J 7.2          153
                                100 MHz                             Short J 7.2 & J 7.3          153

                               The FPGA Pin U11.123 is used to Enable/Disable the CPU Clock. When this
                               pin is driven HIGH or tri-stated (used as inputs), the CPU clock is enabled.
                               Driving this pin LOW disables the CPU Clock. It is recommended to disable
                               the CPU clock, if it is not used by the design, using CPU_STOP (U11.123)
                               signal.




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                         PCI Clock Enable Jumper (J5)
                         J5 Header is used to stop the PCI Clock available on the ESDK 1C6 board.

                          Table 2-28.PCI Clock Enable Jumper (J5) Settings
                                    Jumper Setting                            Function
                          Short J 5.2 & J 5.1                    Disable PCI Clock
                          Short J 5.2 & J 5.3                    Enable PCI Clock

                         When the PCI Clock is disabled, all PCI Clocks, except the PCI Clock on the
                         JP3 Headers, are stopped. The PCI clock on the JP3 Header is a free running
                         clock and is not affected by the PCI Clock Enable configuration. Rest of the
                         PCI Clock targets are affected by this jumper setting. It is recommended to
                         disable the PCI clocks, if they are not used in the design, using PCI Clock
                         Enable Jumper. PCI Clock Jumper settings are shown in Table 2-28 .

                         Clock Headers
                         The ESDK 1C6 board contains the following clock headers: Table 2-29 lists
                         the same

                         Table 2-29.Clock Headers
                          Sr. No.     Jumper/                         Description
                                      Header
                         1           JP2          User Clock Header
                         2           JP4          CPU Clock Header
                         3           JP19         Reference Clock Header

                         The above mentioned Headers are mentioned in detail below:

                         USER Clock Header (JP2)
                         JP2 is a USER Clock header, which bears the PLL1_OUTp output and can be
                         used as User Clock output or User Clock Input. Any clock can be driven out
                         to this header or can be driven in from this header as per the user design
                         requirements. The Pin description for this header is described in Table 2-30 .




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Clock Circuitry




                                Table 2-30.User Clock Header (JP2)
                                     User Clock                  Pin Name                FPGA (U11) Pin No.
                                 Header(JP2) Pin No.
                                JP 2.1                    GND                        -
                                JP 2.2                    USER CLK (as per           38
                                                          User configuration)

                               CPU Clock Header (JP4)
                               JP4 contains a copy of CPU Clock available on the header directly from the
                               clock chip. JP4 gives clock output on headers only. These pins are not con-
                               nected to any FPGA pins. The clock frequency available on this header
                               depends upon the CPU CLOCK SELECT jumper (J7) setting. The Pin
                               description for this header is described in Table 2-31 .

                                Table 2-31.CPU Clock Header (JP4)
                                 CPU Clock Header (JP4) Pin No.                           Signal
                                JP 4.1                                 CPU_CLK_2 (U18.23) (as per CPU
                                                                       Clock Select Jumper Setting)
                                JP 4.2                                 GND


                               Reference Clock Header (JP19)
                               JP19 contains a copy of Reference Clock available on the header directly
                               from the clock chip. JP19 gives clock output on headers only. These pins are
                               not connected to any FPGA pins. This header contains a free running refer-
                               ence clock of frequency 14.318 MHz. Table 2-32 lists the Pin description for
                               this header:

                                Table 2-32.Reference Clock Header (JP19)
                                  Reference Clock Header(JP19)                            Signal
                                JP 19.1                                REF1_CLK (U18.26) (14.318 MHz)
                                JP 19.2                                GND




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                         Santa Cruz Header Clocks
                         The clocking options available on the Santa Cruz Headers on the ESDK 1C6
                         board are explained in the Table 2-33 below:

                         Table 2-33.Santa Cruz Header Clocking Options
                                   Header                    Signal                FPGA (U11) Pin No.
                         J 4.9                       PCI CLK (33.33 MHz)       -
                         J 4.11                      USER CLK2 (as per         144
                                                     User configuration)
                         J 4.13                      CLK OUT (as per User      131
                                                     configuration)

                         For more details of the Santa Cruz headers, refer to section “Expansion
                         Connectors” on page 37

Power Supply             This section describes the power supply, power regulators and the power
                         plane connectors.
Circuitry
                         DC Power Input Jack (SW1)
                         The DC input power to the ESDK 1C6 board is provided by a right-angle 2.5
                         mm power jack SW1.The board accepts 6-9 Volt unregulated/regulated DC
                         supply from external source (with center-terminal positive supply). This input
                         power is regulated down to 5VDC, 3.3VDC and 1.5VDC by three voltage
                         regulators.

                         ESDK 1C6 Board Power Supply
                         The ESDK 1C6 board is powered with number of different regulated supply
                         voltages as mentioned below:
                         1.    +1.5 Volts for Cyclone device core supply
                         2.    +3.3 Volts for Cyclone device I/O ring supply
                         3.    +5 Volts for 5-volts operative devices on the board




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July 2009                     Embedded Systems Development Kit Reference Manual (Cyclone Edition, EP1C6)
Power Supply Circuitry




                               Power Supply Configuration Jumper (JP5)
                               The board is provided with jumper setting for input supply to the board.
                               Jumper pins JP5.2 and JP5.3 are shorted when input supply from external
                               source (through DC power jack SW1) is 6-9 volt regulated/unregulated,
                               which is the default setting on the board.

                               Jumper pins JP5.1 and JP5.2 are shorted when input supply from external
                               source (through DC power jack SW1) is +5 volt regulated. This setting is
                               useful when the 5 Volt regulator chip is not stuffed on the board. Be careful
                               while using this option, since in this mode, all the +5 V operative devices are
                               directly fed this supply (since +5V Regulator is bypassed in this mode).
                               Hence if the supply is not proper (+5 V regulated) then this may damage the
                               +5 V operative devices on the board when this option is used.

                               Table 2-34 below shows the Power supply select setting:

                                Table 2-34.Power Supply Select Setting
                                          Jumper Setting                             Function
                                Short JP 5.2 & JP 5.1                  Use regulated +5V DC Power from
                                                                       DC Power Jack SW1
                                Short JP 5.2 & JP 5.3 (Default)        Use unregulated/regulated 6-9V
                                                                       Power from DC Power Jack SW1

                               The default configuration on the ESDK 1C6 Board uses regulated/
                               unregulated
                               6-9VDC from the DC Power jack SW1. Only two pins of JP5 header are
                               stuffed to enable the default configuration for the Power supply on the ESDK
                               1C6 board. To take advantage of the available non-default configuration, user
                               has to stuff the non-populated headers on the ESDK 1C6 board, which are
                               seldom required.




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                                                                                        Board Components




                             On-Board Power Regulators (U12, U13, U14)
                             There are three linear voltage regulators on the ESDK 1C6 board to control
                             the different voltage rails available on the ESDK 1C6 board. Three linear
                             voltage regulators provide +5V, +3.3v and +1.5V on the ESDK 1C6 board.
                             Table 2-35 below describes each voltage regulator.

Table 2-35.ESDK 1C6 Board Regulators
  Board            Part      Manufacturer       Type        Voltage           Provides Power to
 Reference        Number                                    Output
U12             LD1085-33    ST               Linear       3.3V       •    Cyclone VCC_IO
                             Microelectronics                         •    CFI Flash
                                                                      •    SRAM
                                                                      •    SDRAM
                                                                      •    Configuration PROM
                                                                      •    USB1.1 Phy Chip
                                                                      •    RS232 Transceiver Chip
                                                                      •    Clock Generator Chip
                                                                      •    Push Button switches
                                                                      •    DIP Switches
                                                                      •    LEDs
                                                                      •    Santacruz Expansion Headers
U13             LM1084 IS-   National       Linear         5.0V       •    Reset Chip
                5.0          Semiconductors                           •    I2C RTC
                                                                      •    I2C EEPROM
                                                                      •    Level Translator (Voltage
                                                                           Limiter Switches)
                                                                      •    LCD
                                                                      •    PS/2 Connector
                                                                      •    Santacruz Expansion Headers
U14             LM1086 CS-   National       Linear         1.5V       •    Cyclone VCC_INT
                ADJ          Semiconductors                           •    Cyclone VCCA_PLL




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Power Supply Circuitry




                               Power Plane Connectors (JP6-JP8, JP10)
                               The ESDK 1C6 board contains Power Plane Connectors for debugging and
                               testing purpose. The connection details of these connectors are given in the
                               following sections:

                               DC Input power Header (JP8)
                               The connection details of the DC input power header JP8 is mentioned in the
                               Table 2-36 below:

                                Table 2-36.DC Input Power Header (JP8)
                                               Header                                Signal
                                JP 8.1                                 Regulated/Unregulated DC Power
                                                                       input (Same as is available through
                                                                       the DC power jack SW1)
                                JP 8.2                                 GND


                               +5V Power Header (JP6)
                               The connection details of the +5V power header JP6 is mentioned in the
                               Table 2-37 below:

                                Table 2-37.+5V power Header (JP6)
                                               Header                                Signal
                                JP 6.1                                 Regulated +5V DC Power on the
                                                                       ESDK 1C6 Board
                                JP 6.2                                 GND




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                                                                                    Board Components




                         +3.3V Power Header (JP7)
                         The connection details of the +3.3V power header JP7 is mentioned in the
                         Table 2-38 below:

                         Table 2-38.+3.3V power Header (JP7)
                                        Header                                 Signal
                         JP 7.1                                 Regulated +3.3V DC Power on the
                                                                ESDK 1C6 Board
                         JP 7.2                                 GND


                         +1.5V Power Header (JP10)
                         The connection details of the +1.5V power header JP6 is mentioned in the
                         Table 2-39 below:

                         Table 2-39.+1.5V power Header (JP10)
                                        Header                                 Signal
                         JP 10.1                                Regulated +1.5V DC Power on the
                                                                ESDK 1C6 Board
                         JP 10.2                                GND


                         Voltage Limiter Switches (U2-U3, U9-U10, U23-U30)
                         Each signal passes through analog switches to protect the EP1C6 from 5-V
                         logic levels. Analog switches are permanently enabled. These voltage limit-
                         ers combine with J1, J2, J3 and J4, which make up the Expansion Prototype
                         Connector. See ““Expansion Connectors” on page 37 and “Power Supply Cir-
                         cuitry” on page 52.




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July 2009                   Embedded Systems Development Kit Reference Manual (Cyclone Edition, EP1C6)
                                                                    Appendix A:
                                                                Shared Bus Table


                         Table A gives full description about the shared signal lines on the ESDK 1C6
                         board and signal details of the same.

                         Table A. Shared Lines on ESDK 1C6 board
                           FPGA Pin                                Signal Name
                             No.
                                                SRAM            SDRAM           FLASH          LCD
                         11               ---             SDRAM CLK       ---            ---
                         63               AD-07           AD-07           AD-07          ---
                         64               AD-08           AD-08           AD-08          ---
                         65               AD-09           AD-09           AD-09          ---
                         66               AD-10           AD-10           AD-10          ---
                         67               AD-11           AD-11           AD-11          ---
                         68               AD-12           BA0             AD-12          ---
                         74               AD-13           BA1             AD-13          ---
                         75               AD-14           CAS             AD-14          ---
                         76               AD-15           RAS             AD-15          ---
                         77               LB              LDQM            AD-16          ---
                         78               ---             ---             AD-19          ---
                         79               WE_n            WE_n            WE_n           ---
                         80               ---             ---             RY/BY_n        ---
                         81               ---             ---             AD-18          ---
                         82               UB              UDQM            AD-17          ---
                         83               AD-06           AD-06           AD-06          ---
                         84               AD-05           AD-05           AD-05          ---
                         85               AD-04           AD-04           AD-04          ---
                         86               AD-03           AD-03           AD-03          ---
                         87               AD-02           AD-02           AD-02          ---


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July 2009                     Embedded Systems Development Kit Reference Manual (Cyclone Edition, EP1C6)
                         Table A. Shared Lines on ESDK 1C6 board
                          FPGA Pin                                 Signal Name
                            No.
                                                SRAM            SDRAM           FLASH          LCD
                         88               AD-01           AD-01           AD-01          ---
                         93               AD-00           AD-00           AD-00          ---
                         94               DQ-00           DQ-00           DQ-00          DQ-00
                         95               DQ-08           DQ-08           DQ-08          ---
                         96               DQ-01           DQ-01           DQ-01          DQ-01
                         97               DQ-09           DQ-09           DQ-09          ---
                         98               DQ-02           DQ-02           DQ-02          DQ-02
                         99               DQ-10           DQ-10           DQ-10          ---
                         100              DQ-03           DQ-03           DQ-03          DQ-03
                         101              DQ-11           DQ-11           DQ-11          ---
                         102              DQ-04           DQ-04           DQ-04          DQ-04
                         103              DQ-12           DQ-12           DQ-12          ---
                         104              DQ-05           DQ-05           DQ-05          DQ-05
                         105              DQ-13           DQ-13           DQ-13          ---
                         106              DQ-06           DQ-06           DQ-06          DQ-06
                         107              DQ-14           DQ-14           DQ-14          ---
                         113              DQ-07           DQ-07           DQ-07          DQ-07
                         114              DQ-15/A-1       DQ-15/A-1       DQ-15/A-1      ---
                         115              ---             CKE             BYTE_n         ---
                         116              CE_n            ---             ---            ---
                         117              -               ---             CE_n           ---
                         118              OE_n            ---             OE_n           ---
                         119              -               CE_n            ---            ---




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July 2009                     Embedded Systems Development Kit Reference Manual (Cyclone Edition, EP1C6)
                                            Appendix B:
                         Clocking Chip Pin Configuration


                         Table B describes the clocking chip pin configuration.

                         Table B.      Clocking Chip Pin Configuration
                          Clock Chip             Pin Name                      Connection
                            Pin No.
                         1                GND1                      Board ground
                         2                X1                        Crystal Y 1.1
                         3                X2                        Crystal Y 1.2
                         4                GND2                      Board ground
                         5                PCICLK F                  Clock setting Jumper JP 3.7
                         6                PCICLK F                  NC
                         7                PCICLK0                   Cyclone CLK0 (U 11.28)
                         8                PCICLK1                   NC
                         9                VDD2                      +3.3 Volt Supply
                         10               PCICLK2                   Santa Cruz Connector J4.9
                         11               PCICLK3                   NC
                         12               PCICLK4 / SEL100/66#      CPU clock select jumper J7.2
                         13               VDD3                      +3.3 Volt Supply
                         14               48 MHz                    Clock Setting Jumper JP 3.3
                         15               GND3                      Board ground
                         16               SPREAD#                   Tied high +3.3 Volt
                         17               PD#                       Tied high +3.3 Volt
                         18               CPU_STOP#                 Cyclone U 11.123 (Drive this pin
                                                                    low to stop the CPU clock)
                         19               PCI_STOP#                 J5.2 (JP5.1 = GND,
                                                                    JP5.2=PCI_STOP, JP5.3=VCC)
                         20               GND                       Board ground
                         21               VDDLC                     +3.3 Volt Supply



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July 2009                     Embedded Systems Development Kit Reference Manual (Cyclone Edition, EP1C6)
                         Table B.      Clocking Chip Pin Configuration
                         Clock Chip              Pin Name                      Connection
                           Pin No.
                         22               CPUCLK2                   Clock header JP 4.1
                         23               CPUCLK1                   NC
                         24               CPUCLK0                   Cyclone CLK2 (U 11. 153)
                         25               VDDLA                     +3.3 Volt Supply
                         26               IOAPIC                    Clock header JP 19.1
                         27               VDD1                      +3.3 Volt Supply
                         28               REF0                      Clock setting Jumper JP3.6




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July 2009                     Embedded Systems Development Kit Reference Manual (Cyclone Edition, EP1C6)

				
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