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					A Project Report on VLSI

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INTRODUCTION
What is VLSI? VLSI stands for "Very Large Scale Integration". This is the field which involves packing more and more logic devices into smaller and smaller areas.Thanks to VLSI, circuits that would have taken boardfuls of space can now be put into a small space few millimeters across! This has opened up a big opportunity to do things that were not possible before. VLSI circuits are everywhere ... your computer, your car, your brand new state-ofthe-art digital camera, the cell-phones, and what have you. All this involves a lot of expertise on many fronts within the same field, which we will look at in later sections. VLSI has been around for a long time, there is nothing new about it ... but as a side effect of advances in the world of computers, there has been a dramatic proliferation of tools that can be used to design VLSI circuits. Alongside, obeying Moore's law, the capability of an IC has increased exponentially over the years, in terms of computation power, utilisation of available area, yield. The combined effect of these two advances is that people can now put diverse functionality into the IC's, opening up new frontiers. Examples are embedded systems, where intelligent devices are put inside everyday objects, and ubiquitous computing where small computing devices proliferate to such an extent that even the shoes you wear may actually do something useful like monitoring your heartbeats! These two fields are kinda related, and getting into their description can easily lead to another article.

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Fig a.1 VLSI Integrated Circuit (IC) with the latest technology can have a million or more components in it. Designing the IC, describing the design at different levels and the details required for fabrication, so that the IC can be tested satisfactorily are all challenging tasks - considering the size and complexity of ICs at this level.

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DEALING WITH VLSI CIRCUITS
Digital VLSI circuits are predominantly CMOS based. The way normal blocks like latches and gates are implemented is different from what students have seen so far, but the behaviour remains the same. All the miniaturisation involves new things to consider. A lot of thought has to go into actual implementations as well as design. Let us look at some of the factors involved ... 1. Circuit Delays. Large complicated circuits running at very high frequencies have one big problem to tackle - the problem of delays in propagation of signals through gates and wires ... even for areas a few micrometers across! The operation speed is so large that as the delays add up, they can actually become comparable to the clock speeds. 2. Power. Another effect of high operation frequencies is increased consumption of power. This has two-fold effect devices consume batteries faster, and heat dissipation increases. Coupled with the fact that surface areas have decreased, heat poses a major threat to the stability of the circuit itself. 3. Layout. Laying out the circuit components is task common to all branches of electronics. Whats so special in our case is that there are many possible ways to do this; there can be multiple layers of different materials on the same silicon, there can be different arrangements of the smaller parts for the same component and so on.

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A typical digital design flow is as follows:
Specification Architecture RTL Coding RTL Verification Synthesis Backend Tape Out to Foundry to get end product….a wafer with repeated number of identical Ics Both forms of description are then used to generate a very lowlevel description that actually spells out how all this is to be fabricated on the silicon chips. This will result in the manufacture of the intended IC.

A typical analog design flow is as follows:
In case of analog design, the flow changes somewhat. Specifications Architecture Circuit Design SPICE Simulation Layout Parametric Extraction / Back Annotation Final Design Tape Out to foundry. While digital design is highly automated now, very small portion of analog design can be automated. There is a hardware description language called AHDL but is not widely used as it
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does not accurately give us the behavioral model of the circuit because of the complexity of the effects of parasitic on the analog behavior of the circuit. Many analog chips are what are termed as “flat” or non-hierarchical designs. This is true for small transistor count chips such as an operational amplifier, or a filter or a power management chip. For more complex analog chips such as data converters, the design is done at a transistor level, building up to a cell level, then a block level and then integrated at a chip level. Not many CAD tools are available for analog design even today and thus analog design remains a difficult art. SPICE remains the most useful simulation tool for analog as well as digital design.

HARDWARE DISCRIPTION LANGUAGE (HDL)
In electronics, a hardware description language or HDL is any language from a class of computer languages and/or programming languages for formal description of electronic circuits, and more specifically, digital logic. It can describe the circuit's operation, its design and organization, and tests to verify its operation by means of simulation. HDLs are used to write executable specifications of some piece of hardware. A simulation program, designed to implement the underlying semantics of the language statements, coupled with simulating the progress of time, provides the hardware designer with the ability to model a piece of hardware before it is created physically.

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VHDL Very High Speed Integrated Circuits Hardware Discription Language
All modern digital designs start with a designer writing a hardware description of the IC (using HDL or Hardware Description Language) in Verilog/VHDL. A Verilog or VHDL program essentially describes the hardware (logic gates, FlipFlops, counters etc) and the interconnect of the circuit blocks and the functionality. Various CAD tools are available to synthesize a circuit based on the HDL. The most widely used synthesis tools come from two CAD companies. Synposys and Cadence. Without going into details, we can say that the VHDL, can be called as the "C" of the VLSI industry. VHDL stands for "VHSIC Hardware Definition Language", where VHSIC stands for "Very High Speed Integrated Circuit". This languages is used to design the circuits at a high-level, in two ways. It can either be a behavioural description, which describes what the circuit is supposed to do, or a structural description, which describes what the circuit is made of. There are other languages for describing circuits, such as Verilog, which work in a similar fashion.

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VHDL development was initiated originally from the American Department of Defense (DoD). They requested a language for describing a hardware, which had to be readable for machines and humans at the same time and strictly forces the developer to write structured and comprehensible code, so that the source code itself can serve as a kind of specification document. Most important was the concept of concurrency to cope with the parallelism of digital hardware. Sequential statements to model very complex functions in a compact form were also allowed.

In 1987, VHDL was standardized by the American Institute of Electrical and Electronics Engineers (IEEE) for the first time with the first official update in 1993. Apart from the file handling procedures these two versions of the standard are compatible. The standard of the language is described in the Language Reference Manual (LRM).

VHDL is used mainly for the development of Application Specific Integrated Cicuits (ASICs). Tools for the automatic transformation of VHDL code into a gate-level netlist were developed already at an early point of time. This transformation is called synthesis and is an integral part of current design flows.

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For the use with Field Programmable Gate Arrays (FPGAs) several problems exist. In the first step, boolean equations are derived from the VHDL description, no matter, whether an ASIC or a FPGA is the target technology. But now, this boolean code has to be partitioned into the configurable logic blocks (CLB) of the FPGA. This is more difficult than the mapping onto an ASIC library. Another big problem is the routing of the CLBs as the available resources for interconnections are the bottleneck of current FPGAs. While synthesis tools cope pretty well with complex designs, they obtain usually only suboptimal results. Therefore, VHDL is hardly used for the design of low complexity Programmable Logic Devices (PLDs).

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Designing process
In VHDL an entity is used to describe a hardware module. An entity can be described using, 1. Entity declaration. 2. Architecture. 3. Configuration 4. Package declaration. 5. Package body. Let‟s see what are these? Entity declaration: It defines the names, input output signals and modes of a hardware module. Syntax: entity Port entity_name is declaration;

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end

entity_name;

An entity declaration should starts with „entity‟ and ends with „end‟ keywords. Ports are interfaces through which an entity can communicate with its environment. Each port must have a name, direction and a type. An entity may have no port declaration also. The direction will be input, output or inout.

In Out Inout

Port can be read Port can be written Port can be read and written

Buffer Port can be read and written, it can have only one source. Architecture:

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It describes the internal description of design or it tells what is there inside design. Each entity has atleast one architecture and an entity can have many architecture. Architecture can be described using structural, dataflow, behavioral or mixed style. Architecture can be used to describe a design at different levels of abstraction like gate level, register transfer level (RTL) or behavior level. Syntax: architecture architecture_name of entity_name

architecture_declarative_part; begin Statements; end architecture_name; Here we should specify the entity name for which we are writing the architecture body. The architecture statements should be inside the begin and end keyword. Architecture declarative part may contain variables, constants, or component declaration. Configuration:

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If an entity contains many architectures and any one of the possible architecture binding with its entity is done using configuration. It is used to bind the architecture body to its entity and a component with an entity. Syntax: configuration configuration_name of entity_name is block_configuration; end configuration_name. Block_configuration defines the binding of components in a block. This can be written as for block_name component_binding; end for; block_name is the name of the architecture body. Component binding binds the components of the block to entities. This can be written as, for component_labels:component_name block_configuration; end for; Package declaration:

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Package declaration is used to declare components, types, constants, functions and so on. Syntax: package package_name is

Declarations; end package_name; Package body: A package body is used to declare the definitions and procedures that are declared in corresponding package. Values can be assigned to constants declared in package in package body. Syntax: package body Function_procedure end package_name; The internal working of an entity can be defined using different modeling styles inside architcture body. They are package_name is

definitions;

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1. 2. 3.

Dataflow modeling. Behavioral modeling. Structural modeling.

Structure of an entity:

Let‟s try to understand with the help of one example. Dataflow modeling: In this style of modeling, the internal working of an entity can be implemented using concurrent signal assignment. Let‟s take half adder example which is having one XOR gate and a AND gate.

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Library IEEE; use IEEE.STD_LOGIC_1164.all; entity ha_en is port (A,B:in bit;S,C:out bit); end ha_en; architecture ha_ar of ha_en is begin S<=A xor B; C<=A and B; end ha_ar;

Here STD_LOGIC_1164 is an IEEE standard which defines a nine-value logic type, called STD_ULOGIC. use is a keyword, which imports all the declarations from this package. The architecture body consists of concurrent signal assignments, which describes the functionality of the design. Whenever there

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is a change in RHS, the expression is evaluated and the value is assigned to LHS. Behavioral modeling: In this style of modeling, the internal working of an entity can be implemented using set of statements. It contains:
   

Process statements Sequential statements Signal assignment statements Wait statements

Process statement is the primary mechanism used to model the behavior of an entity. It contains sequential statements, variable assignment (:=) statements or signal assignment (<=) statements etc. It may or may not contain sensitivity list. If there is an event occurs on any of the signals in the sensitivity list, the statements within the process is executed. Inside the process the execution of statements will be sequential and if one entity is having two processes the execution of these

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processes will be concurrent. At the end it waits for another event to occur.

library IEEE; use IEEE.STD_LOGIC_1164.all; entity ha_beha_en is port( A : in BIT; B : in BIT; S : out BIT; C : out BIT ); end ha_beha_en;

architecture ha_beha_ar of ha_beha_en is begin process_beh:process(A,B) begin S<= A xor B; C<=A and B; end process process_beh; end ha_beha_ar;

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Here whenever there is a change in the value of a or b the process statements are executed. Structural modeling: The implementation of an entity is done through set of interconnected components. It contains:
   

Signal declaration. Component instances Port maps. Wait statements.

Component declaration: Syntax: component component_name [is] List_of_interface ports; end component component_name;

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Before instantiating the component it should be declared using component declaration as shown above. Component declaration declares the name of the entity and interface of a component. Let‟s try to understand this by taking the example of full adder using 2 half adder and 1 OR gate.

library IEEE; use IEEE.STD_LOGIC_1164.all; entity fa_en is port(A,B,Cin:in bit; SUM, CARRY:out bit); end fa_en;

architecture fa_ar of fa_en is component ha_en

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port(A,B:in bit;S,C:out bit); end component;

signal C1,C2,S1:bit; begin HA1:ha_en port map(A,B,S1,C1); HA2:ha_en port map(S1,Cin,SUM,C2); CARRY <= C1 or C2; end fa_ar; The program we have written for half adder in dataflow modeling is instantiated as shown above. ha_en is the name of the entity in dataflow modeling. C1, C2, S1 are the signals used for internal connections of the component which are declared using the keyword signal. Port map is used to connect different components as well as connect components to ports of the entity. Component instantiation is done as follows. Component_label: component_name port map (signal_list);

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Signal_list is the architecture signals which we are connecting to component ports. This can be done in different ways. What we declared above is positional binding. One more type is the named binding. The above can be written as, HA1:ha_en port map(A => A,B => B, S => S1 ,C => C1 ); HA2:ha_en port map(A => S1,B => Cin, S=> SUM, C => C2); Test bench: The correctness of the above program can be checked by writing the test bench. The test bench is used for generating stimulus for the entity under test. Let‟s write a simple test bench for full adder. library IEEE; use IEEE.STD_LOGIC_1164.all; entity tb_en is end tb_en; architecture tb_ar of tb_en is signal a_i,b_i,c_i,sum_i,carry_i:bit;

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begin eut: entity work.fa_en(fa_ar) port map(A=>a_i,B=>b_i,Cin=>c_i,SUM=>sum_i,CARRY=>carry _i); stimulus: process begin a_i<='1';b_i<='1';c_i<='1'; wait for 10ns; a_i<='0';b_i<='1';c_i<='1'; wait for 10ns; a_i<='1';b_i<='0';c_i<='0'; wait for 10ns; if now=30ns then wait; end if; end process stimulus; end tb_ar; Here now is a predefined function that returns the current simulation time

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