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D8.3 Counters

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					  Counters

Discussion D8.3
               Counters
• Divide-by-8 Counter
• Behavioral Counter in Verilog
• Counter using One-Hot State Machine
      Divide-by-8 Counter

 s0          s1           s2           s3
000         001          010          011




 s7          s6           s5           s4
111         110          101          100




A state diagram for a divide by 8 counter
Divide-by-8 Counter
       Present state    Next state
State Q2 Q1 Q0         D2 D1 D0
 s0   0    0     0     0   0     1
 s1   0    0     1     0   1     0
 s2   0    1     0     0   1     1
 s3   0    1     1     1   0     0
 s4   1    0     0     1   0     1
 s5   1    0     1     1   1     0
 s6   1    1     0     1   1     1
 s7   1    1     1     0   0     0


      A state-transition table
               Divide-by-8 Counter
       Present state    Next state        D   Q
State Q2 Q1 Q0         D2 D1 D0
                                     D0   D   Q    Q0
                                          CLK ~Q
                                          CLK ~Q
 s0   0    0     0     0   0    1
 s1   0    0     1     0   1    0
 s2   0    1     0     0   1    1         D   Q
 s3   0    1     1     1   0    0    D1   D   Q    Q1
                                          CLK ~Q
 s4   1    0     0     1   0    1         CLK ~Q

 s5   1    0     1     1   1    0
 s6   1    1     0     1   1    1
 s7   1    1     1     0   0    0    D2   D
                                          D
                                              Q
                                              Q    Q2
                                          CLK ~Q
                                          CLK ~Q
                       Divide-by-8 Counter
                                       Q1 Q0
       Present state     Next state
                                      Q2   00   01   11   10
State Q2 Q1 Q0          D2 D1 D0
 s0   0    0     0       0   0   1      0            1
 s1   0    0     1       0   1   0
                                        1   1   1         1
 s2   0    1     0       0   1   1
 s3   0    1     1       1   0   0
                                                D2
 s4   1    0     0       1   0   1
 s5   1    0     1       1   1   0
                                       D2 = ~Q2 & Q1 & Q0
 s6   1    1     0       1   1   1
                                            | Q2 & ~Q1
 s7   1    1     1       0   0   0
                                            | Q2 & ~Q0
                     Divide-by-8 Counter
       Present state    Next state    Q1 Q0
State Q2 Q1 Q0         D2 D1 D0      Q2   00   01    11   10

 s0   0    0     0     0   0    1      0        1         1
 s1   0    0     1     0   1    0
 s2   0    1     0     0   1    1      1        1         1
 s3   0    1     1     1   0    0
 s4   1    0     0     1   0    1               D1
 s5   1    0     1     1   1    0
                                           D1 = ~Q1 & Q0
 s6   1    1     0     1   1    1
                                               | Q1 & ~Q0
 s7   1    1     1     0   0    0
                     Divide-by-8 Counter
       Present state    Next state    Q1 Q0
State Q2 Q1 Q0         D2 D1 D0      Q2   00     01   11   10

 s0   0    0     0     0   0    1      0   1               1
 s1   0    0     1     0   1    0
 s2   0    1     0     0   1    1      1   1               1
 s3   0    1     1     1   0    0
 s4   1    0     0     1   0    1                D0
 s5   1    0     1     1   1    0
 s6   1    1     0     1   1    1              D0 = ~Q0
 s7   1    1     1     0   0    0
                Divide-by-8 Counter

                                  D        Q
                                                Q2
                                      Q2
A Divide by 8 counter              CLK
                                           !Q

Circuit using D Flip-flops

                                  D        Q
                                                Q1
                                      Q1
                                           !Q
                                   CLK




                                  D        Q
                                                Q0
                                      Q0
                                           !Q
                                   CLK




                                  CLK
module DFF (D, clk, clr, Q);

input clk ;
wire clk ;                         D         Q
input clr ;                        D         Q
wire clr ;                         CLK ~Q
                                   clk ~Q
input D ;
wire D ;                               clr

output Q ;
reg Q ;

always @(posedge clk or posedge clr)
      if(clr == 1)
            Q <= 0;
      else
            Q <= D;

endmodule
module count3 ( Q ,clr ,clk );
                                                D   Q
input clr ;
                                         D0     D   Q    Q0
                                                CLK ~Q
wire clr ;                                      CLK ~Q
input clk ;
wire clk ;

output [2:0] Q ;                                D   Q
wire [2:0] Q ;                           D1     D   Q    Q1
wire [2:0] D ;                                  CLK ~Q
                                                CLK ~Q

assign D[2] = ~Q[2] & Q[1] & Q[0]
       | Q[2] & ~Q[1]
       | Q[2] & ~Q[0];
                                                D   Q
                                         D2     D   Q    Q2
assign D[1] = ~Q[1] & Q[0]                      CLK ~Q
             | Q[1] & ~Q[0];                    CLK ~Q


assign D[0] = ~Q[0];

DFF U2(.D(D[2]), .clk(clk), .clr(clr), .Q(Q[2]));
DFF U1(.D(D[1]), .clk(clk), .clr(clr), .Q(Q[1]));
DFF U0(.D(D[0]), .clk(clk), .clr(clr), .Q(Q[0]));

endmodule
count3 Simulation
               Counters
• Divide-by-8 Counter
• Behavioral Counter in Verilog
• Counter using One-Hot State Machine
                 3-Bit Counter
           clr
                   count3   Q(2 downto 0)
           clk



Behavior
  always @(posedge clk or posedge clr)
   begin
     if(clr == 1)
        Q <= 0;
     else
        Q <= Q + 1;
   end
module counter3 (clk, clr, Q );           counter3.v

input clr ;
wire clr ;
input clk ;
wire clk ;

output [2:0] Q ;
reg [2:0] Q ;

//    3-bit counter
always @(posedge clk or posedge clr)
  begin
                                     Asynchronous clear
    if(clr == 1)
       Q <= 0;
    else
       Q <= Q + 1;
  end
                                      Output count increments
endmodule                             on rising edge of clk
counter3 Simulation
          Recall Divide-by-8 Counter
                                          D   Q
       Present state    Next state   D0   D   Q    Q0
State Q2 Q1 Q0         D2 D1 D0           CLK ~Q
                                          CLK ~Q

 s0   0    0     0     0   0    1
 s1   0    0     1     0   1    0
 s2   0    1     0     0   1    1    D1   D
                                          D
                                              Q
                                              Q    Q1
 s3   0    1     1     1   0    0         CLK ~Q
                                          CLK ~Q
 s4   1    0     0     1   0    1
 s5   1    0     1     1   1    0
 s6   1    1     0     1   1    1         D   Q
 s7   1    1     1     0   0    0    D2   D   Q    Q2
                                          CLK ~Q
                                          CLK ~Q



Use Q2, Q1, Q0 as inputs to a combinational circuit
to produce an arbitrary waveform.
                                Example
State Q2 Q1 Q0          D2 D1           D0    y      Q1 Q0
                                                    Q2   00           01   11          10
 s0   0     0       0   0       0       1     1
 s1   0     0       1   0       1       0     1       0       1       1
 s2   0     1       0   0       1       1     0
 s3   0     1       1   1       0       0     0       1               1        1
 s4   1     0       0   1       0       1     0
 s5   1     0       1   1       1       0     1
                                                              y = ~Q2 & ~Q1
 s6   1     1       0   1       1       1     0
                                                                 | Q2 & Q0
 s7   1     1       1   0       0       0     1



      1 1       0   0   0   1       0       1 1 1    0    0       0    1   0       1
              Counters
• Divide-by-8 Counter
• Behavioral Counter in Verilog
• Counter using One-Hot State Machine
           One-Hot State Machines
    s0       s1        s2       s3              D     Q
   000      001       010      011         D0   D
                                                CLK
                                                      Q
                                                       ~Q
                                                            Q0
                                                CLK   ~Q




    s7       s6        s5       s4
   111      110       101      100              D     Q
                                           D1   D
                                                CLK
                                                      Q
                                                       ~Q
                                                            Q1
                                                CLK   ~Q




Instead of using the minimum number of
                                                D     Q
flip-flops (3) to implement the state      D2   D
                                                CLK
                                                      Q
                                                       ~Q
                                                            Q2
                                                CLK   ~Q
machine, one-hot encoding uses one
flip-flop per state (8) to implement the
state machine.
     Why use One-Hot State Machines?

     s0       s1      s2      s3
    000      001     010     011
                                           D        Q
                                                         Q2
                                               Q2
                                                    !Q
                                            CLK
     s7       s6      s5      s4
    111      110     101     100


                                           D        Q
                                                         Q1
                                               Q1
                                                    !Q
                                            CLK

Using one-hot encoding or one flip-flop
per state (8) will normally simplify the   D        Q
                                                         Q0
combinational logic at the expense of          Q0
                                                    !Q
more flip-flops.                            CLK




                                           CLK
Let's see how for the 3-bit counter
                       One-Hot Encoding
       Present state     Next state
State Q2 Q1 Q0           D[0:7]
 s0   0    0     0         s1          Think of each state as a flip-flop
 s1   0    0     1         s2
 s2   0    1     0         s3
 s3   0    1     1         s4             s0
                                         000
                                                   s1
                                                  001
                                                           s2
                                                          010
                                                                  s3
                                                                 011

 s4   1    0     0         s5
 s5   1    0     1         s6             s7       s6      s5     s4
                                         111      110     101    100
 s6   1    1     0         s7
 s7   1    1     1         s0
                                               D[i] = s[i-1]

                                 This is just a ring counter!
D     Q
          s0
               3-bit Counter           State Q2 Q1   Q0
clk



          s1
                                        s0   0   0   0
D
clk
      Q
                                        s1   0   0   1
                               Q0       s2   0   1   0
          s2
D
clk
      Q
                                        s3   0   1   1
                                        s4   1   0   0
                                             1   0   1
          s3
D     Q                                 s5
clk
                               Q1
                                        s6   1   1   0
D     Q
          s4
                                        s7   1   1   1
clk



          s5
D     Q
                               Q2
clk
                                    Q2 = s4 | s5 | s6 | s7
          s6
D
clk
      Q
                                    Q1 = s2 | s3 | s6 | s7

D     Q
          s7                        Q0 = s1 | s3 | s5 | s7
clk
module cnt3hot1(clk,clr,Q);                  D     Q
                                                       s0

                                             clk



input clk;                                             s1

input clr;
                                             D     Q
                                             clk

output [2:0] Q;                                             Q0

wire [2:0] Q;                                D     Q
                                                       s2


reg [0:7] s;                                 clk



                                                       s3

//     8-bit Ring Counter                    D
                                             clk
                                                   Q


always @(posedge clk or posedge clr)                        Q1


begin                                        D     Q
                                                       s4


    if(clr == 1)                             clk


       s <= 8'b10000000;                               s5
    else                                     D
                                             clk
                                                   Q
                                                            Q2

       begin
          s[0] <= s[7];                      D     Q
                                                       s6

          s[1:7] <= s[0:6];                  clk

       end
end                                          D     Q
                                                       s7

                                             clk


//       3-bit counter
assign   Q[2] = s[4] | s[5] | s[6] | s[7];
assign   Q[1] = s[2] | s[3] | s[6] | s[7];
assign   Q[0] = s[1] | s[3] | s[5] | s[7];

endmodule

				
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posted:12/10/2012
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