Docstoc

vhdl lab question

Document Sample
vhdl lab question Powered By Docstoc
					                      SATHYABAMA UNIVERSITY
                     (Established under section 3 of UGC act 1956)
                Department of Electronics and Communication
                 University Practical Examination Oct.2012
Lab Code/Name:SECX4012 /Hardware Description Language Lab
Max.Mark:100                                              Date:13-10-2012
Register Number: 3 0 1 3 6


Booklet Number: …………………….

QUESTION :
  1. A). Design and simulate the full adder using vhdl.
     B). Design a 4-bit asynchronus counter and verify the output using vhdl.

       Sl.no     Description               Marks allocated Marks secured
       1         Algorithm,circuit         30
                 diagram, tabulation
       2         Program                   30
       3         Simulation&Synthesis      20
       4         Record                    10
       5         Viva Voce                 10
       6         Total                     100


                      SATHYABAMA UNIVERSITY
                     (Established under section 3 of UGC act 1956)
                Department of Electronics and Communication
                 University Practical Examination Oct.2012
Lab Code/Name:SECX4012 /Hardware Description Language Lab
Max.Mark:100                                              Date:13-10-2012
Register Number: 3 0 1 3 6


Booklet Number: …………………….

QUESTION :
  2. A). Design and simulate the full subtractor using vhdl.
     B). Design and develop a vhdl code for JK-FLIPFLOP and verify the output


       Sl.no     Description               Marks allocated Marks secured
       1         Algorithm,circuit         30
                 diagram, tabulation
       2         Program                   30
       3         Simulation&Synthesis      20
       4         Record                    10
       5         Viva Voce                 10
       6         Total                     100
                     SATHYABAMA UNIVERSITY
                     (Established under section 3 of UGC act 1956)
                Department of Electronics and Communication
                 University Practical Examination Oct.2012
Lab Code/Name:SECX4012 /Hardware Description Language Lab
Max.Mark:100                                              Date:13-10-2012
Register Number: 3 0 1 3 6


Booklet Number: …………………….

QUESTION :
  3. A). Design and develop a vhdl code for 8*3 Encoder and verify the output
     B). Design a 4-bit asynchronus counter and verify the output using vhdl.

       Sl.no    Description                Marks allocated Marks secured
       1        Algorithm,circuit          30
                diagram, tabulation
       2        Program                    30
       3        Simulation&Synthesis       20
       4        Record                     10
       5        Viva Voce                  10
       6        Total                      100


                     SATHYABAMA UNIVERSITY
                     (Established under section 3 of UGC act 1956)
                Department of Electronics and Communication
                 University Practical Examination Oct.2012
Lab Code/Name:SECX4012 /Hardware Description Language Lab
Max.Mark:100                                              Date:13-10-2012
Register Number: 3 0 1 3 6


Booklet Number: …………………….
QUESTION :
   4. A). Design and develop a vhdl code for BCD to Excess-3 code and verify the
      output
      B). Design and simulate the SR Flip-Flop using vhdl.

       Sl.no    Description                Marks allocated Marks secured
       1        Algorithm,circuit          30
                diagram, tabulation
       2        Program                    30
       3        Simulation&Synthesis       20
       4        Record                     10
       5        Viva Voce                  10
       6        Total                      100
                      SATHYABAMA UNIVERSITY
                     (Established under section 3 of UGC act 1956)
                Department of Electronics and Communication
                 University Practical Examination Oct.2012
Lab Code/Name:SECX4012 /Hardware Description Language Lab
Max.Mark:100                                              Date:13-10-2012
Register Number: 3 0 1 3 6


Booklet Number: …………………….
QUESTION :
   5. A). Design and develop a vhdl code for 3*8 Decoder and verify the output
      B) .Design and simulate SIPO shift register using vhdl.

       Sl.no     Description               Marks allocated Marks secured
       1         Algorithm,circuit         30
                 diagram, tabulation
       2         Program                   30
       3         Simulation&Synthesis      20
       4         Record                    10
       5         Viva Voce                 10
       6         Total                     100


                      SATHYABAMA UNIVERSITY
                     (Established under section 3 of UGC act 1956)
                Department of Electronics and Communication
                 University Practical Examination Oct.2012
Lab Code/Name:SECX4012 /Hardware Description Language Lab
Max.Mark:100                                              Date:13-10-2012
Register Number: 3 0 1 3 6


Booklet Number: …………………….
QUESTION :
   6. A). Design and simulate vhdl code for comparator and verify the output.
      B). Design and simulate the D Flip-Flop using vhdl.

       Sl.no     Description               Marks allocated Marks secured
       1         Algorithm,circuit         30
                 diagram, tabulation
       2         Program                   30
       3         Simulation&Synthesis      20
       4         Record                    10
       5         Viva Voce                 10
       6         Total                     100
                      SATHYABAMA UNIVERSITY
                     (Established under section 3 of UGC act 1956)
                Department of Electronics and Communication
                 University Practical Examination Oct.2012
Lab Code/Name:SECX4012 /Hardware Description Language Lab
Max.Mark:100                                              Date:13-10-2012
Register Number: 3 0 1 3 6


Booklet Number: …………………….
QUESTION :
   7. A). Design and develope a vhdl code for 2*4 Decoder and verify the output
      B). Design and develope a vhdl code for T-FLIPFLOP and verify the output

       Sl.no     Description               Marks allocated Marks secured
       1         Algorithm,circuit         30
                 diagram, tabulation
       2         Program                   30
       3         Simulation&Synthesis      20
       4         Record                    10
       5         Viva Voce                 10
       6         Total                     100


                      SATHYABAMA UNIVERSITY
                     (Established under section 3 of UGC act 1956)
                Department of Electronics and Communication
                 University Practical Examination Oct.2012
Lab Code/Name:SECX4012 /Hardware Description Language Lab
Max.Mark:100                                              Date:13-10-2012
Register Number: 3 0 1 3 6



Booklet Number: …………………….
QUESTION :
   8. A). Design and develope a vhdl code for 1*4 Demux and verify the output
      B). Design and develope a vhdl code for PIPO shift register and verify the output

       Sl.no     Description               Marks allocated Marks secured
       1         Algorithm,circuit         30
                 diagram, tabulation
       2         Program                   30
       3         Simulation&Synthesis      20
       4         Record                    10
       5         Viva Voce                 10
       6         Total                     100
                     SATHYABAMA UNIVERSITY
                     (Established under section 3 of UGC act 1956)
                Department of Electronics and Communication
                 University Practical Examination Oct.2012
Lab Code/Name:SECX4012 /Hardware Description Language Lab
Max.Mark:100                                              Date:13-10-2012
Register Number: 3 0 1 3 6


Booklet Number: …………………….
QUESTION :
   9. A). Design a 4-bit SISO shift register and verify the output using vhdl.
      B). Design and develope a vhdl code for 4*1mux using case statement and verify
      the output

       Sl.no     Description               Marks allocated Marks secured
       1         Algorithm,circuit         30
                 diagram, tabulation
       2         Program                   30
       3         Simulation&Synthesis      20
       4         Record                    10
       5         Viva Voce                 10
       6         Total                     100


                     SATHYABAMA UNIVERSITY
                     (Established under section 3 of UGC act 1956)
                Department of Electronics and Communication
                 University Practical Examination Oct.2012
Lab Code/Name:SECX4012 /Hardware Description Language Lab
Max.Mark:100                                              Date:13-10-2012
Register Number: 3 0 1 3 6


Booklet Number: …………………….
QUESTION :
   10. A). Design and simulate the full subtractor using vhdl.
       B). Design and develope a vhdl code for JK-FLIPFLOP and verify the output

       Sl.no     Description               Marks allocated Marks secured
       1         Algorithm,circuit         30
                 diagram, tabulation
       2         Program                   30
       3         Simulation&Synthesis      20
       4         Record                    10
       5         Viva Voce                 10
       6         Total                     100
                      SATHYABAMA UNIVERSITY
                      (Established under section 3 of UGC act 1956)
                 Department of Electronics and Communication
                  University Practical Examination Oct.2012
Lab Code/Name:SECX4012 /Hardware Description Language Lab
Max.Mark:100                                              Date:13-10-2012
Register Number: 3 0 1 3 6


Booklet Number: …………………….
QUESTION :
   11. A). Design and develope a vhdl code for Gray to Binary code converter and verify
       the output
       B). Design and develope a vhdl code for SR-FLIPFLOP and verify the output

        Sl.no    Description                Marks allocated Marks secured
        1        Algorithm,circuit          30
                 diagram, tabulation
        2        Program                    30
        3        Simulation&Synthesis       20
        4        Record                     10
        5        Viva Voce                  10
        6        Total                      100


                      SATHYABAMA UNIVERSITY
                      (Established under section 3 of UGC act 1956)
                 Department of Electronics and Communication
                  University Practical Examination Oct.2012
Lab Code/Name:SECX4012 /Hardware Description Language Lab
Max.Mark:100                                              Date:13-10-2012
Register Number: 3 0 1 3 6


Booklet Number: …………………….
QUESTION :
   12. A). Design and develope a vhdl code for SIPO shift register and verify the output
       B). Design and develope a vhdl code for Binary to Gray Code converter and
       verify the output
        Sl.no     Description              Marks allocated Marks secured
        1         Algorithm,circuit        30
                  diagram, tabulation
        2         Program                  30
        3         Simulation&Synthesis     20
        4         Record                   10
        5         Viva Voce                10
        6         Total                    100

				
DOCUMENT INFO
Shared By:
Tags: vhdl, question
Stats:
views:44
posted:12/2/2012
language:English
pages:7
Description: vhdl lab question