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Complex Programmable Logic Devices (CPLDs)

Complex Programmable Logic Devices (CPLD) are another way to extend the density of the simple PLDs. The concept is to have a few PLD
blocks or macrocells on a single device with general purpose interconnect in between. Simple logic paths can be implemented
within a single block. More sophisticated logic will require multiple blocks and use the general purpose interconnect in between to
make these connections.

                Figure 1.3          CPLD Architecture

CPLDs are great at handling wide and complex gating at blistering speeds e.g. 5ns which is equivalent to 200MHz. The timing model for
CPLDs is easy to calculate so before you even start your design you can calculate your in to output speeds.
Why Use a CPLD?

CPLDs enable ease of design, lower development costs, more product revenue for your money, and the opportunity to speed your products
to market...

Ease of Design: CPLDs offer the simplest way to implement design. Once a design has been described, by schematic and/or HDL entry,
a designer simply uses CPLD development tools to optimise, fit, and simulate the design. The development tools create a file, which is
then used to customise (program) a standard off-the-shelf CPLD with the desired functionality. This provides an instant hardware
prototype and allows the debugging process to begin. If modifications are needed, design changes are just entered into the
CPLD development tool, and the design can be re-implemented and tested immediately.

Lower Development Costs: CPLDs offer very low development costs. Ease of design, as described above, allows for shorter
development cycles. Because CPLDs are re-programmable,designers can easily and very inexpensively change their designs.
This allows them to optimise their designs and continues to add new features to continue to enhance their products. CPLD development
tools are relatively inexpensive and in the case of Xilinx, are free. Traditionally, designers have had to face large cost penalties such
as re-work, scrap, and development time. With CPLDs, designers have flexible solutions thus avoiding many traditional design pitfalls.

More Product Revenue: CPLDs offer very short development cycles, which means your products get to market quicker and begin
generating revenue sooner. Because CPLDs are re-programmable, products can be easily modified using ISP over the Internet. This in
turn allows you to easily introduce additional features and quickly generate new revenue from them. (This results in an expanded time
for revenue). Thousands of designers are already using CPLDs to get to market quicker and then stay in the market longer by continuing to
enhance their products even after they have been introduced into the field. CPLDs decrease Time To Market (TTM) and extend Time In
Market (TIM).

Reduced Board Area: CPLDs offer a high level of integration (large number of system gates per area) and are available in very small
form factor packages. This provides the perfect solution for designers of products which must fit into small enclosures or who
have a limited amount of circuit board space to implement the logic design. The CoolRunner CPLDs are available in the latest chip
scale packages, e.g. CP56 which has a pin pitch of 0.5mm and is a mere 6mm by 6mm in size so are ideal for small, low power end

Cost of Ownership: Cost of Ownership can be defined as the amount it costs to maintain, fix, or warranty a product. For instance,
if a design change requiring hardware rework must be made to a few prototypes, the cost might be relatively small. However, as the
number of units that must be changed increases, the cost can become enormous. Because CPLDs are re-programmable, requiring
no hardware rework, it costs much less to make changes to designs implemented using them. Therefore cost of ownership is dramatically
reduced. And don't forget the ease or difficulty of design changes can also affect opportunity costs. Engineers who are spending a lot
of time fixing old designs could be working on introducing new products and features - ahead of the competition.
There are also costs associated with inventory and reliability. PLDs can reduce inventory costs by replacing standard discrete logic
devices. Standard logic has a predefined function and in a typical design lots of different types have to be purchased and stocked. If
the design is changed then there may be excess stock of superfluous devices. This issue can be alleviated by using PLDs i.e.
you only need to stock one device and if your design changes you simply reprogram. By utilising one device instead of many your
board reliability will increase by only picking and placing one device instead of many. Reliability can also be increased by using the ultra
low power CoolRunner CPLDs i.e. lower heat dissipation and lower power operation leads to decreased Failures In Time (FIT).

What is a CPLD?
A Complex Programmable Logic Device (CPLD) is a combination of a fully programmable AND/OR array and a bank of macrocells. The
AND/OR array is reprogrammable and can perform a multitude of logic functions.

        Macrocells are functional blocks that perform combinatorial or sequential logic, and also have the added flexibility for true or
complement, along with varied feedback paths.
Traditionally, CPLDs have used analog sense amplifiers to boost the performance of their architectures. This performance boost came at
the cost of very high current requirements. CoolRunner™-II CPLDs, created by Xilinx, use an innovative all-digital core to achieve the
same levels of performance at ultra-low power requirements. This allows designers to use the same CPLD architecture for both high-
performance and low-power designs.
The removal of analog sense amplifiers also makes the architecture scalable, allowing for aggressive cost reduction and feature
enhancement with each successive process generation.
CPLD Block Structure

CPLD Benefits
CPLDs perform a variety of useful functions in systems design due to their unique capabilities and as the market leader in programmable
logic solutions, Xilinx provides a total solution to a designer's CPLD needs.

A complex programmable logic device (CPLD) is a programmable logic device with complexity between that of PALs and FPGAs, and
architectural features of both. The building block of a CPLD is the macro cell, which contains logic implementing disjunctive normal
form expressions and more specialized logic operations.
Features in common with PALs:

      Non-volatile configuration memory. Unlike many FPGAs, an external configuration ROM isn't required, and the CPLD can function
    immediately on system start-up.
      For many legacy CPLD devices, routing constrains most logic blocks to have input and output signals connected to external pins,
    reducing opportunities for internal state storage and deeply layered logic. This is usually not a factor for larger CPLDs and newer
    CPLD product families.

Features in common with FPGAs:

       Large number of gates available. CPLDs typically have the equivalent of thousands to tens of thousands of logic gates, allowing
    implementation of moderately complicated data processing devices. PALs typically have a few hundred gate equivalents at most, while
    FPGAs typically range from tens of thousands to several million.
       Some provisions for logic more flexible than sum-of-product expressions, including complicated feedback paths between macro
    cells, and specialized logic for implementing various commonly-used functions, such as integer arithmetic.
The most noticeable difference between a large CPLD and a small FPGA is the presence of on-chip non-volatile memory in the CPLD.
This distinction is rapidly becoming less relevant, as several of the latest FPGA products also offer models with embedded configuration

The characteristic of non-volatility makes the CPLD the device of choice in modern digital designs to perform 'boot loader' functions before
handing over control to other devices not having this capability. A good example is where a CPLD is used to load configuration data for an
FPGA from non-volatile memory.

CPLDs were an evolutionary step from even smaller devices that preceded them, PLAs (first shipped by Signetics), and PALs. These in
turn were preceded by standard logic products, that offered no programmability and were "programmed" by wiring several standard logic
chips together.
The main distinction between FPGA and CPLD device architectures is that FPGAs are internally based on look-up tables (LUTs) while
CPLDs form the logic functions with sea-of-gates (for example, sum of products).

Application-specific integrated circuit (ASIC)
                                     A tray of Application-specific integrated circuit (ASIC) chips
An application-specific integrated circuit, or ASIC /ˈeɪsɪk/, is an integrated circuit (IC) customized for a particular use, rather than
intended for general-purpose use. For example, a chip designed to run in a digital voice recorder is an ASIC. Application-specific standard
products (ASSPs) are intermediate between ASICs and industry standard integrated circuits like the 7400 or the 4000 series.
As feature sizes have shrunk and design tools improved over the years, the maximum complexity (and hence functionality) possible in an
ASIC has grown from 5,000 gates to over 100 million. Modern ASICs often include entire microprocessors, memory blocks
includingROM, RAM, EEPROM, Flash and other large building blocks. Such an ASIC is often termed a SoC (system-on-chip). Designers
of digital ASICs use a hardware description language(HDL), such as Verilog or VHDL, to describe the functionality of ASICs.
Field-programmable gate arrays (FPGA) are the modern-day technology for building abreadboard or prototype from standard parts;
programmable logic blocks and programmable interconnects allow the same FPGA to be used in many different applications. For smaller
designs and/or lower production volumes, FPGAs may be more cost effective than an ASIC design even in production. The non-recurring
engineering (NRE) cost of an ASIC can run into the millions of dollars.

Erasable programmable logic device (EPLD)
An Erasable programmable logic device (EPLD) is an integrated circuit that comprises an array of programmable logic devices(PLD)
that do not come pre-connected; the connections are programmed electrically by the user.

Simple programmable logic device (SPLD)

A simple programmable logic device (SPLD) is a programmable logic device with complexity below that of a complex programmable
logic device (CPLD).
The term commonly refers to devices such as ROMs, PALs, PLAs and GALs.
A macrocell array is an approach to the design and manufacture of ASICs. Essentially, it is a small step up from the otherwise similargate
array, but rather than being a prefabricated array of simple logic gates, the macrocell array is a prefabricated array of higher-level logic
functions such as flip-flops, ALU functions, registers, and the like. These logic functions are simply placed at regular predefined positions
and manufactured on a wafer, usually called master slice. Creation of a circuit with a specified function is accomplished by adding metal
interconnects to the chips on the master slice late in the manufacturing process, allowing the function of the chip to be customised as
Macrocell array master slices are usually prefabricated and stockpiled in large quantities regardless of customer orders. The fabrication
according to the individual customer specifications may be finished in a shorter time compared with standard cell or full custom design.
The macrocell array approach reduces the mask costs since fewer custom masks need to be produced. In addition manufacturing test
tooling lead time and costs are reduced since the same test fixtures may be used for all macrocell array products manufactured on the
same die size.
Drawbacks are somewhat low density and performance than other approaches to ASIC design. However this style is often a viable
approach for low production volumes.
Programmable Array Logic (PAL)

The term Programmable Array Logic (PAL) is used to describe a family of programmable logic device semiconductors used to
implement logic functions in digital circuits introduced by Monolithic Memories, Inc. (MMI) in March 1978.[1] MMI obtained a registered
trademark on the term PAL for use in "Programmable Semiconductor Logic Circuits". The trademark is currently held by Lattice
 PAL devices consisted of a small PROM (programmable read-only memory) core and additional output logic used to implement particular
desired logic functions with few components.
Using specialized machines, PAL devices were "field-programmable". Each PAL device was "one-time programmable" (OTP), meaning
that it could not be updated and reused after its initial programming. (MMI also offered a similar family called HAL, or "hard array logic",
which were like PAL devices except that they were mask-programmed at the factory.)
PAL architecture

The programmable elements (shown as a fuse) connect both the true and complemented inputs to the AND gates. These AND gates, also
known as product terms, are ORed together to form a sum-of-products logic array.
The PAL architecture consists of two main components: a logic plane and output logic macrocells.

Programmable logic plane
The programmable logic plane is a programmable read-only memory(PROM) array that allows the signals present on the devices pins (or
the logical complements of those signals) to be routed to an output logic macrocell.
PAL devices have arrays of transistor cells arranged in a "fixed-OR, programmable-AND" plane used to implement "sum-of-products"
binary logic equations for each of the outputs in terms of the inputs and either synchronous or asynchronous feedback from the outputs.

Programming PALs

PALs were programmed electrically using binary patterns (as JEDEC ASCII/hexadecimal files) and a special electronic programming
system available from either the manufacturer or a third-party, such as DATA/IO. In addition to single-unit device programmers, device
feeders and gang programmers were often used when more than just a few PALs needed to be programmed. (For large volumes,
electrical programming costs could be eliminated by having the manufacturer fabricate a custom metal mask used to program the
customers' patterns at the time of manufacture; MMI used the term "hard array logic" (HAL) to refer to devices programmed in this way.)

Though some engineers programmed PAL devices by manually editing files containing the binary fuse pattern data, most opted to design
their logic using a hardware description language (HDL) such as Data I/O's ABEL, Logical Devices' CUPL, or MMI's PALASM. These
were computer-assisted design (CAD) (now referred to as "electronic design automation") programs which translated (or "compiled") the
designers' logic equations into binary fuse map files used to program (and often test) each device.
The PALASM (from "PAL assembler") language was used to express boolean equations for the output pins in a text file which was then
converted to the 'fuse map' file for the programming system using a vendor-supplied program; later the option of translation from
schematics became common, and later still, 'fuse maps' could be 'synthesized' from an HDL(hardware description language,) such
as Verilog.
The PALASM compiler was written by MMI in FORTRAN IV on an IBM 370/168. MMI made the source code available to users at no cost.
By 1983, MMI customers ran versions on theDEC PDP-11, Data General NOVA, Hewlett-Packard HP 2100, MDS800 and others.
Data I/O Corporation released ABEL.
Logical Devices, Inc. released the Universal Compiler for Programmable Logic (CUPL), which ran under MSDOS on the IBM PC and is
currently available as an integrated development package for Microsoft Windows.
Device programmers
Popular device programmers included Data I/O Corporation's Model 60A Logic Programmer and Model 2900.
One of the very first PAL Programmers was the Structured Design "SD-20". They had the PALASM software built-in and only required a
CRT terminal to enter the equations and view the fuse plots. After fusing, the outputs of the PAL could be verified if test vectors were
entered in the source file.

Programmable logic array (PAL)
A programmable logic array (PLA) is a kind of programmable logic device used to implement combinational logic circuits. The PLA has a
set of programmable AND gate planes, which link to a set of programmable OR gate planes, which can then be conditionally
complemented to produce an output. This layout allows for a large number of logic functions to be synthesized in the sum of products (and
sometimes product of sums) canonical forms.
Implementation procedure

    1.   Prepare the truth table
    2.   Write the Boolean expression in SOP (sum of products) form.
    3.   Obtain the minimum SOP form to reduce the number of product terms to a minimum.
    4.   Decide the input connection of the AND matrix for generating the required product term.
    5.   Then decide the input connections of OR matrix to generate the sum terms.
    6.   Decide the connections of invert matrix.
    7.   Program the PLA.
PLA block diagram:
 1ST BLOCK        2ND BLOCK 3RD BLOCK                      4TH BLOCK                         5TH BLOCK


Why PLA over Read-only memory

A combinational circuit Combinational logic may occasionally have don't-care conditions. When implemented with a Read-only memory, a
don't care condition becomes an address input that will never occur. The words at the don't care address need not be programmed and
may be left in their original state(all 0's or all 1's ). The result is not all the bit patterns available in Read-only memory are used which may
be considered a waste of available component

One application of a PLA is to implement the control over a datapath. It defines various states in an instruction set, and produces the next
state (by conditional branching). [e.g. if the machine is in state 2, and will go to state 4 if the instruction contains an immediate field; then
the PLA should define the actions of the control in state 2, will set the next state to be 4 if the instruction contains an immediate field, and
will define the actions of the control in state 4]. Programmable logic arrays should correspond to a state diagramfor the system.
Other commonly used programmable logic devices are PAL, CPLD and FPGA.
Note that the use of the word "programmable" does not indicate that all PLAs are field-programmable; in fact many are mask-programmed
during manufacture in the same manner as a mask ROM. This is particularly true of PLAs that are embedded in more complex and
numerous integrated circuits such as microprocessors. PLAs that can be programmed after manufacture are called FPGA(Field-
programmable gate array), or less frequently FPLA (Field-programmable logic array).

Programmable logic device (PLD)
A simplified PAL device. The programmable elements (shown as a fuse) connect both the true and complemented inputs to the AND
gates. These AND gates, also known as product terms, are ORed together to form a sum-of-products logic array.
A programmable logic device or PLD is an electronic component used to build reconfigurable digital circuits. Unlike a logic gate, which
has a fixed function, a PLD has an undefined function at the time of manufacture. Before the PLD can be used in a circuit it must be
programmed, that is, reconfigured.
Using a ROM as a PLD

Before PLDs were invented, read-only memory (ROM) chips were used to create arbitrary combinational logic functions of a number of
inputs. Consider a ROM with m inputs (the address lines) and n outputs (the data lines). When used as a memory, the ROM contains
 words of n bits each. Now imagine that the inputs are driven not by an m-bit address, but by m independent logic signals. Theoretically,
there are 22m possible Boolean functions of these m signals, but the structure of the ROM allows just of these functions to be produced
at the output pins. The ROM therefore becomes equivalent to n separate logic circuits, each of which generates a chosen function of
the m inputs.
The advantage of using a ROM in this way is that any conceivable function of the m inputs can be made to appear at any of the noutputs,
making this the most general-purpose combinational logic device available. Also, PROMs (programmable ROMs), EPROMs(ultraviolet-
erasable PROMs) and EEPROMs (electrically erasable PROMs) are available that can be programmed using a standard PROM
programmer without requiring specialised hardware or software. However, there are several disadvantages:

      they are usually much slower than dedicated logic circuits,
      they cannot necessarily provide safe "covers" for asynchronous logic transitions so the PROM's outputs may glitch as the inputs
      they consume more power,
      they are often more expensive than programmable logic, especially if high speed is required.
Since most ROMs do not have input or output registers, they cannot be used stand-alone for sequential logic. An external TTL register
was often used for sequential designs such as state machines. Common EPROMs, for example the 2716, are still sometimes used in this
way by hobby circuit designers, who often have some lying around. This use is sometimes called a 'poor man's PAL'.
could implement multilevel or sequential circuits of over 100 gates. The device was supported by a GE design environment where Boolean
equations would be converted to mask patterns for configuring the device. The part was never brought to market.[8]


Lattice GAL 16V8 and 20V8
An innovation of the PAL was the generic array logic device, or GAL, invented by Lattice Semiconductor in 1985. This device has the
same logical properties as the PAL but can be erased and reprogrammed. The GAL is very useful in the prototyping stage of a design,
when any bugs in the logic can be corrected by reprogramming. GALs are programmed and reprogrammed using a PAL programmer, or
by using the in-circuit programming technique on supporting chips.
Lattice GALs combine CMOS and electrically erasable (E^2) floating gate technology for a high-speed, low-power logic device.
A similar device called a PEEL (programmable electrically erasable logic) was introduced by the International CMOS Technology (ICT)
Complex programmable logic device CPLDs

PALs and GALs are available only in small sizes, equivalent to a few hundred logic gates. For bigger logic circuits, complex PLDs
orCPLDs can be used. These contain the equivalent of several PALs linked by programmable interconnections, all in one integrated
circuit. CPLDs can replace thousands, or even hundreds of thousands, of logic gates.
Some CPLDs are programmed using a PAL programmer, but this method becomes inconvenient for devices with hundreds of pins. A
second method of programming is to solder the device to its printed circuit board, then feed it with a serial data stream from a personal
computer. The CPLD contains a circuit that decodes the data stream and configures the CPLD to perform its specified logic function.

Field-programmable gate array

An example of a Xilinx Spartan 6 FPGA programming/evaluation board

An Altera Stratix IV GX FPGA
A field-programmable gate array (FPGA) is an integrated circuit designed to be configured by a customer or a designer after
manufacturing—hence "field-programmable". The FPGA configuration is generally specified using ahardware description language (HDL),
similar to that used for an application-specific integrated circuit (ASIC) (circuit diagrams were previously used to specify the configuration,
as they were for ASICs, but this is increasingly rare). FPGAs can be used to implement any logical function that an ASIC could perform.
The ability to update the functionality after shipping, partial re-configuration of a portion of the design[1] and the low non-recurring
engineering costs relative to an ASIC design (notwithstanding the generally higher unit cost), offer advantages for many applications.[2]
FPGAs contain programmable logic components called "logic blocks", and a hierarchy of reconfigurable interconnects that allow the blocks
to be "wired together"—somewhat like many (changeable) logic gates that can be inter-wired in (many) different configurations. Logic
blocks can be configured to perform complex combinational functions, or merely simple logic gates likeAND and XOR. In most FPGAs, the
logic blocks also include memory elements, which may be simple flip-flops or more complete blocks of memory.[2]
In addition to digital functions, some FPGAs have analog features. The most common analog feature is programmable slew rate and drive
strength on each output pin, allowing the engineer to set slow rates on lightly loaded pins that would otherwise ring unacceptably, and to
set stronger, faster rates on heavily loaded pins on high-speed channels that would otherwise run too slow.[3][4]Another relatively common
analog feature is differential comparators on input pins designed to be connected to differential signaling channels. A few "mixed
signal FPGAs" have integrated peripheral analog-to-digital converters (ADCs)and digital-to-analog converters (DACs) with analog signal
conditioning blocks allowing them to operate as a system-on-a-chip.[5] Such devices blur the line between an FPGA, which carries digital
ones and zeros on its internal programmable interconnect fabric, and field-programmable analog array (FPAA), which carries analog
values on its internal programmable interconnect fabric.


VHDL (VHSIC hardware description language) is a hardware description languageused in electronic design automation to
describe digital and mixed-signal systems such asfield-programmable gate arrays and integrated circuits.
Verilog, standardized as IEEE 1364, is a hardware description language (HDL) used to model electronic systems. It is most commonly
used in the design and verification ofdigital circuits at the register-transfer level of abstraction. It is also used in the verification of analog
circuits and mixed-signal circuits.
Hardware description languages such as Verilog differ from software programming languages because they include ways of describing the
propagation of time and signal dependencies (sensitivity). There are two assignment operators, a blocking assignment (=), and a non-
blocking (<=) assignment. The non-blocking assignment allows designers to describe a state-machine update without needing to declare
and use temporary storage variables. Since these concepts are part of Verilog's language semantics, designers could quickly write
descriptions of large circuits in a relatively compact and concise form. At the time of Verilog's introduction (1984), Verilog represented a
tremendous productivity improvement for circuit designers who were already using graphical schematic capture software and specially
written software programs to document and simulate electronic circuits.
The designers of Verilog wanted a language with syntax similar to the C programming language, which was already widely used in
engineering software development. Like C, Verilog is case-sensitive and has a basic preprocessor (though less sophisticated than that of
ANSI C/C++). Its control flow keywords (if/else, for, while, case, etc.) are equivalent, and its operator precedence is compatible. Syntactic
differences include variable declaration (Verilog requires bit-widths on net/reg types[clarification needed]), demarcation of procedural blocks
(begin/end instead of curly braces {}), and many other minor differences.
A Verilog design consists of a hierarchy of modules. Modules encapsulate design hierarchy, and communicate with other modules through
a set of declared input, output, and bidirectional ports. Internally, a module can contain any combination of the following: net/variable
declarations (wire, reg, integer, etc.), concurrent and sequential statement blocks, and instances of other modules (sub-hierarchies).
Sequential statements are placed inside a begin/end block and executed in sequential order within the block. However, the blocks
themselves are executed concurrently, making Verilog a dataflow language.
Verilog's concept of 'wire' consists of both signal values (4-state: "1, 0, floating, undefined") and strengths (strong, weak, etc.). This system
allows abstract modeling of shared signal lines, where multiple sources drive a common net. When a wire has multiple drivers, the wire's
(readable) value is resolved by a function of the source drivers and their strengths.
A subset of statements in the Verilog language are synthesizable. Verilog modules that conform to a synthesizable coding style, known as
RTL (register-transfer level), can be physically realized by synthesis software. Synthesis software algorithmically transforms the (abstract)
Verilog source into a netlist, a logically equivalent description consisting only of elementary logic primitives (AND, OR, NOT, flip-flops, etc.)
that are available in a specific FPGA or VLSI technology. Further manipulations to the netlist ultimately lead to a circuit fabrication blueprint
(such as a photo mask set for an ASIC or a bitstream file for an FPGA).
With the increasing success of VHDL at the time, Cadence decided to make the language available for open standardization. Cadence
transferred Verilog into the public domain under the Open Verilog International (OVI) (now known as Accellera) organization. Verilog was
later submitted to IEEE and became IEEE Standard 1364-1995, commonly referred to as Verilog-95.
In the same time frame Cadence initiated the creation of Verilog-A to put standards support behind its analog simulator Spectre. Verilog-A
was never intended to be a standalone language and is a subset of Verilog-AMS which encompassed Verilog-95.
Verilog 2001
Extensions to Verilog-95 were submitted back to IEEE to cover the deficiencies that users had found in the original Verilog standard.
These extensions became IEEE Standard 1364-2001 known as Verilog-2001.
Verilog-2001 is a significant upgrade from Verilog-95. First, it adds explicit support for (2's complement) signed nets and variables.
Previously, code authors had to perform signed operations using awkward bit-level manipulations (for example, the carry-out bit of a
simple 8-bit addition required an explicit description of the Boolean algebra to determine its correct value). The same function under
Verilog-2001 can be more succinctly described by one of the built-in operators: +, -, /, *, >>>. A generate/endgenerate construct (similar to
VHDL's generate/endgenerate) allows Verilog-2001 to control instance and statement instantiation through normal decision operators
(case/if/else). Using generate/endgenerate, Verilog-2001 can instantiate an array of instances, with control over the connectivity of the
individual instances. File I/O has been improved by several new system tasks. And finally, a few syntax additions were introduced to
improve code readability (e.g. always @*, named parameter override, C-style function/task/module header declaration).
Verilog-2001 is the dominant flavor of Verilog supported by the majority of commercial EDA software packages.
Verilog 2005
Not to be confused with SystemVerilog, Verilog 2005 (IEEE Standard 1364-2005) consists of minor corrections, spec clarifications, and a
few new language features (such as the uwire keyword).
A separate part of the Verilog standard, Verilog-AMS, attempts to integrate analog and mixed signal modeling with traditional Verilog.

SystemVerilog is a superset of Verilog-2005, with many new features and capabilities to aid design verification and design modeling. As of
2009, the SystemVerilog and Verilog language standards were merged into SystemVerilog 2009 (IEEE Standard 1800-2009).
The advent of hardware verification languages such as OpenVera, and Verisity's e language encouraged the development
of Superlog byCo-Design Automation Inc. Co-Design Automation Inc was later purchased by Synopsys. The foundations of Superlog and
Vera were donated to Accellera, which later became the IEEE standard P1800-2005: SystemVerilog.

Note: These operators are not shown in order of precedence.
Operator type Operator symbols        Operation performed

             ~                   Bitwise NOT (1's complement)

             &                   Bitwise AND

Bitwise      |                   Bitwise OR

             ^                   Bitwise XOR

             ~^ or ^~            Bitwise XNOR

                 !               NOT

Logical      &&                  AND

             ||                  OR

             &                   Reduction AND

             ~&                  Reduction NAND
             |                   Reduction OR

             ~|                  Reduction NOR
Four-valued logic

The IEEE 1364 standard defines a four-valued logic with four states: 0, 1, Z (high impedance), and X (unknown logic value). For the
competing VHDL, a dedicated standard for multi-valued logic exists as IEEE 1164 with nine levels.

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